TEXAS INSTRUMENTS TMS28F010A Technical data
查询TMS28F010A-10供应商
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS28F010A
1048576-BIT FLASH
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
• Organization . . . 128K × 8-Bit Flash Memory
• Pin Compatible With Existing 1-Megabit
EPROMs
• V
Tolerance ±10%
CC
• All Inputs/Outputs TTL Compatible
• Maximum Access/Minimum Cycle Time
’28F010A-10 100 ns
’28F010A-12 120 ns
’28F010A-15 150 ns
’28F010A-17 170 ns
• Industry-Standard Programming Algorithm
• PEP4 Version Available With 168-Hour
Burn-In and Choice of Operating
T emperature Ranges
• Chip Erase Before Reprogramming
• 10000 and 1000 Program/Erase-Cycle
Versions Available
• Low Power Dissipation (V
= 5.5 V)
CC
– Active Write . . . 55 mW
– Active Read...165 mW
– Electrical Erase...82.5 mW
– Standby...0.55 mW
(CMOS-Input Levels)
• Automotive Temperature Range
description
– 40°C to 125°C
The TMS28F010A is a 1048576-bit, programmable read-only memory that can be electrically
bulk-erased and reprogrammed. It is available in
10000 and 1000 program/erase-endurancecycle versions.
The TMS28F010A Flash EEPROM is offered in a
dual in-line plastic package (N suffix) designed for
insertion in mounting-hole rows on 15,2-mm
(600-mil) centers, a 32-lead plastic leaded
chip-carrier package using 1,25-mm (50-mil) lead
spacing (FM suffix), a 32-lead thin small-outline
package (DD suffix), and a reverse pinout TSOP
package (DU suffix).
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
N PACKAGE
(TOP VIEW)
V
1
PP
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
13
DQ1
14
DQ2
15
V
16
SS
FM PACKAGE
(TOP VIEW)
A12
A15
A16
3213231
430
5
6
7
8
9
10
11
12
13
14
15 16 17 18 19
SS
DQ1
DQ2
V
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PPVCC
V
DQ3
DQ4
V
CC
W
NC
A14
A13
A8
A9
A1 1
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
W
20
DQ5
NC
29
28
27
26
25
24
23
22
21
DQ6
A14
A13
A8
A9
A1 1
G
A10
E
DQ7
The TMS28F010A is characterized for operation
in temperature ranges of 0°C to 70°C (NL, FML,
DDL, and DUL suffixes), –40°C to 85°C (NE, FME,
DDE, and DUE suffixes), and –40°C to 125°C
(NQ, FMQ, DDQ, and DUQ suffixes). All package
types are offered with 168-hour burn-in (4 suffix).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
A0–A16 Address Inputs
DQ0–DQ7 Data In/Data Out
E
G
NC No Internal Connection
V
CC
V
PP
V
SS
W
• HOUSTON, TEXAS 77251–1443
PIN NOMENCLATURE
Chip Enable
Output Enable
5-V Power Supply
12-V Power Supply
Ground
Write Enable
Copyright 1993, Texas Instruments Incorporated
1
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
DD PACKAGE
(TOP VIEW)
A11
A9
A8
A13
A14
NC
W
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4
A10
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A1 1
A9
A8
A13
A14
NC
W
V
CC
V
PP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DU PACKAGE
REVERSE PINOUT
(TOP VIEW)
1
G
2
3
E
4
5
6
7
8
9
10
11
12
13
14
15
16
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
device symbol nomenclature
-12 C4 FM L 4TMS28F010A
TMS28F010A
1048576-BIT FLASH
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
PEP4 Burn-In
4 = 168-Hour Burn-In
(blank if no burn-in)
Temperature Range Designator
L= 0°Cto70°C
E=–40°Cto85°C
Q=–40°C to 125°C
Package Designator
N = Plastic Dual In-Line Package
FM = Plastic Leaded Chip Carrier
DD = Thin Small-Outline Package
DU = Thin Small-Outline Package,
Reverse Pinout
Program/Erase Endurance
C4 = 10 000 Cycles
C3 = 1 000 Cycles
Speed Designator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the N package.
†
FLASH
EEPROM
131 072 × 8
0
A
131 071
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
E
24
G
31
W
13
14
15
17
18
19
20
21
0
16
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇ 4
A, Z4
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
functional block diagram
TMS28F010A
1048576-BIT FLASH
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
DQ0–DQ7
V
PP
A0–A16
Erase-Voltage Switch
W
E
G
State Control
Program/Erase
Stop Timer
Command Register
17
To Array
Program-Voltage
Switch
STB
A
d
d
r
e
s
s
L
a
t
c
h
STB
Chip-Enable and
Output-Enable
Logic
Column Decoder
Row Decoder
Input/Output Buffers
8
Data Latch
Column Gating
1048576-Bit
Array Matrix
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
5
TMS28F010A
Algorithm-Selection Mode
V
VILV
VIDV
IDENTIFIER
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
Table 1. Operation Modes
FUNCTION
MODE
Read V
Output Disable V
Read
Read/
Write
NOTE: X can be VIL or VIH.
†
V
PPL
Standby and Write Inhibit V
Read V
Output Disable V
Standby and Write Inhibit V
Write V
≤ VCC + 2 V; V
PPH
operation
read/output disable
is the programming voltage specified for the device. For more details, refer to the recommended operating conditions.
V
PP
(1)
PPL
PPL
PPL
PPL
PPH
PPH
PPH
PPH
†
E
(22)
V
V
V
IH
V
V
V
IH
V
G
(24)
IL
IL
IL
IL
IL
V
IL
V
IH
X X X
IL
V
IL
V
IH
X X X
V
IH
A0
(12)
X X
X X
V
IL
V
IH
X X
X X
X X
A9
(26)
W
(31)
V
IH
V
IH
X
IH
V
IH
V
IH
X
V
IL
DQ0–DQ7
(13–15, 17–21)
Data Out
HI-Z
HI-Z
Mfr Equivalent Code 89h
Device Equivalent Code B4h
Data Out
HI-Z
HI-Z
Data In
When the outputs of two or more TMS28F010As are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. T o
read the output of the TMS28F010A, a low-level signal is applied to the E
and G pins. All other devices in the
circuit should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write inhibit
Active I
high CMOS level on E
current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 µA with a
CC
. In this mode, all outputs are in the high-impedance state. The TMS28F010A draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
agorithms. This mode is activated when A9 (pin 26) is forced to V
A0. All other addresses must be held low.
A0 low selects the manufacturer equivalent code 89h, and A0 high
. Two identifier bytes are accessed by toggling
ID
selects the device equivalent code B4h, as shown in the algorithm-selection mode table below:
PINS
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
Manufacturer Equivalent Code V
Device Equivalent Code V
NOTE: E = G = VIL, A1–A8 = VIL, A9 = VID, A10–A16 = VIL, VPP = V
IL
IH
1 0 0 0 1 0 0 1 89
1 0 1 1 0 1 0 0 B4
.
PPL
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Afterwards, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F010A
COMMAND
BUS
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
command register
The command register controls the program and erase functions of the TMS28F010A. The algorithm-selection
mode can be activated using the command register in addition to the above method. When V
contents of the command register and the function being performed can be changed. The command register
is written to when E
is low and W is pulsed low. The address is latched on the leading edge of the pulse, while
the data is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to invoke either operation.
power supply considerations
PP
is high, the
Each device should have a 0.1-µF ceramic capacitor connected between V
Changes in current drain on V
require it to have a bypass capacitor as well. Printed-circuit traces for both
PP
and VSS to suppress circuit noise.
CC
power supplies should be appropriate to handle the current demand.
Table 2. Command Definitions
REQUIRED
CYCLES
Read 1 Write X 00h Read RA RD
Algorithm-Selection Mode 3 Write X 90h Read
Set-Up-Erase/Erase 2 Write X 20h Write X 20h
Erase Verify 2 Write EA A0h Read X EVD
Set-Up-Program/Program 2 Write X 40h Write PA PD
Program Verify 2 Write X C0h Read X PVD
Reset 2 Write X FFh Write X FFh
†
Modes of operation are defined in Table 1.
Legend:
EA Address of memory location to be read during erase verify.
RA Address of memory location to be read.
PA Address of memory location to be programmed. Address is latched on the falling edge of W
RD Data read from location RA during the read operation.
EVD Data read from location EA during erase verify.
PD Data to be programmed at location PA. Data is latched on the rising edge of W
PVD Data read from location PA during program verify.
OPERATION†ADDRESS DATA OPERATION†ADDRESS DATA
FIRST BUS CYCLE SECOND BUS CYCLE
0000
0001
.
.
89h
B4h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
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