Texas Instruments TMS27C512-10JE, TMS27PC512-25FML, TMS27PC512-25FME, TMS27PC512-20FML, TMS27PC512-20FME Datasheet

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TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

Organization...65536 by 8 Bits

Single 5-V Power Supply

Pin Compatible With Existing 512K MOS ROMs, PROMs, and EPROMs

All Inputs/Outputs Fully TTL Compatible

Max Access/Min Cycle Time

± 10%

’27C/PC512-10 100 ns ’27C/PC512-12 120 ns ’27C/PC512-15 150 ns ’27C/PC512-20 200 ns ’27C/PC512-25 250 ns

Power Saving CMOS Technology

Very High-Speed SNAP! Pulse Programming

3-State Output Buffers

400-mV Minimum DC Noise Immunity With Standard TTL Loads

Latchup Immunity of 250 mA on All Input and Output Lines

Low Power Dissipation ( VCC = 5.25 V ) – Active . . . 158 mW Worst Case – Standby...1.4 mW Worst Case

(CMOS Input Levels)

Temperature Range Options

512K EPROM Available With MIL-STD-883C Class B High Reliability Processing (SMJ27C512)

description

The TMS27C512 series are 65536 by 8-bit (524288-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs).

The TMS27PC512 series are 65536 by 8-bit (524288-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs).

J PACKAGE (TOP VIEW)

A15

A12

DQ0

DQ1

DQ2

GND

A4 A3

DQ0

A0–A15 Address Inputs E Chip Enable/Power Down DQ0–DQ7 Inputs (programming)/Outputs

GND Ground NC No Internal Connection NU Make No External Connection V

FM PACKAGE

(TOP VIEW)

A12

A15NUV

3213231

430

15 16 17 18 19

DQ1

DQ2NUDQ3

GND

PIN NOMENCLATURE

13-V Programming Power Supply

5-V Power Supply

28 27 26 25 24 23 22 21 20 19 18 17 16 15

A14 A13 A8 A9 A1 1 G

/V A10 E DQ7 DQ6 DQ5 DQ4 DQ3

A14

DQ4

A13

29 28 27 26 25 24 23 22 21

DQ5

A8 A9 A1 1 NC G

/V A10 E DQ7 DQ6

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

description (continued)

These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external resistors.

The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C512 and the TMS27PC512 are pin compatible with 28-pin 512K MOS ROMs, PROMs, and EPROMs.

The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 OTP PROM is supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).

The TMS27C512 and TMS27PC512 are offered with two choices of temperature ranges of 0°C to 70°C (JL and FML suffix) and – 40°C to 85°C (JE and FME suffix). See Table 1.

All package styles conform to JEDEC standards.

Table 1. Temperature Range Suffixes

EPROM

AND

OTP PROM

TMS27C512-xxx JL JE TMS27PC512-xxx FML FME

SUFFIX FOR OPERATING

FREE-AIR TEMPERATURE RANGES

0°C TO 70°C –40°C TO 85°C

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals are TTL level. The device is programmed using the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a V

of 13 V and a VCC of 6.5 V for a nominal programming time of seven seconds.

For programming outside the system, existing EPROM programmers can be used. Locations can be programmed singly, in blocks, or at random.

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TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

operation

The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are TTL level except for V

FUNCTION

E V

G/V

A9 X X X X X X V A0 X X X X X X V

DQ0–DQ7 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z

†

X can be VIL or VIH.

‡

VH = 12 V ± 0.5 V.

READ

during programming (13 V for SNAP! Pulse) and 12 V on A9 for signature mode.

Table 2. Operation Modes

†

MODE

OUTPUT

DISABLE

STANDBY PROGRAMMING VERIFY

X V

PROGRAM

INHIBIT

SIGNATURE

MODE

V V

‡

CODE

MFG DEVICE

97 85

IL IL

‡

read/output disable

When the outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. T o read the output of a single device, a low-level signal is applied to the E

and G/VPP pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7.

latchup immunity

Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P .C. board level when the devices are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup without compromising performance or packing density.

power down

Active I inputs) by applying a high TTL/CMOS signal to the E

supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level

pin. In this mode all outputs are in the high-impedance

state.

erasure (TMS27C512)

Before programming, the TMS27C512 EPROM is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity × exposure time) is 15-W⋅s/cm

. A typical 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C512, the window should be covered with an opaque label.

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TMS27C512 65536 BY 8-BIT UV ERASABLE

IDENTIFIER

†

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

initializing (TMS27PC512)

The one-time programmable TMS27PC512 PROM is provided with all bits in the logic high state, then logic lows are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.

SNAP! Pulse programming

The 512K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm illustrated by the flowchart in Figure 1, which programs in a nominal time of seven seconds. Actual programming time varies as a function of the programmer used.

The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs pulses per byte are provided before a failure is recognized.

The programming mode is achieved with G (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E

/VPP= 13 V , VCC= 6.5 V , and E =VIL. Data is presented in parallel

is pulsed.

More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with V

= 5 V, G/VPP = V

and E = VIL.

IL,

program inhibit

Programming can be inhibited by maintaining a high level input on the E

pin.

program verify

Programmed bits can be verified when G

/VPP and E = VIL.

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 is forced to 12 V . T wo identifier bytes are accessed by toggling A0. All other addresses must be held low. the signature code for these devices is 9785. A0 selects the manufacturer’s code 97 (Hex), and A0 high selects the device code 85, as shown in Table 3.

Table 3. Signature Mode

PINS

A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX

Manufacturer Code V

Device Code V

†

E = G = VIL, A9 = VH, A1–A8 = VIL, A10–A15 = VIL, PGM = VIH or VIL.

1 0 0 1 0 1 1 1 97

1 0 0 0 0 1 0 1 85

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TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

Start

Address = First Location

VCC = 6.5 V ± 0.25 V , G

Program One Pulse = tw = 100 µs

Increment

Address

/VPP = 13 V ± 0.25 V

Last

Address

Yes

Address = First Location

X = 0

Verify

One Byte

Pass

Fail

Increment Address

Program One Pulse = tw = 100 µs

X = 10?X = X + 1

Program

Mode

Interactive

Mode

VCC = 5 V ± 0.5 V, G

Last

Address

Yes Yes

/VPP = V

Compare

All Bytes

To Original

Data

Pass

Device Passed

Fail

Figure 1. SNAP! Pulse Programming Flow Chart

Device Failed

Final

Verification

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TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

logic symbols

A10

A11

A12

A13

A14

A15

G/V

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the J package.

†

15 [PWR DWN]

EPROM

65 536 × 8

65 535

OTP PROM

65 536 × 8

65 535

A A A A A A A A

11 12 13 15 16 17 18 19

G/V

A4 A5 A6 A7 A8

A9 A10 A11 A12 A13 A14 A15

5 4

3 25 24 21 23

2 26 27

1 20

A A A A A A A A

12 13 15 16 17 18 19

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

15 [PWR DWN]

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Supply voltage range, V Input voltage range (see Note 1): All inputs except A9 –0.6 V to V

Output voltage range (see Note 1) –0.6 V to V Operating free-air temperature range (’27C512-_ _JL, ’27PC512-_ _FML)T Operating free-air temperature range (’27C512-_ _JE, ’27PC512-_ _FME)T Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

(see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A9 –0.6 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0°C to 70°C. . . . . . . . . . . . . . .

–40°C to 85°C. . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

‡

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VCCSuppl

oltage

VIHHigh-level dc input voltage

VILLow-level dc input voltage

VOHHigh-level dc output voltage

VOLLow-level dc output voltage

pply current (standby)

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

recommended operating conditions

MIN NOM MAX UNIT

y v

G/V

NOTE 2: VCC must be applied before or at the same time as G/VPP and removed after or at the same time as G/VPP. The device must not be

Supply voltage SNAP! Pulse programming algorithm 12.75 13 13.25 V

Operating free-air temperature

inserted into or removed from the board when VPP or VCC is applied.

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Input current (leakage) VI = 0 V to 5.5 V ±1 µA

Output current (leakage) VO = 0 V to V

G/VPP supply current (during program pulse) G/VPP = 13 V 35 50 mA

CC1VCC

CC2VCC

†

Typical values are at TA = 25°C and nominal voltages.

supply current (active)

Read mode (see Note 2) 4.5 5 5.5 SNAP! Pulse programming algorithm 6.25 6.5 6.75

TTL 2 VCC+1 CMOS VCC– 0.2 VCC+1 TTL – 0.5 0.8 CMOS – 0.5 0.2 TMS27C512-_ _JL

TMS27PC512-_ _FML TMS27C512-_ _JE

TMS27PC512-_ _FME

IOH = – 2.5 mA 3.5 IOH = – 20 µA VCC– 0.1 IOL = 2.1 mA 0.4 IOL = 20 µA 0.1

TTL-input level VCC = 5.5 V, E = V CMOS-input level VCC = 5.5 V, E = V

VCC = 5.5 V, E = VIL, t

= minimum cycle time,

cycle

outputs open

. . . . . 250 500

. . . . . 100 250

IH CC

0 70 °C

–40 85 °C

±1 µA

15 30 mA

capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz

G/VPP

†

Capacitance measurements are made on a sample basis only.

‡

Typical values are at TA = 25°C and nominal voltages.

†

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

Input capacitance VI = 0 V, f = 1 MHz 6 10 pF Output capacitance VO = 0 V, f = 1 MHz 10 14 pF G/VPP input capacitance G/VPP = 0 V, f = 1 MHz 20 25 pF

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TMS27C512 65536 BY 8-BIT UV ERASABLE

(SEE NOTES 3 AND 4)

100 F

≤ 20

(SEE NOTES 3 AND 4)

100 F

(SEE NOTES 3 AND 4)

100 F

≤ 20

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

switching characteristics over recommended ranges of operating conditions

’27C512-10

’27PC512-10

MIN MAX MIN MAX

100 120 ns

55 55 ns

0 45 0 45 ns 0 0 ns

a(A)

a(E)

en(G)

dis

v(A)

PARAMETER

Access time from address 100 120 ns Access time from chip enable Output enable time from G/V Output disable time from G/VPP or E, whichever occurs first Output data valid time after change of address, E, or G/VPP,

whichever occurs first

†

TEST CONDITIONS

1 Series 74 TTL Load,

Input tr ≤ 20 ns,

†

nput

’27C512-12

’27PC512-12

UNIT

PARAMETER

a(A)

a(E)

en(G)

dis

v(A)

a(A)

a(E)

en(G)

dis

v(A)

†

Value calculated from 0.5 V delta to measured output level. This parameter is only sampled.

NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V . T iming measurements are made at 2 V for logic high and

Access time from address 150 ns Access time from chip enable Output enable time from G/V Output disable time from G/VPP or E, whichever occurs first Output data valid time after change of address, E, or G /VPP, whichever

occurs first

Access time from address 200 250 ns Access time from chip enable Output enable time from G/V Output disable time from G/VPP or E, whichever occurs first Output data valid time after change of address, E, or G/VPP,

whichever occurs first

0.8 V for logic low (see Figure 2).

4. Common test conditions apply for t

†

PARAMETER

†

except during programming.

dis

†

TEST CONDITIONS

1 Series 74 TTL Load,

Input tr ≤ 20 ns,

nput

TEST CONDITIONS

1 Series 74 TTL Load,

Input tr ≤ 20 ns,

nput

≤ 20 ns

’27C512-20

’27PC512-20

MIN MAX MIN MAX

0 60 0 60 ns 0 0 ns

’27C512-15

’27PC512-15

MIN MAX

0 60 ns 0 ns

’27C512-25

’27PC512-25

200 250 ns

75 100 ns

UNIT

150 ns

75 ns

UNIT

switching characteristics for programming: VCC = 6.50 V and G/VPP = 13 V (SNAP! Pulse),

= 25°C (see Note 3)

dis(G)

NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

Disable time, output from G/V

0.8 V for logic low.

PARAMETER MIN MAX UNIT

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0 130 ns

timing requirements for programming

w(IPGM)

su(A)

su(D)

su(VPP

su(VCC)

h(A)

h(D)

h(VPP)

rec(PG)

EHD

r(PG)G

Pulse duration, initial program 95 100 105 µs Setup time, address 2 µs Setup time, data 2 µs Setup time, G/V Setup time, V Hold time, address 0 µs Hold time, data 2 µs Hold time, G/V Recovery time, G/V Data valid from E low 1 µs Rise time, G/V

PARAMETER MEASUREMENT INFORMATION

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

MIN NOM MAX UNIT

2 µs 2 µs

50 ns

2.08 V

Output

Under Test

2.4 V

0.4 V

NOTES: A. CL includes probe and fixture capacitance.

B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low . Timing

measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs and outputs.

2 V

0.8 V

Figure 2. AC Testing Output Load Circuit

RL = 800 Ω

CL = 100 pF (see Note A)

2 V

0.8 V

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TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

A0–A15

G/V

DQ0–DQ7

Hi-Z

Addresses Valid

a(A)

a(E)

en(G)

Figure 3. Read-Cycle Timing

v(A)

Output Valid

dis

Hi-Z

A0–A15

su(A)

DQ0–DQ7

su(D)

su(VCC)

†

is a characteristic of the device but must be accommodated by the programmer.

dis(G)

‡

/VPP and 6.5-V VCC for SNAP! Pulse programming.

13-V G

r(PG)G

h(VPP)

su(VPP)

w(IPGM)

Address Stable

h(D)

rec(PG)

Data-Out ValidHi-ZData-In Stable

EHD

dis(G)

h(A)

IH/VOH

IL/VOL

†

‡

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

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TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER

Seating Plane

0.140 (3,56)

0.495 (12,57)

0.485 (12,32)

0.453 (11,51)

0.447 (11,35)

301

0.129 (3,28)

0.123 (3,12)

0.049 (1,24)

0.043 (1,09)

0.008 (0,20) NOM

0.132 (3,35)

0.004 (0,10)

0.050 (1,27)

0.020 (0,51)

0.015 (0,38)

0.595 (15,11)

0.585 (14,86)

0.553 (14,05)

0.547 (13,89)

0.030 (0,76) TYP

4040201-4/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-016

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TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

J (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PIN SHOWN

0.090 (2,29)

0.060 (1,53)

0.100 (2,54)

0.065 (1,65)

0.045 (1,14)

0.018 (0,46) MIN

0.022 (0,56)

0.014 (0,36)

0.175 (4,45)

0.140 (3,56)

Seating Plane

0.125 (3,18) MIN

Lens Protrusion

0.010 (0,25) MAX

0°–10°

0.012 (0,30)

0.008 (0,20)

DIM

NOTES: A. All linear dimensions are in inches (millimeters).

PINS**

MAX

MIN MAX

MIN

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.265(32,13) 1.265(32,13)

1.235(31,37) 1.235(31,37)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.465(37,21) 1.465(37,21)

1.435(36,45) 1.435(36,45)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

WIDE WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

1.668(42,37) 1.668(42,37)

1.632(41,45) 1.632(41,45)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

WIDE

NARR

0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99)

2.068(52,53) 2.068(52,53)

2.032(51,61) 2.032(51,61)

0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50)

4040084/B 04/95

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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Texas Instruments TMS27C512-10JE, TMS27PC512-25FML, TMS27PC512-25FME, TMS27PC512-20FML, TMS27PC512-20FME Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual