TEXAS INSTRUMENTS TMS27C020 Technical data
查询TMS27C020 262144供应商
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
D
Organization...262144 by 8 Bits
D
Single 5-V Power Supply
D
Operationally Compatible With Existing
Megabit EPROMs
D
Industry Standard 32-Pin Dual-In-line
Package and 32-Lead Plastic Leaded Chip
Carrier
D
All Inputs/Outputs Fully TTL Compatible
D
±10% VCC Tolerance
D
Max Access/Min Cycle Time
V
± 10%
CC
’27C/PC020-10 100 ns
’27C/PC020-12 120 ns
’27C/PC020-15 150 ns
’27C/PC020-20 200 ns
’27C/PC020-25 250 ns
D
8-Bit Output For Use in
Microprocessor-Based Systems
D
Very High-Speed SNAP! Pulse
Programming
D
Power Saving CMOS Technology
D
3-State Output Buffers
D
400 mV Minimum DC Noise Immunity With
Standard TTL Loads
D
Latchup Immunity of 250 mA on All Input
and Output Pins
D
No Pullup Resistors Required
D
Low Power Dissipation (VCC = 5.5 V)
– Active...165 mW Worst Case
– Standby...0.55 mW Worst Case
(CMOS-Input Levels)
D
Temperature Range Options
description
The TMS27C020 series are 262144 by 8-bit
(2097152-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
The TMS27PC020 series are one-time programmable (OTP) electrically programmable read-only
memories (PROMs).
J PACKAGE
(TOP VIEW)
V
1
PP
A16
2
A15
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
DQ0
13
DQ1
14
DQ2
15
GND
A7
5
A6
6
7
A5
8
A4
9
A3
10
A2
11
A1
12
A0
13
DQ0
A0–A17 Address Inputs
DQ0–DQ7 Inputs (programming)/Outputs
E
G
GND Ground
PGM
V
CC
V
PP
†Only in program mode
16
TMS27PC020
FM PACKAGE
(TOP VIEW)
A12
A15
A16
3213231
430
14
15 16 17 18 19
DQ1
DQ2
GND
PIN NOMENCLATURE
Chip Enable
Output Enable
Program
5-V Power Supply
13-V Power Supply
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PP
V
DQ3
CC
V
DQ4
V
CC
PGM
A17
A14
A13
A8
A9
A1 1
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
PGM
20
DQ5
A17
29
28
27
26
25
24
23
22
21
DQ6
†
A14
A13
A8
A9
A11
G
A10
E
DQ7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 1997, Texas Instruments Incorporated
1
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C020 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C020 is also offered with two choices of
temperature ranges of 0° to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). See Table 1.
The TMS27PC020 is offered in a 32-lead plastic leaded chip carrier using 1,25 mm (50 mil) lead spacing
(FM suffix). The TMS27PC020 is offered with two choices of temperature ranges of 0° C to 70°C (FML suffix)
and – 40°C to 85°C (FME suffix). See Table 1.
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING
FUNCTION
TMS27C040-XXX JL JE
TMS27PC040-XXX FML FME
TEMPERATURE RANGES
0°C TO 70°C –40 °C TO 85°C
These EPROMs operate from a single 5-V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation for the TMS27C020 and TMS27PC020 are listed in Table 2. The read mode
requires a single 5-V supply . All inputs are TTL level except for V
A9 for the signature mode.
Table 2. Operation Modes
MODE
FUNCTION
E V
G V
PGM X X X V
V
PP
V
CC
A9 X X X X X X VH‡ VH‡
A0 X X X X X X V
DQ0–DQ7 Data Out Hi-Z Hi-Z Data In Data Out Hi-Z
†
X can be VIL or V
‡
VH = 12 V ± 0.5 V
READ
IL
IL
X V
V
CC
IH
OUTPUT
DISABLE
V
IL
V
IH
CC
V
CC
STANDBY PROGRAMMING VERIFY
V
IH
X V
V
CC
V
CC
V
IL
IH
IL
V
PP
V
CC
during programming (13 V), and VH (12 V) on
PP
†
PROGRAM
INHIBIT
V
IL
V
IL
V
IH
V
PP
V
CC
V
IH
X V
X X
V
PP
V
CC
SIGNATURE MODE
V
V
IL
CODE
MFG DEVICE
97 32
V
IL
IL
CC
CC
V
IH
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
read/output disable
When the outputs of two or more TMS27C020s or TMS27PC020s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C020 and TMS72PC020 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
100 µA by applying a high CMOS input on E
erasure
Before programming, the TMS27C020 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose
(UV intensity × exposure time) is 15-W⋅s/cm
21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are
in the high state. It should be noted that normal ambient light contains the correct wavelength for erasure.
Therefore, when using the TMS27C020, the window should be covered with an opaque label. After erasure (all
bits in logic high state), logic lows are programmed into the desired locations. A programmed low can be erased
only by ultraviolet light.
supply current can be reduced from 30 mA to 500 µA by applying a high TTL input on E and to
CC
. In this mode all outputs are in the high-impedance state.
2
. A typical 12-mW/cm2, filterless UV lamp erases the device in
and G pins. All other
SNAP! Pulse programming
The TMS27C020 and TMS27PC020 are programmed using the TI SNAP! Pulse programming algorithm,
illustrated by the flowchart in Figure 1, which programs in a nominal time of twenty-six seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to ten 100-µs pulses
per byte are provided before a failure is recognized.
equals 13 V , VCC = 6.5 V, E = VIL, G = VIH. Data is presented
The programming mode is achieved when V
in parallel (eight bits) on pins DQ0 through DQ7. Once addresses and data are stable, PGM
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
= VPP = 5 V ± 10%.
V
CC
program inhibit
Programming can be inhibited by maintaining a high level input on the E
program verify
Programmed bits can be verified with V
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other
addresses must be held low. The signature code for the TMS27C020 is 9732. A0 low selects the manufacturer’s
code 97 (Hex), and A0 high selects the device code 32 (Hex), as shown in Table 3.
PP
PP
or PGM pins.
equals 13 V when G = VIL, E = VIL, and PGM = VIH.
is pulsed low.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
TMS27C020 262144 BY 8-BIT UV ERASABLE
IDENTIFIER
†
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
signature mode (continued)
Table 3. Signature Mode
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
MANUFACTURER CODE V
DEVICE CODE V
†
E
= G = VIL, A1–A8 = VIL, A9 = VH, A10–A17 = VIL, VPP = VCC.
IL
IH
1 0 0 1 0 1 1 1 97
0 0 1 1 0 0 1 0 32
PINS
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
Start
Address = First Location
VCC = 6.5 V ± 0.25 V , VPP = 13 V ± 0.25 V
Program One Pulse = tw = 100 µs
Last
Address?
Yes
Address = First Location
X = 0
Increment
Address
Verify
One Byte
Pass
Fail
No
Increment Address
Program One Pulse = tw = 100 µs
No
X = 10?X = X + 1
Program
Mode
Interactive
Mode
No
VCC = VPP = 5 V ± 0.5 V
Last
Address?
Yes Yes
Compare
All Bytes
to Original
Data
Pass
Device Passed
Fail
Device Failed
Figure 1. SNAP! Pulse Programming Flowchart
Final
Verification
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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