TEXAS INSTRUMENTS TMP320C50KGD, TMP320LC50KGD Technical data
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D
35-ns and 50-ns Single-Cycle Instruction
Execution Time for 5 V Operation
D
50-ns Single-Cycle Instruction Execution
Time for 3.3 V Operation
D
Source-Code Compatible With All ’C1x and
’C2x Devices
D
RAM-Based Operation
– 9K-Words × 16-Bit Single-Access
On-Chip Program/Data RAM
– 1056-Word × 16-Bit Dual-Access On-Chip
Data RAM
D
2K-Word × 16-Bit On-Chip Boot ROM
D
224K-Word × 16-Bit Maximum Addressable
External Memory Space (64K-Word
Program, 64K-Word Data, 64K-Word I/O,
and 32K-Word Global)
D
32-Bit Arithmetic Logic Unit (ALU)
– 32-Bit Accumulator (ACC)
– 32-Bit Accumulator Buffer (ACCB)
description
TMP320C50KGD, TMP320LC50KGD
DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIE
SGZS008B – JULY 1996 – REVISED JUNE 1999
D
16-Bit Parallel Logic Unit (PLU)
D
16 × 16-Bit Multiplier, 32-Bit Product
D
Eleven Context Switch Registers
D
Two Buffers for Circular Addressing
D
Full-Duplex Synchronous Serial Port
D
Time-Division Multiplexed Serial Port (TDM)
D
Timer With Control and Counter Registers
D
16 Software Programmable Wait-State
Generators
D
Divide-By-1 Clock Option
D
IEEE Standard 1149.1† Test Access Port
D
Operations are Fully Static
D
Fabricated Using the Texas Instruments
Enhanced Performance Implanted CMOS
(EPIC) 0.72-µm Technology
The TMP320C50KGD digital signal processor (DSP) is a high performance, 16-bit, fixed-point processor
manufactured in 0.72-µm double-level metal CMOS technology. The TMP320LC50KGD has the same
functionality as the ’C50KGD except for operation at 3.3 V instead of 5 V.
T exas Instruments Military Products currently employs three primary processes for the development of a known
good die (KGD), one of which is applied to the TMP320C50 and TMP320LC50 devices. This process, known
as hot-chuck-probe, uses a standard probed product that is tested again, this time at full data sheet
specifications, in wafer form at speed and elevated temperature (85°C). Each individual die then is sawed,
inspected, and packed for shipment. This flow produces a bare die that has been temperature-tested at speed
and is known to be good, without having to use a temporary package.
A number of enhancements to the basic ’C2x architecture give the ’C5x a minimum 2x performance over the
previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to
subroutine, and delayed return from subroutine, allows the ’C5x to perform instructions in fewer cycles. The
addition of a PLU gives the ’C5x a method of manipulating bits in data memory without using the accumulator
and ALU. The ’C5x has additional shifting and scaling capability for proper alignment of multiplicands or storage
of values to data memory.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 1999, Texas Instruments Incorporated
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TMP320C50KGD, TMP320LC50KGD
DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIE
SGZS008B – JULY 1996 – REVISED JUNE 1999
description (continued)
With the addition of the IDLE2 instruction, the ’C5x achieves low-power consumption. IDLE2 removes the
functional clock from the internal hardware of the ’C5x that puts it into a total-sleep mode using only 5 µA.
A low-logic level on an external interrupt with chip duration of at least five clock cycles ends the IDLE2 mode.
TMP Product Flow; 40 and 57 MHz
Multiprobe dc test @ 25°C
Visual 40x
Test conditions Per commercial data sheet
DC test Hot chuck probe @ 85°C
AC test Hot chuck probe @ 85°C @ Speed
Warranty Datasheet upon shipment, 1 year
For electrical and timing specifications, see the
TMS320C5x, TMS320LC5x Digital Signal Processors
sheet, literature number SPRS030.
Specific Die-Related Information
Die Size (approximate) 391 mils x 421 mils
Die Thickness 15.5 mils " 1 mil
Backside Surface Finish SIO2
Die Backside Potential Floating
Max Allowable Die Junction Operating Temperature 175°C
Glassivation Material and Thickness 3KAOX/9KACN
Recommended Packing GEL PAK
Die Attach Information SILVER GLASS
Suggested Bond Wire Size 1.25 AL
Suggested Bonding Method WEDGE
ESD Sensitivity Class II
Max Allowable Process Temperature for Die Attach 450°C
data
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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