TEXAS INSTRUMENTS TM2SN64EPH Technical data
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Organization:
– TM2SN64EPH . . . 2 097 152 x 64 Bits
– TM4SN64EPH . . . 4 194 304 x 64 Bits
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Single 3.3-V Power Supply
(±10% Tolerance)
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Designed for 66-MHz 4-Clock Systems
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JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
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TM2SN64EPH — Uses Eight 16M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(2M × 8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
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TM4SN64EPH — Uses Sixteen 16M-Bit
SDRAMs (2M × 8-Bit) in Plastic TSOPs
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Byte-Read/Write Capability
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Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
t
CK3
†
(CL = 3)
’xSN64EPH-10 10 ns 15 ns 7.5 ns 7.5 ns 64 ms
†
CL = CAS latency
t
CK2
(CL = 2)
ACCESS TIME
CLOCK TO
OUTPUT
t
AC3
(CL = 3)
t
AC2
(CL = 2)
REFRESH
INTERV AL
TM2SN64EPH 2097152 BY 64-BIT
TM4SN64EPH 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS706A – MARCH 1998 – REVISED APRIL 1998
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High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
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Read Latencies 2 and 3 Supported
D
Support Burst-Interleave and
Burst-Interrupt Operations
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Burst Length Programmable to 1, 2, 4,
and 8
D
Two Banks for On-Chip Interleaving
(Gapless Access)
D
Ambient Temperature Range
0°C to 70°C
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Gold-Plated Contacts
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Pipeline Architecture
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Serial Presence Detect (SPD) Using
EEPROM
description
The TM2SN64EPH is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of
eight TMS626812BDGE, 2097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812B data sheet (literature
number SMOS693).
The TM4SN64EPH is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812BDGE,
2 097152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors.
operation
The TM2SN64EPH operates as eight TMS626812BDGE devices that are connected as shown in the
TM2SN64EPH functional block diagram. The TM4SN64EPH operates as sixteen TMS626812BDGE devices
connected as shown in the TM4SN64EPH functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Copyright 1998, Texas Instruments Incorporated
1
TM2SN64EPH 2097152 BY 64-BIT
TM4SN64EPH 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS706A – MARCH 1998 – REVISED APRIL 1998
DUAL-IN-LINE MEMORY MODULE
(TOP VIEW)
1
10
11
40
TM2SN64EPH
(SIDE VIEW)
TM4SN64EPH
(SIDE VIEW)
PIN NOMENCLATURE
A[0:10] Row-Address Inputs
A[0:8] Column-Address Inputs
A11/BA0 Bank-Select Zero
CAS
CKE[0:1] Clock Enable
CK[0:3] System Clock
DQ[0:63] Data-In/Data-Out
DQMB[0:7] Data-In/Data-Out
NC No Connect
RAS Row-Address Strobe
S[0:3] Chip-Select
SA[0:2] Serial Presence Detect (SPD)
SCL SPD Clock
SDA SPD Address/Data
V
DD
V
SS
WE
Column-Address Strobe
Mask Enable
Device Address Input
3.3-V Supply
Ground
Write Enable
41
84
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2SN64EPH 2097152 BY 64-BIT
TM4SN64EPH 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS706A – MARCH 1998 – REVISED APRIL 1998
Pin Assignments
PIN PIN PIN PIN
NO. NAME NO. NAME NO. NAME NO. NAME
1 V
2 DQ0 44 NC 86 DQ32 128 CKE0
3 DQ1 45 S2 87 DQ33 129 S3
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 V
7 DQ4 49 V
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 NC 94 DQ39 136 NC
11 DQ8 53 NC 95 DQ40 137 NC
12 V
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 V
18 V
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 NC 104 DQ47 146 NC
21 NC 63 CKE1 105 NC 147 NC
22 NC 64 V
23 V
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 V
27 WE 69 DQ24 111 CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 S0 72 DQ27 114 S1 156 DQ59
31 NC 73 V
32 V
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 V
37 A8 79 CK2 121 A9 163 CK3
38 A10 80 NC 122 A11/BA0 164 NC
39 NC 81 NC 123 NC 165 SA0
40 V
41 V
42 CK0 84 V
SS
DD
SS
DD
SS
DD
SS
DD
DD
43 V
48 NC 90 V
54 V
60 DQ20 102 V
65 DQ21 107 V
68 V
74 DQ28 116 V
82 SDA 124 V
83 SCL 125 CK1 167 SA2
SS
DD
SS
DD
SS
SS
DD
SS
DD
85 V
91 DQ36 133 V
96 V
101 DQ45 143 V
106 NC 148 V
110 V
115 RAS 157 V
120 A7 162 V
126 NC 168 V
SS
DD
SS
DD
SS
DD
SS
DD
127 V
132 NC
138 V
144 DQ52
149 DQ53
152 V
158 DQ60
166 SA1
SS
DD
SS
DD
SS
SS
DD
SS
DD
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
3
TM2SN64EPH 2097152 BY 64-BIT
TM4SN64EPH 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS706A – MARCH 1998 – REVISED APRIL 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
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PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
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Bypass capacitors: Multilayer ceramic
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Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2SN64EPH
DQMB0
DQ[0:7]
DQMB1
DQ[8:15]
DQMB2
DQ[16:23]
S0
S2
8
8
8
CS
DQM
DQ[0:7]
CS
DQM
DQ[0:7]
CS
DQM
DQ[0:7]
U0
U1
U2
DQMB4
DQ[32:39]
DQMB5
DQ[40:47]
DQMB6
DQ[48:55]
R
C
CS
U4
8
8
8
DQM
DQ[0:7]
CS
U5
DQM
DQ[0:7]
CS
U6
DQM
DQ[0:7]
RR
RR
RR
CK0
CK1
CK2
CK3
R = 10 Ω
RC = 10 Ω
C = 10 pF
V
DD
V
SS
R
C
R
C
R
C
R
C
R
C
Two 0.1 µF
(minimum) per
SDRAM
CK: U0, U4
CK: U1, U5
CK: U2, U6
CK: U3, U7
C
C
U[0:7]
U[0:7]
CS
U3
DQMB3
DQ[24:31]
RAS RAS: SDRAM U[0:7]
CAS CAS: SDRAM U[0:7]
WE
CKE0
A[0:11]
4
8
DQM
DQ[0:7]
WE: SDRAM U[0:7]
CKE: SDRAM U[0:7]
A[0:11]: SDRAM U[0:7]
CS
DQMB7
DQ[56:63]
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
RR
DQM
8
DQ[0:7]
LEGEND: CS
SPD = Serial Presence Detect
U7
= Chip Select
SPD EEPROM
SCL SDA
A0 A1 A2
SA0 SA1 SA2
functional block diagram for the TM4SN64EPH
S1
S0
CS
U0
DQMB0 DQMB4
DQ[0:7] DQ[0:7]
DQMB1
DQ[8:15]
R
R
DQM DQM
8
CS
U1
DQM
8
DQ[0:7]
CS
UB0
DQM
DQ[0:7]
CS
UB1
DQM
DQ[0:7]
DQ[32:39]
DQMB5
DQ[40:47]
TM2SN64EPH 2097152 BY 64-BIT
TM4SN64EPH 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS706A – MARCH 1998 – REVISED APRIL 1998
V
DD
CS
U4
R
8
DQ[0:7]
CS
U5
8
DQM
DQ[0:7]
R
CS
UB4
DQM
DQ[0:7]
CS
UB5
DQM
DQ[0:7]
V
SS
CKE1 CKE: UB[0:7]
CKE0
RAS RAS: U[0:7], UB[0:7]
CAS CAS: U[0:7], UB[0:7]
WE
A[0:11]
Two 0.1 µF
(minimum) per
SDRAM
V
DD
10 kΩ
CKE: U[0:7]
WE: U[0:7], UB[0:7]
A[0:11]: U[0:7], UB[0:7]
U[0:7], UB[0:7]
U[0:7], UB[0:7]
DQMB2
DQ[16:23]
DQMB3
DQ[24:31]
S3
S2
8
8
CS
U2
DQM
DQ[0:7]
CS
U3
DQM
DQ[0:7]
CS
UB2
DQM
DQ[0:7]
CS
UB3
DQM
DQ[0:7]
DQMB6
DQ[48:55]
DQMB7
DQ[56:63]
R = 10 Ω
RC = 10 Ω
R
C
C
C
C
C
C
C
C
CK: U0, U4
CK: U1, U5
CK: UB0, UB4
CK: UB1, UB5
CK: U2, U6
CK: U3, U7
CK: UB2, UB6
CK: UB3, UB7
CK0
CS
U6
8
8
DQM
DQ[0:7]
CS
U7
DQM
DQ[0:7]
RR
RR
CS
UB6
DQM
DQ[0:7]
CS
UB7
DQM
DQ[0:7]
CK1
CK2
CK3
R
R
R
R
R
R
R
SPD EEPROM
SCL SDA
A0 A1 A2
SA0 SA1 SA2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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