Texas Instruments TM2797, TM2795, TM2793, TM2791 Datasheet

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• On-Chip PILL Data Separator

• On-Chip Write Precompensation Logic

• Single + 5-V Supply

• Accommodates Single-and Double-Density Formats

- MM3740 (FM)

- IBM34 (MFM)

• Automatic Seek with Verify

• Multiple Sector Read/Write

• TTL Compatible

• Programmable Control

- Selectable Track-to-Track Access

- Head Load Timing

• Software Compatible with the FD179X Series

• Soft Sector Format Compatibility

description

The TMS279X family are N-channel silicon gate MOS LSl devices which perform the functions of a Floppy Disk Formatter/Controller in a single chip implementation. The TMS279X, which can be considered the end result of both the Western Digital FD1771 and FD179X designs, is IBM compatible in single-density mode (FM) and System 34 compatible in double-density mode (MFM). The TMS279X contains all the features of its predecessor the FD179X plus a high performance phase-lock-loop data separator as well as write precompensation logic. In double-density mode, write precompensation is automatically engaged to a value programmed via an external potentiometer. In order to maintain compatibility, the FD1771, FD179X and TMS279X designs were made as close as possible with the computer interface, instruction set, and I/O registers being identical. Also, head load control is identical. In each case, the actual pin assignments vary by only a few pins from any one to another.

The processor interface consists of an 8-bit bi-directional bus for data, status, and control word transfers. The TMS279X is set up to operate on a multiplexed bus with other bus -oriented devices.

The TMS279X is TTL compatible on all inputs and outputs. The outputs will drive one TTL load or three LS loads. The 2793 is identical to the 2791 except the DAL lines are true for systems that utilize true data busses.

The 2795/7 has a side-select output for controlling double-sided drives.

PROGRAMMABLE

TMS279X

PRODUCTS FLOPPY DISK FORMATTERICONTROLLER FAMILY

JUNE 1984

FEATURES 2791 2793 2795 2797

Single Density (FM) X X X X Double Density (MFM) X X X X True Data Bus X X Inverted Data Bus X X Side Select Out X X Internal CLK Divide X X

Scanned and Edited by Michael Holley - Aug 21, 2001 - HolleyMJ@aol.com

Texas Instruments was a second source for the WD279X and this data sheet is almost identical to the

Western Digital WD279X-02 Data Sheet and Application Note. (But has larger figures and is more readable.)

Active low signals use a trailing # instead of an overbar.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

pin descriptions

NUMBER

PIN NAME SYMBOL FUNCTION

1 ENABLE PRECOMP ENP A Logic high on this input enables write precompensation to

be performed on double density Write Data output only.

19 MASTER RESET# MR# A logic low (50 microseconds min.) on this input resets the

device and loads HEX 03 into the command register. The Not Ready (Status Bit 7) is reset during MR ACTIVE. When MR# is brought to a logic high a RESTORE Command is executed, regardless of the state of the Ready signal from the drive. Also, HEX 01 is loaded into sector register.

20 POWER SUPPLIES VSS Ground 21 VCC +5V ±5%

COMPUTER INERFACE

2 WRITE ENABLE# WE# A logic low on this input gates data on the DAL into the

selected register when CS# is low.

3 CHIP SELECT# CS# A logic low on this input selects the chip and enables

computer communication with the device.

4 READ ENABLE# RE# A logic low on this input controls the placement of data from a

selected register on the DAL when CS# is low.

5,6 REGISTER SELECT

LINE

A0, A1 These inputs select the register to receive / transfer data on

the DAL lines under RE# and WE# control:

CS#

0 0 0 0

0 0 1 1

0 1 0 1

RE# Status Reg Track Reg Sector Reg Data Reg

WE# Command Reg Track Reg Sector Reg Data Reg

7-14 DATA ACCESS LINES DALO-

DAL7

Eight bit bi-directional bus used for transfer of commands, status, and data. These lines are inverted (active low) on TMS2791 and TMS2795.

24 CLOCK CLK This input requires a free-running 50% duty cycle square wave

clock for internal timing reference, 2 MHz ± 1 % for 8" drives, 1 MHz ± 1 % for mini-floppies.

38 DATA REQUEST DRQ This output indicates that the Data Register contains

assembled data in Read operations, or the DR is empty in Write operations. This signal is reset when serviced by the computer through reading or loading the DR.

39 INTERRUPT

REQUEST

INTRQ This output is set at the completion of any command and is

reset when the Status register is read or the Command register is written to.

FLOPPY DISK INTERFACE

15 STEP STEP The step output contains a pulse for each step. 16 DIRECTION DIRC Direction Output is active high when stepping in, active low

when stepping out.

17 5 1/4”, 8" SELECT 5#/8 This input selects the internal VCO frequency for use with

51/4" drives or 8" drives.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

NUMBER

PIN NAME SYMBOL FUNCTION

18 READ PULSE WIDTH RPW An external potentiometer tied to this input controls the phase

comparator within the data separator.

22 TEST# TEST# A logic low on this input allows adjustment of external resistors

by enabling internal signals to appear on selected pins.

23 PUMP PUMP High-Impedance output signal which is forced high or low to

increase / decrease the VCO frequency

25 ENABLE

MINI-FLOPPY (2791,2793)

ENMF# A logic low on this input enables an internal divide by 2 of the

Master Clock. This allows both 51/4" and 8" drive operation with a single 2 MHz clock. For a 1 MHz clock on Pin 24, this line must be left open or tied to a Logic 1.

25 SIDE SELECT

OUTPUT (2795,2797)

SSO The logic level of the Side Select Output is directly controlled by

the 'S' flag in Type 11 or III commands. When U = 1, SSO is set to a logic 1. When U = 0, SSO is set to a logic 0. The SSO is compared with the compare Status Bit 4 (RNF) is set. The Side Select Output is only updated at the beginning of a Type II or III command. It is forced to a logic 0 upon a MASTER RESET condition.

26 VOLTAGE-

CONTROLLED OSCILLATOR

VCO An external capacitor tied to this pin adjusts the VCO center

frequency

27 RAW READ# RAW RD# The data input signal directly from the drive. This input shall be

a negative pulse for each recorded flux transition.

28 HEAD LOAD HLD The HLD output controls the loading of the Read- Write head

against the media.

29 TRACK GREATER

THAN 43

TG43

This output informs the drive that the Read/Write head is positioned between tracks 44-76. This output is valid only during Read and Write Commands.

30 WRITE GATE WG

This output is made valid before writing is to be performed on the diskette.

31 WRITE DATA WD MFM or FM output pulse per flux transition. WD contains the

unique Address marks as well as data and clock in both FM and

MFM formats.

32 READY READY This input indicates disk readiness and is sampled for a logic

high before Read or Write commands are performed. If Ready is low the Read or Write operation is not performed and an interrupt is generated. Type I operations are performed regardless of the state of Ready. The Ready input appears in inverted format as Status Register bit 7.

33 WRITE PRECOMP

WIDTH

WPW An external potentiometer tied to this input controls the amount

of delay in Write precompensation mode.

34 TRACK 00# TR00# This input informs the TMS279X that the Read/Write head is

positioned over Track 00.

35 INDEX PULSE# IP# This input informs the TMS279X when the index hole is

encountered on the diskette.

36 WRITE PROTECT# WPRT#

This input is sampled whenever a Write Command is received. A logic low terminates the command and sets the Write Protect Status bit.

NOTE: A trailing # replaces the overbar means the symbol is active low.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

NUMBER

PIN NAME SYMBOL FUNCTION

37 DOUBLE DENSITY# DDEN# This input pin selects either single or double density operation.

When DDEN = 0, double density is selected. When DDEN = 1, single density is selected.

40 HEAD LOAD TIMING HLT When a logic high is found on the HLT input the head is

assumed to be engaged. It is typically derived from a 1 shot triggered by HLD.

system interface

The TMS279X Floppy Disk Formatter/Controller system interface is shown in Figure 1. This interface consists of the parallel processor interface and the floppy disk interface. Applications for the TMS279X family are 8" floppy and 5 1/4" mini-floppy controller and single- or double-density controller/formatter.

The TMS279X family are MOS/LSI devices which perform the functions of a Floppy Disk Controller / Formatter. Software compatible with its predecessor, the FD179X the device also contains a high performance phase-lock-loop data separator as well as write precompensation logic.

When operating in double-density mode, write precompensation may be enabled, its value predetermined by an external potentiometer. An on-chip VCO and phase comparator allows adjustable frequency range for 5 1/4" or 8" floppy disk interfacing.

The TMS279X is fabricated in NMOS silicon gate technology and available in a 40-pin dual-in-line package.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

functional block diagram

organization

The TMS279X is illustrated in the functional block diagram. The elements that comprise the TMS279X and the processor and floppy disk interface will be described in the paragraphs that follow.

data shift register

This 8-bit register assembles serial data from the read data input (RAW RD#) during read operations and transfers serial data to the write data output during write operations.

data register

This 8-bit register is used as a holding register during disk read and write operations. In disk read operations, the assembled data byte is transferred in parallel to the data register from the data shift register. In disk write operations, information is transferred in parallel from the data register to the data shift register.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

When executing the Seek command, the data register holds 5e address of the desired track position. This register is loaded from the DAL and gated onto the DAL under processor control.

track register

This 8-bit register holds the track number of the current read/write head position. It is incremented by one every time the head is stepped in (towards track 76) and decremented by one when the head is stepped out (towards track 00). The contents of the register are compared with the recorded track number in the ID field during disk read, write and verify operations. The track register can be loaded from or transferred to the DAL. This register should not be loaded when the device is busy.

sector register (SR)

This 8-bit register holds the address of the desired sector position. The contents of the register are compared with the recorded sector number in the ID field during disk read or write operations. The sector register contents can be loaded from or transferred to the DAL. This register should not be loaded when the device is busy.

command register (CR)

This 8-bit register holds the command presently being executed. This register should not be loaded when the device is busy unless the new command is a force interrupt. The command register can be loaded from the DAL, but not read onto the DAL.

status register (STR)

This 8-bit register holds device status information. The meaning of the status bits is a function of the type of command previously executed. This register can be read onto the DAL, but not loaded from the DAL.

CRC logic

This logic is used to check or to generate the 16-bit cyclic redundancy check (CRC). The polynomial is: G(x) = x16 + x12 + x5 + 1.

The CRC includes all information starting with the address mark and up to the CRC characters. The CRC register is preset to ones prior to data being shifted through the circuit.

arithmetic/logic unit (ALU)

The ALU is a serial comparator, incrementer, and decrementer and is used for register modification and comparisons with the disk recorded ID field.

timing and control

All computer and floppy disk interface controls are generated through this logic. The internal device timing is generated from an external crystal clock.

AM detector

The address mark detector detects ID, data and index address marks during read and write operations.

write precompensation

Enables write precompensation to be performed on the double-density write data output.

data separator

A high-performance phase-lock-loop data separator with on-chip VCO and phase comparator allows adjustable frequency range for 5¼" or 8" floppy disk interfacing.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

processor interface

The interface to the processor is accomplished through the eight data access lines (DAL) and associated control signals. The DAL are used to transfer data, status, and control words out of, or into the TMS279X. The DAL are three-state buffers that are enabled as output drivers when chip select (CS#) and read enable (RE#) are active (low logic state) or act as input receivers when CS# and write enable (WE#) are active.

When transfer of data with the floppy disk controller is required by the host processor, the device address is decoded and CS# is made low. The address bits A1 and AO, combined with the signals RE# during a mad operation or WE# during a write operation are interpreted as selecting the following registers:

A1 A0 READ (RE#) WRITE (WE#)

0 0 Status Register Command Register 0 1 Track Register Track Register 1 0 Sector Register Sector Register 1 1 Data Register Data Register

During direct memory access (DMA) types of data transfers between the data register of the TMS279X and the processor, the data request (DRQ) output is used in data transfer control. This signal also appears as status bit 1 during read and write operations.

On disk read operations, the data request is activated (set high) when an assembled serial input byte is transferred in parallel to the data register. This bit is cleared when the data register is read by the processor. If the data register is read after one or more characters are lost, by having new data transferred into the register prior to processor readout, the lost data bit is set in the status register. The read operation continues until the end of sector is reached.

On disk write operations, the data request is activated when the data register transfers its contents to the data shift register, and requires a new data byte. It is reset when the data register is loaded with new data by the processor. If new data is not loaded at the time the next serial byte is required by the floppy disk, a byte of zeroes is written on the diskette and the lost data bit is set in the status register.

At the completion of every command, an INTRQ is generated. INTRQ is reset by either reading the status register or by loading the command register with a new command. In addition, INTRQ is generated if a Force Interrupt command condition is met.

The 279X has two modes of operation according to the state of DDEN# (pin 37). When DDEN# = 1, single density (FM) is selected. When DDEN# = 0, double density (MFM) is selected. In either case, the CLK input (pin 24) is set at 2 MHz for 8" drives or 1 MHz for 5 ¼" drives.

On the 2791/2793, the ENMF# input (pin 25) can be used for controlling both 5 ¼" and 8" drives with a single 2 MHz clock. When ENMF# = 0, an internal ÷ 2 of the CLK is performed. When ENMF# = 1, no divide takes place. This allows the use of a 2 MHz clock for both 5 ¼" and 8" configurations.

The internal VCO frequency must also be set to the proper value. The 5#/8 input (pin 17) is used to select data separator operation by internally dividing the read clock. When 5#/8 = 0, 5 ¼" data separation is selected; when 5#/8 = 1, 8 " drive data separation is selected.

CLOCK (24) ENMF# (25) 5#/8 (17) DRIVE

2 MHz 1 1 8" 2 MHz 0 0 5 ¼" 1 MHz 0 0 5 ¼"

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

functional description

The TMS279X-02 is software compatible with the FD179X-02 series of floppy disk controllers. Commands, status, and data transfers are performed in the same way. Software generated for the 179X can be transferred to a 279X system without modification.

In addition to the 179X, the 279X contains an internal data separator and write precompensation circuit. The TEST# (pin 22) line is used to adjust both data separator and precompensation. When TEST# = 0, the WD (pin 31) line is internally connected to the output of the write precomp one-shot. Adjustment of the WPW (pin

33) line can then be accomplished. A second one-shot tracks the precomp setting at approximately 3:1 to ensure adequate write data pulse durations to meet drive specifications.

Similarly, data separation is also adjusted with TEST# = 0. The TG43 (pin 2 9) line is internally connected to the output of the read data one-shot, which is adjusted via the R PW (pin 1811ine. The DIRC (pin 1611ine contains the read clock output (.5 MHz for 8" drives). The VCO trimming capacitor (pin 26) is adjusted for center frequency.

Internal timing signals are used to generate pulses during the adjustment mode so that these adjustments can be made while the device is in-circuit. The TEST# line also contains a pull-up resistor, so adjustments can b e performed simply by grounding the TEST# on, overriding the pull-up. The TEST# pin cannot be used to disable stepping rates during operation as its function is quite different from the 179X.

Other pins on the device also include pull-up resistors and may be left open to satisfy a logic 1 condition. These are: ENP, 5#/8, ENMF#, WPRT#, DDEN#, HLT, TEST#, and MR#.

general disk read operations

Sector lengths of 128, 256, 512 or 1024 are obtainable in either FM or MFM formats. For FM, DDEN# should be placed to logical "1." For MFM formats, DDEN# should be placed to a logical " 0." Sector lengths are determined at form at time by the fourth byte in the "ID" field.

SECTOR LENGTH TABLE*

SECTOR LENGTH

FIELD (HEX)

NUMBER OF BYTES

IN SECTOR (DECIMAL)

00 128 01 256 02 512 03 1024

*2795/97 may vary - see command summary.

The TMS279X recognizes tracks and sectors numbered 00-FFX.However, due to programming restrictions, only tracks and sectors 00 thru F4 can be formatted.

general disk write operation

When writing is to take place on the diskette, the write gate (WG) output is activated, allowing current to flow into the read/write head. As a precaution to erroneous writing, the first data byte must be loaded into the data register in response to a data request from the 279X before the write gate signal can be activated.

Writing is inhibited when the WRITE PROTECT# input is a logic low, in which case any Write command is immediately terminated, an interrupt is generated and the write protect status bit is set.

For write operations, the 279X provides write gate (pin 30) and write data (pin 31) outputs. Write data consists of a series of pulses set to a width approximately three times greater than the precomp adjustment. Write data provides the unique address marks in both formats.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

ready

Whenever a Read or Write command (Type II or III) is received, the 279X samples the ready input. If this input is logic low the command is not executed and an interrupt is generated. All Type I commands are performed regardless of the state of the ready input. Also, whenever a Type II or III command is received, the TG43 signal output is updated. TG43 may be tied to ENP to enable write precompensation on tracks 44-76.

command description

The TMS279X will accept eleven commands. Command words should only be loaded in the command register when the busy status bit is off (status bit 0). The one exception is the Force Interrupt command. Whenever a command is being executed, Be busy status bit is set. When a command is completed, an interrupt is generated and the busy status bit is reset. The status register indicates whether the completed command encountered an error or was fault free. For ease of discussion, commands are divided into four types. Commands and Types are summarized in Table 1.

TABLE 1 - COMMAND SUMMARY

COMMANDS FOR MODELS

2791,2793

COMMANDS FOR 2795,2797

TYPE COMMAND BITS BITS

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

I Restore 0 0 0 0 h V r1r00 0 0 0 h V r

1r0

I Seek 0 0 0 1 h V r1r00 0 0 1 h V r

1r0

I Step 0 0 1 T h V r1r00 0 1 T h V r

1r0

I Step-in 0 1 0 T h V r1r00 1 0 T h V r

1r0

I Step-out 0 1 1 T h V r1r00 1 1 T h V r

1r0 II Read Sector 1 0 0 m S E C 0 1 0 0 m L E U 0 II Write Sector 1 0 1 m S E C a01 0 1 m L E U a

0 III Read Address 1 1 0 0 0 E 0 0 1 1 0 0 0 E U 0 III Read Track 1 1 1 0 0 E 0 0 1 1 1 0 0 E U 0 III Write Track 1 1 1 1 0 E 0 0 1 1 1 1 0 E U 0

IV Force Interrupt 1 1 0 1 I3I2I 1101 1 0 1 I3I2I 11

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

TABLE 2 - FLAG SUMMARY

COMMAND

TYPE

BIT

NUMBER(S)

DESCRIPTION

I 0, 1 r1 r0 = Stepping Motor Rate

See Table 3 for Rate Summary

I 2 V = Track Number Verify Flag V = 0, No verify

V = 1, Verify on destination track

I 3 h = Head Load Flag h = 0, Unload head at beginning

h = 1, Load head at beginning

I 4 T = Track Update Flag T = 0, No update

T = 1, Update track register

II & III 0 a0 = Data Address Mark a0 = 0, FB (DAM)

a0 = 1, F8 (deleted DAM)

II 1 C = Side Compare Flag C = 0, Disable side compare

C = 1, Enable side compare

II & III 1 U = Update SSO U = 0, Update SSO to 0

U = 1, Update SSO to 1

II & III 2 E = 1 5 ms Delay E = 0, No. 15 ms delay

E = 1, 15 ms delay (30 ms for 1 MHz)

II 3 S = Side Compare Flag S = 0, Compare for side 0

S = 1, Compare for side 1

II 3 L = Sector Length Flag LBS's Sector Length in ID Field

00 01 10 11 L=0 256 512 1024 128 L=1 128 256 512 1024

II 4 m = Multiple Record Flag m=0, Single record

m=1, Multiple record

IV 0-3 Ix = Interrupt Condition Flags

I0 = 1 Not Ready to Ready Transition I1 = 1 Ready To Not Ready Transition I2 = 1 Index Pulse I3 = 1 Immediate Interrupt, Requires A Reset* I3-I0 = 0 Terminate With No Interrupt (INTRQ)

*See Type IV command for further information.

write precompensation

When operating in double density mode (DDEN = 0), the 279X has the capability of providing a user-defined precompensation value for write data. An external potentiometer (10 k?) tied to the WPW signal (pin 33) allows a setting of 100 to 300 ns from nominal.

Setting the write precomp value is accomplished by forcing the TEST# line (pin 22) to a logic 0. A stream of pulses can then be seen on the write data (pin 31) line. Adjust the WPW potentiometer for the desired pulse duration. This adjustment may be performed in-circuit since write gate (pin 30) is inactive while TEST# = 0.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

data separation

The 279X can operate with either an external data separator or its own internal recovery circuits. The condition of the TEST# line (pin 22) in conjunction with MR# (pin 19) will select internal or external mode.

To program the 279X for an external VCO, a MR# pulse must be applied while TEST# = 0. A clock equivalent to eight times the data rate (e.g., 4.0 MHz for 8" double density) is applied to the VCO input (pin

26).The feedback reference voltage is available on the pump output (pin 23) for external integration to control the VCO. TEST# is returned to a logic 1 for normal operation. Note: to maintain this mode, TEST# must be held low whenever MR# is applied.

For internal VCO operation, the TEST# line must be high during the MR# pulse, then set to a logic 0 for the adjustment procedure.

A 50 k? potentiometer tied to the RPW input (pin 18) is used to set the internal read data pulse for proper phasing. With a scope on pin 29 (TG43), adjust the RPW pulse for 1/8 of the data rate (250 ns for 8" double density). An n external variable capacitor of 5-60 pF is tied to the VCO input (pin 26) for adjusting center frequency. With a frequency counter on pin 16 (DIRC), adjust the trimmer cap to yield the appropriate data rate (500 kHz for 8" double density). The DDEN# line must below while the 5#/8 line is held high or the adjustment times above will be doubled.

After adjustments have been made, the TEST# pin is returned to a logic 1 and the device is ready for operation. Adjustments may be made in-circuit since the DIRC and TG43 lines may toggle without affecting the drive.

The PUMP output (pin 23) consists of positive and negative pulses; their duration is equivalent to the phase difference of incoming data vs. VCO frequency. This signal is internally connected to the VCO input, but a filter is needed to connect these pulses to a slow moving DC voltage.

The internal phase-detector is unsymmetrical for a random distribution of data pulses by a factor or two, in favor of a PUMP UP condition. Therefore, it is desirable to have a PUMP DOWN twice as responsive to prevent run-away during a lock attempt.

A first-order lag-lead filter can be used at the PUMP output (pin 23). This filter controls the instantaneous response of the VCO to bit-shifted data (jitter) as well as the response to normal frequency shift, i.e., the lock-up time. A balance must be accomplished between the two conditions to inhibit over- responsiveness to jitter and to prevent an extremely wide lock-up response, leading to PUMP runaway. The filter affects these two reactions in mutually opposite directions.

The following filter circuit is recommended for 8" FM/MFM:

Since 5 1/4" drives operate at exactly one-half the data rate (250 Kb/sec) the above capacitor should be doubled to 0.2 µF or 0.22 µF.

type I commands

The Type I commands include the Restore, Seek, Step, Step-In, and Step-Out commands. Each of the Type I commands contains a rate field (r0r1), which determines the stepping motor rate as defined in Table 3.

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

A 2 µs (MFM) or 4 µs (FM) pulse is provided as an output to the drive. For every step pulse issued, the drive moves one track location in a direction determined by the direction output. The chip will step the drive in the same direction it last stepped unless the command changes the direction.

The direction signal is active high when stepping in and low when stepping out. The direction signal is valid before the first stepping pulse is generated.

The rates (shown in Table 3) can be applied to a step-direction motor through the device interface.

TABLE 3 - STEPPING RATES

CLK 2 MHz 1 MHz

r1 r0 TEST# = 1 TEST# = 1

0 0 3 ms 6 ms 0 1 6 ms 12 ms 1 0 10 ms 20 ms 1 1 15 ms 30 ms

After the last directional step, an additional 15 milliseconds of head settling time takes place if the verify flag is set in Type I commands. Note that this time doubles to 30 ms for a 1 MHz clock. There is also a 15 ms head settling time if the E flag is set in any Type 11 or III command.

When a Seek, Step or Restore command is executed, an optional verification of read-write head position can be performed by setting bit 2 (V = 1) in the command word to a logic 1. The verification operation begins at the end of the 15 millisecond settling time after the head is loaded against the media. The track number from the first encountered ID field is compared against the contents of the track register. If the track numbers compare and the ID field cyclic redundancy check (CRC) is correct, the verify operation is complete and an INTRQ is generated with no errors. If there is a match but not a valid CRC, the CRC error status bit is set (status bit 3), and the next encountered ID field is read from the disk for the verification operation.

The TMS279X must find an ID field with correct track number and correct CRC within 5 revolutions of the media; otherwise the seek error is set and an INTRQ is generated. If V = 0, no verification is performed.

The head load (HLD) output controls the movement of the read/write head against the media. HLD is activated at the beginning of a Type I command if the h flag is set (h = 1), at the end of the Type I command if the verify flag (V = 1), or upon receipt of any Type II or III command. Once HLD is active it remains active until either a Type I command is received with (h = 0 and V = 0); or if the 279X is in an idle state (non-busy) and 15 index pulses have occurred.

Head load timing (HLT) is an input to the 279X which is used for the head engage time. When HLT = 1, the 279X assumes the head is completely engaged. The head engage time is typically 30 to 100 ms depending on drive. The low-to-high transition on HLD is typically used to fire a one shot. The output of the one shot is then used for HLT and supplied as an input to the 279X.

HLT (FROM ONE SHOT)

HEAD LOAD TIMING

TMS279X (WD279X) FLOPPY DISK FORMATTER / CONTROLLER FAMILY

When both HLD and HLT are true, the 279X will then read from or write to the media. The AND of HLD and HLT appears as status bit 5 in Type I status.

In summary, for Type I commands: if h = 0 and V = 0, HLD is reset. If h = 1 and V = 0, HLD is set at the beginning of the command and HLT is not sampled nor is there an internal 15 ms delay. If h = 0 and V = 1, HLD is set near the end of the command, an internal 15 ms occurs, and the 279X waits for HLT to be true. If h = 1 and V = 1, HLD is set at the beginning of the command. Near the end of the command, after all the steps have been issued, an internal 15 ms delay occurs and the 279X then waits for HLT to occur.

For Type II and III commands with E flag off, HLD is made active and HLT is sampled until true. With E flag on, HLD is made active, an internal 15 ms delay occurs and then HLT is sampled until true.

restore (seek track 0)

Upon receipt of this command, the track 00 (TR00) input is sampled. If TR00 is active low, indicating the read-write head is positioned over track 0, the track register is loaded with zeroes and an interrupt is generated. If TR00 is not active low, stepping pulses at a rate specified by the r1 r0 field are issued until the TR00 input is activated. At this time the track register is loaded with zeroes and an interrupt is generated. If the TR00 input does not go active low after 255 stepping pulses, the 279X terminates operation, interrupts, and sets the seek error status bit. A verification operation takes place if the V flag is set. The h bit allows the head to be loaded at the start of command. Note that the Restore command is executed when M R goes from an active to an inactive state.

seek

This command assumes that the track register contains the track number of the current position of the read-write head and the data register contains the desired track number. The TMS279X will update the track register and issue stepping pulses in the appropriate direction until the contents of the track register are equal to the contents of the data register (the desired track location). A verification operation takes place if the V flag is on. The h bit allows the head to be loaded at the start of the command. An interrupt is generated at the completion of the command. Note: when using multiple drives, the track register must be updated for the drive selected before seeks are issued.

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step

Upon receipt of this command, the 279X issues one stepping pulse to the disk drive. The stepping motor direction is the same as in the previous step command. After a delay determined by the r1r0 field, a verification takes place if the V flag is on. If the T flag is on, the track register is updated. The h bit allows the head to be loaded at the start of the command. An interrupt is generated at the completion of the command.

step-in

Upon receipt of this command, the 279X issues one stepping pulse in the direction towards track 76. If the T flag is on, the track register is incremented by one. After a delay determined by the r1r0 field, a verification takes place if the V flag is on. The h bit allows the head to be loaded at the start of the command. An interrupt is generated at the completion of the command.

step-out

Upon receipt of this command, the 279X issues one stepping pulse in the direction towards track 0. If the T flag is on, the track register is decremented by one. After a delay determined by the r1r0 field, a verification takes place if the V flag is on. The h bit allows the head to be loaded at the start of the command. An interrupt is generated at the completion of the command.

exceptions

On the 2795/7 devices, the SSO output is not affected during Type I commands, and an internal side compare does not take place when the (V) verify flag is on.

type II commands

The Type II commands are the Read Sector and Write Sector commands. Prior to loading the Type H command into the command register, the computer must load the sector register with the desired sector number. Upon receipt of the Type II command, the busy status bit is set. If the E flag = 1 (this is the normal case) HLD is made active and HLT is sampled after a 15 ms delay. If the E flag is O, the head is loaded and HLT sampled with no 15 ms delay.

When an lD field is located on the disk, the 279X compares the track number on the ID field with the track register. If there is not a match, the next encountered ID field is read and a comparison is again made. If there was a match, the sector number of the ID field is compared with the sector register. If there is not a sector match, the next encountered ID field is read off the disk and comparisons again made. If the ID field CRC is correct, the data field is then located and will be either written into, or read from depending upon the command. The 279X must find an ID field with a track number, sector number, side number, and CRC within 5revolutions of the disk; otherwise, the record not found status bit is set (status bit 4) and the command is terminated with an interrupt.

Each of the Type II commands contains an (m) flag which determines if multiple records (sectors) are to be read or written, depending upon the command. If m = 0, a single sector is read or written and an interrupt is generated at the completion of the command. If m = 1, multiple records are read or written with the sector register internally updated so that an address verification can occur on the next record. The 279X will continue to read or write multiple records and update the sector register in numerical ascending sequence until the sector register exceeds the number of sectors on the track or until the Force Interrupt command is loaded into the command register, which terminates the command and generates an interrupt.

For example: if the 279X is instructed to read sector 27 and there are only 26 on the track, the sector register exceeds the number available. The 279X will search for 5 disk revolutions, interrupt out, reset busy, and set the record not found status bit.

The Type II commands for 2791-93 also contain side select compare flags. When C = 0 (bit 11 no side comparison is made. When C = 1, the LSB of the side number is read off the ID field of the disk and compared with the contents of the (S) flag (bit 3). If the S flag compares with the side number recorded in the ID field, the 279X continues with the ID search. If a comparison is not made within 5 index pulses, the interrupt line is made active and the record-not found status bit is set.

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The Type II and Ill commands for the 2795-97 contain a side select flag (bit 1). When U = 0, SSO is updated to 0. Similarly, U = 1 updates SSO to 1. The chip compares the SSO to the ID field. If they do not compare within 5 revolutions, the interrupt line is made active and the RNF status bit is set.

The 2795/7 Read Sector and Write Sector commands include a 'L' flag. The 'L' flag, in conjunction with the sector length byte of the ID field, allows different byte lengths to be implemented in each sector. For IBM compatibility, the 'L' flag should be set to a one.

read sector

Upon receipt of the Read Sector command, the head is loaded, the busy status bit set, and when an ID field is encountered that has the correct track number, correct sector number, correct side number, and correct CRC, the data field is presented to the computer The data address mark of the data field must be found within 30 bytes in single density and 43 bytes in double density of the last ID field CRC byte; if not, the ID field search is repeated.

When the first character or byte of the data field has been shifted through the DSR, it is transferred to the DR, and DRO is generated. When the next byte is accumulated in the DSR, it is transferred to the DR and another DRQ is generated. if the computer has not read the previous contents of the DR before a new character is transferred that character is lost and the lost data status bit is set. This sequence continues until the complete data field has been inputted to the computer. If there is a CRC error at the end of the data field, the CRC error status bit is set, and the command is terminated (even if it is a multiple sector command).

At the end of the read operation, the type of data address mark encountered in the data field is recorded in the status register (bit 5) as shown:

STATUS BIT 5 1 Deleted Data Mark 0 Data Mark

write sector

Upon receipt of the Write Sector command, the head is loaded (HLD active) and the busy status bit is set. When an ID field is encountered that has the correct track number, correct sector number, correct side number, and correct CRC, a DRQ is generated. The 279X counts off 11 bytes in single density and 22 bytes in double density from the CRC field and the write gate (WG) output is made active if the DRO is serviced (i.e., the DR has been loaded by the computer). If DRQ has not been serviced, the command is terminated and the lost data status bit is set. If the DRQ has been serviced, the WG is made active and six bytes of zeroes in single density and 12 bytes in double density are then written on the disk. At this time the data address mark is then written on the disk as determined by the a0 field of the command as shown below:

a0 Data Address Mark (Bit 0) 1 Deleted Data Mark 0 Data Mark

The 279X then writes the data field and generates DRQ's to the computer. If the DRQ is not serviced in time for continuous writing, the lost data status bit is set and a byte of zeroes is written on the disk. The command is not terminated. After the last data byte has been written on the disk, the two-byte CRC is computed internally and written on the disk followed by one byte of FE in FM or in MFM. The WG output is then deactivated. For a 2 MHz clock, the INTRO will set 8 to 12 its after the last CRC byte is written. For partial sector writing, the proper method is to write the data and fill the balance with zeroes. By letting the chip fill the zeroes, errors may be masked by the lost data status and improper CRC bytes.

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types III commands

read address

Upon receipt of the Read Address command, the head is loaded and the busy status bit is set. The next encountered ID field is then read in from the disk, and the six data bytes of the ID field are assembled and transferred to the DR, and a DRQ is generated for each byte. The six bytes of the ID field are shown below:

TRACK

ADDR

SIDE

NUMBER

SECTOR

ADDRESS

SECTOR

LENGTH

CRC

1 2 3 4 5 6

Although the CRC characters are transferred to the computer, the 279X checks for validity and the CRC error status bit is set if there is a CRC error. The track address of the ID field is written into the sector register so that a comparison can be made by the host. At the end of the operation, an interrupt is generated and the busy status is reset.

read track

Upon receipt of the Read Track command, the head is loaded, and the busy status bit is set. Reading starts with the leading edge of the first encountered index pulse and continues until the next index pulse. All gap, header, and data bytes are assembled and transferred to the data register and DRQ's are generated for each byte. The accumulation of bytes is synchronized to each address mark encountered. An interrupt is generated at the completion of the command.

This command has several characteristics which make it suitable for diagnostic purposes. They are: no CRC checking is performed; gap information is included in the data stream; the internal side compare is not performed; and the address mark detector is on for the duration of the command. Because the AM detector is always on, write splices or noise may cause the chip to look for an AM if an address mark does not appear on schedule with the lost data status flag being set.

The ID AM, ID field, ID CRC bytes, DAM, data and data CRC bytes for each sector will be correct. The gap bytes may be read incorrectly during write-splice time because of synchronization.

write track formatting the disk

(Refer to section on Type III commands for flowcharts.) Formatting the disk is a relatively simple task when operating programmed I/0 or when operating under DMA

with a large amount of memory. Data and gap information must be provided at the computer interface. Formatting the disk is accomplished by positioning the R/W head over the desired track number and issuing the Write Track command.

Upon receipt of the Write Track command, the head is loaded and the busy status bit is set. Writing starts with the leading edge of the first encountered index pulse and continues until the next index pulse, at which time the interrupt is activated. The data request is activated immediately upon receiving the command, but writing will not start until after the first byte has been loaded into the data register. If the DR has not been loaded by the time the index pulse is encountered, the operation is terminated making the device not busy, the lost data status bit is set, and the interrupt is activated. If a byte is not present in the DR when needed, a byte of zeroes is substituted.

This sequence continues from one index mark to the next index mark. Normally, whatever data pattern appears in the data register is written on the disk with a normal clock pattern. However, if the 279X detects a data pattern of F5 thru FE in the data register, this is interpreted as data address marks with missing clocks or CRC generation.

The CRC generator is initialized when any data byte from F8 to FE is about to be transferred from the DR to the DSR or by receipt of F5 in MFM. An F7 pattern will generate two CRC characters in FM or MFM. As a consequence, the patterns F5 thru FE must not appear in the gaps, data fields, or ID fields. Also, CRC's must be generated by an F7 pattern.

Disks may be formatted in IBM 3740 or System 34 formats with sector lengths of 128, 256, 512, or 1024 bytes.

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CONTROL BYTES FOR INITIALIZATION

DATA PATTERN

IN DR (HEX)

TMS279X INTERPRETATION

IN FM (DDEN# = 1)

TMS279X INTERPRETATION

IN MFM (DDEN# = 0)

00 thru F4 Write 00 thru F4 with CLK = FF Write 00 thru F4, in MFM F5 Not Allowed Write Al * in MFM, Preset CRC F6 Not Allowed Write C2 † in MFM F7 Generate 2 CRC bytes Generate 2 CRC bytes F8 thru FB Write F8 thru FM CLK = C7, Preset CRC Write F8 thru FB, in MFM FC Write FC with CLK = D7 Write FC in MFM FD Write FD with CLK = FF Write FD in MFM FE Write FE, CLK = C7, Preset CRC Write FE in MFM FF Write FF with CLK = FF Write FF in MFM

* Missing clock transition between bits 4 and 5. † Missing clock transition between bits 3 and 4.

type IV commands

The Forced Interrupt command is generally used to terminate a multiple sector read or write command or to ensure Type I status in the status register. This command can be loaded into the command register at any time. If there is a current command under execution (busy status bit set) the command will be terminated and the busy status bit reset.

The lower four bits of the command determine the conditional interrupt as follows:

10 = Not -Ready to Ready Transition 11 = Ready to Not -Ready Transition 12 = Every Index Pulse 13 = Immediate Interrupt

The conditional interrupt is enabled when the corresponding bit positions of the command (l3 – I0) are set to a

1. Then, when the condition for interrupt is met, the INTRQ line will go high signifying that the condition specified has occurred. If l3 – I0 are all set to zero (HEX DO), no interrupt will occur but any command presently under execution will be immediately terminated. When using the immediate interrupt condition (l3 = 1), an interrupt will be immediately generated and the current command terminated. Reading the status or writing to the command register will not automatically clear the interrupt. The HEX DO is the only command that will enable the immediate interrupt (HEX D8) to clear on a subsequent load command register or read status register operation. Follow a HEX D8 with DO command.

Wait 8 µs (double density) or 16 µs (single density) before issuing a new command after issuing a forced interrupt (times double when clock = 1 MHz). Loading a new command sooner than this will nullify the forced interrupt.

Forced interrupt stops any command at the end of an internal micro-instruction and generates INTRQ when the specified condition is met. Forced interrupt will wait until ALU operations in progress are complete (CRC calculations, compares, etc.)

More than one condition may be set at a time. If for example, the READY TO NOT-READY condition (I1 = 1) and the Every Index Pulse (I2 = 1) are both set, the resultant command would be HEX "DA" The "OR" function is per formed so that either a READY TO NOT-READY or the next index pulse will cause an interrupt condition.

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status register

Upon receipt of any command, except the Force Interrupt command, the busy status bit is set and the rest of the status bits are updated or cleared for the new command. If the Force Interrupt command is received when there is a current command under execution, the busy status bit is reset, and the reset of the status bits are unchanged. If the Force Interrupt command is received when there is not a current command under execution, the busy status bit is reset and the rest of the status bits are updated or cleared. In this case, status reflects the Type I commands.

The user has the option of reading the status register through program control or using the DRQ line with DMA or interrupt methods. When the data register is read, the DRQ bit in the status register and the DRQ line are automatically reset. A write to the data register also causes both DRQ's to reset.

The busy bit in the status may be monitored with a user program to determine when a command is complete, in lieu of using the INTRQ line. When using the INTRQ, a busy status check is not recommended because a read of the status register to determine the condition of busy will reset the INTRQ line.

The format of the status register is shown below:

(BITS)

7 6 5 4 3 2 1 0

S7 S6 S5 S4 S3 S2 S1 S0

Status varies according to the type of command executed as shown in Table 4.

Because of internal sync cycles, certain time delays must be observed when operating under programmed 1/0. They are: (times double when clock = 1 MHz).

OPERATION NEXT OPERATION DELAY REG’D

FM MFM

Write to Command Register Write to Command Register Write Any Register

12 µs 28 µs

6 µs

14 µs

IBM 3740 format - 128 bytes/sector

Shown below is the IBM single-density format with 128 bytes/sector. In order to format a diskette, the user must issue the Write Track command, and load the data register with the following values. For every byte to be written, there is one data request.

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IBM system 34 format - 256 bytes/sector

Shown below is the IBM dual-density format with 2 56 bytes/sector. ln order to format a diskette the user must issue the Write Track command and load the data register with following values. For every byte to be written, there is one data request.

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non-IBM formats

Variations in the IBM formats are possible to a limited extent if the following requirements are met:

1) Sector size must be 128, 256, 512 or 1024 bytes.

2) Gap 2 cannot be varied from the IBM format.

3) 3 bytes of A1 must be used in MFM.

In addition, the Index Address mark is not required for operation by the 279X. Gap 1, 3, and 4 lengths can be as short as 2 bytes for 279X operation, however PLL lock up time, motor speed variation, write splice area, etc., will add more bytes to each gap to achieve proper operation. It is recommended that the IBM format be used for highest system reliability.

FM MFM

Gap I 16 bytes FF 32 bytes 4E

Gap II 11 bytes FF 22 bytes 4E

* 6 bytes 00 12 bytes 00 * 3 bytes A1

Gap III † 10 bytes FF 24 bytes 4E

4 bytes 00 8 bytes 00

3 bytes A1

Gap IV 16 bytes FF 16 bytes 4E

* Byte counts must be exact. † Byte counts are minimum, except exactly 3 bytes of A1 must be written.

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

Voltage on any input (see Note 1) ..................................................................................... - 0.5 V to 7 V

Power dissipation (all outputs open) .......................................................................................... 0.75 W

Operating free-air temperature range ................................................................................... 0°C to 70°C

Storage temperature range .......................................................................................... - 55 °C to 125°C

† Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values in this data sheet are with respect to VSS.

recommended operating conditions

PARAMETER MIN NOM MAX UNIT

Supply voltage, V

4.75

5.25 V

Supply voltage, V

High-level input voltage, V

Low-level input voltage, V

0.8 V

Operating free-air temperature, T

70 °C

electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT

High-level voltage output PUMP IOH = -1 mA 2.2

All others IOH = -100 µA 2.4 V

Low-level output voltage PUMP IOL = 1 mA 0.2

All others IOL = 1.6 mA 0.45 V

II Input current (leakage) VI = V

10 µA

Output current (leakage) VO = V

10 µA

Internal pull-up current ‡ VI = 0 V 100 1700 µA

Supply current All outputs open 70 150 mA

† All typical values are at TA = 25°C and nominal supply voltages. ‡ Internal pull-up resistors are on pins 1, 1 7, 19, 22, 36, 37, and 40. Also, pin 25 on 2791 and 2793 devices.

timing characteristics over recommended supply voltage range and operating free-air temperature range

READ ENABLE TIMING

PARAMETER TEST

CONDITIONS

ALT.

SYMBOL†

MIN TYP MAX UNIT

su(A-RE)

A0, A1 to RE# setup time T

SET

50 ns

tsu(CS-RE

) CS# to RE# setup time T

SET

50 ns

h(A-RE)

A0, A1 from RE# hold time T

HLD

10 ns

h(CS-RE)

CS# from RE# hold time T

HLD

10 ns

tw(RE) RE pulse duration CL = 50 pF T

200 ns

rs(RE-DRQ)

Reset time, DRQ from RE# T

DRR

100 200 ns

rs(RE-INT)

Reset time, INTRQ from RE# T

IRR

500 3000 ns

a(RE)

Data access time from RE# CL = 50 pF T

DACC

100 200 ns

dis(RE)

Data disable time from RE # CL = 50 pF T

DOH

20 150 ns

† Symbol used in Western Digital Corporation WD279X-02 Data Sheet

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WRITE ENABLE TIMING

PARAMETER TEST

CONDITIONS

ALT.

SYMBOL†

MIN TYP MAX UNIT

su(A-WE)

A0, A1 to WE# setup time T

SET

50 ns

su(CS-WE)

CS# to VVE# setup time T

SET

50 ns

h(A-WE)

A0, A1 from WE# hold time T

HLD

10 ns

h(CS-WE)

CS# from WE# hold time T

HLD

10 ns

w(WE)

WE# pulse duration T

200 ns

rs(WE-DRQ)

DRQ reset time from WE# T

DRR

100

200 ns

rs(WE-INT)

INTRQ reset time from WE# T

IRR

500

3000 ns

su(D-WE)

Data setup time to WE# T

150 ns

h(D-WE

) Data hold time from WE# T

50 ns

† Symbol used in Western Digital Corporation WD279X-02 Data Sheet.

Time doubles when CLK = 1 MHz.

†

SERVICE

(WORST CASE): FM 27.5µs, MFM 13.5 µs.

NOTES:

2. CS# may be permanently tied low if desired.

3. DRQ rising edge: indicates that the data register has assembled data

4. DRQ falling edge: indicates that the data register was read.

5. INTREQ rising edge: occurs at end of command.

6. INTREQ falling edge: indicates that the status register was read.

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* Time doubles when CLK = 1 MHz. †

SERVICE

(WORST CASE): FM 23.5µs, MFM 11.5 µs.

NOTES:

7. CS# may be permanently tied low if desired.

8. When writing data into sector tract or data register, user cannot read this register until at least 4 µs in MFM after the rising edge of WE#. When writing into the command register, status is not valid until some 28 µs in FM, and 14 µs in MFM Iater. These times are doubled when CLK 1 MHz.

9. DRQ rising edge: indicates that the data register is empty.

10. DRQ falling edge: indicates that the data register is loaded.

11. INTREQ rising edge: indicates the end of a command.

12. INTREQ falling edge: indicates that the command register is written to.

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input data timing

PARAMETER ALT.

SYMBOL†

MIN TYP MAX UNIT

tw(RR) RAW READ pulse duration T

100 200 ns

tC(RR) RAW READ cycle time T

1500 2000 ns

† Symbol used in Western Digital Corporation WD279X-02 Data Sheet.

write data timing (all times double when CLK = 1 MHz) (no write precompensation)

PARAMETER TEST

CONDITIONS

ALT.

SYMBOL†

MIN TYP MAX UNIT

FM 400 500 600 ns t

w(WD)

Write data pulse duration

MFM

200 250 300

FM 2 µs t

d(WG-WD)

Write gate to write data delay time

MFM

FM 2 µs t

d(WD-WG)

Write gate from write data delay time

MFM

† Symbol used in Western Digital Corporation WD279X-02 Data Sheet.

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miscellaneous timing

PARAMETER TEST

CONDITIONS

ALT.

SYMBOL †

MIN TYP MAX UNIT

w(CL)

CLK low pulse duration T

CD1

230 250 20000 ns

w(CH)

CLK high pulse duration T

CD2

230 250 20000 ns

w(S)

STEP high pulse duration T

STP

2 or 4 µs

su(DIR-S)

DIRC to STEP setup time + CLK error T

DIR

12 µs

w(MRL)

MR# low pulse duration T

50 µs

w(IPL)

IP# low pulse duration T

10 µs

Input MFM RPW 120 700 nst

w(RW)

Read window pulse duration

0-5 V FM +15% 240 1400

Precomp = 100 ns

MFM

WPW 200 300 400 nst

w(WD)P

Write data pulse duration (precompensation adjustable)

Precomp = 300 ns

MFM

WPW 600 900 1200

Cext = 0 VCO 6 MHzf

VCO

Free-running voltage-controlled oscillator frequency ‡

Cext = 35 pF 4

Pump up+25% PUMP = 2.2 V Cext

= 35 pF

VCO 5 MHzf

VCO

Free-running voltagecontrolled oscillator frequency ‡

Pump down-25% PUMP = 0.2 V Cext

= 35 pF

VCC + 5%

Cext = 3 5 pF

3.8 4.2 MHzf

VCO

Free-running voltage-controlled oscillator frequency ‡

TA = 75°C

Cext = 35 pF

VCO

3.5

ext

Adjustable external capacitor VCO = 4 MHz

(Nom)

ext

20 45 100 pF

VCO ÷ 8 DDEN# = 0

5/8 = 1

500 kHz

DDEN# = 0

5/8 = 0

250f

DRC

Derived read clock frequency

VCO ÷ 16 VCO

4 MHz

DDEN# = 1

5/8 = 1

250

VCO ÷ 32 DDEN# = 1

5/8 = 0

CLK

125

MFM 250 nst

w(PUPD)

Pump up/pump down time on (pulse duration)

PU/DON

500

† Symbol used in Western Digital Corporation WD 279X-02 Data Sheet. ‡ VCO frequency adjustable by external capacitor (Cext) on pin 26.

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miscellaneous timing

From Step Rate Table. NOTES:

14. Times double when CLK = 1 MHz.

15. Output timing readings are at VOL = 0.8 V and VOH - 2 V.

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TABLE 4 - STATUS REGISTER SUMMARY

BIT ALL TYPE I

COMMANDS

READ

ADDRESS

READ

SECTOR

READ

TRACK

WRITE

SECTOR

WRITE

TRACK

S7 NOT READY NOT READY NOT READY NOT READY NOT READY NOT READY S6 WRITE

PROTECT

0 0 0 WRITE

PROTECT

WRITE

PROTECT

S5 HEAD

LOADED

0 RECORD

TYPE

0 0 0

S4 SEEK ERROR RNF RNF 0 RNF 0 S3 CRC ERROR CRC ERROR CRC ERROR 0 CRC ERROR 0 S2 TRACK 0 LOST DATA LOST DATA LOST DATA LOST DATA LOST DATA S1 INDEX PULSE DRQ DRQ DRQ DRQ DRQ

SO BUSY BUSY BUSY BUSY BUSY BUSY

status for type I commands

BIT NAME MEANING

S7 NOT READY This bit when set indicates the drive is not ready. When reset it indicates that the drive is

ready. This bit is an inverted copy of the ready input and logically 'ORed' with MR. S6 PROTECTED When set, indicates write protect is activated. This bit is an inverted copy of WRPT# input. S5 HEAD LOADED When set, it indicates the head is loaded and engaged. This bit is a logical "AND" of HLD

and HLT signals. S4 SEEK ERROR When set, the desired track was not verified. This bit is reset to 0 when updated. S3 CRC ERROR CRC encountered in ID field. S2 TRACK 00 When set, indicates read/write head is positioned to Track 0. This bit is an inverted copy

of the TR00# input. S1 INDEX When set, indicates index mark detected from drive. This bit is an inverted copy of the IP#

input. S0 BUSY When set, command is in progress. When reset, no command is in progress.

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status for type II and III commands

BIT NAME MEANING

S 7 NOT READY This bit when set indicates the drive is not ready. When reset, it indicates that the

drive is ready. This bit is an inverted copy of the ready input and 'ORed' with MR. The Type II and III commands will not execute unless the drive is ready.

S6 WRITE PROTECT On read record: not used. On read track: not used. On any write: it indicates a

write protect. This bit is reset when updated.

S5 RECORD TYPE On read record: it indicates the record-type code from data field address mark.

1 = deleted data mark. 0 = data mark. On any write: forced to a zero.

S4 RECORD NOT FOUND (RNF)

When set, it indicates that the desired track, sector, or side were not found. This bit is reset when updated.

S3 CRC ERROR If S4 is set, an error is found in one or more ID fields; otherwise it indicates error

in data field. This bit is reset when updated.

S2 LOST DATA When set, it indicates the computer did not respond to DRQ in one byte time. This

bit is reset to zero when updated.

S1 DATA REQUEST This bit is a copy of the DRQ output. When set, it indicates the DR is full on a read

operation or the DR is empty on a write operation. This bit is reset to zero when updated.

S0 BUSY When set, command is under execution. When reset, no command is under

execution.

summary of adjustment procedure

NOTE: To maintain internal VCO operation, ensure that TEST# = 1 whenever a master reset pulse is applied.

WRITE PRECOMPENSATION

1) Set TEST# (pin 22) to a logic high.

2) Strobe MR# (pin 19).

3) Set TEST# (pin 22) to a logic low.

4) Observe pulse duration on WD (pin 31).

5) Adjust WPW (pin 33) for desired pulse duration (precompensation value).

6) Set TEST# (pin 22) to a logic high.

DATA SEPARATOR

1) Set TEST# (pin 22) to a logic high.

2) Strobe MR# (pin 19). Ensure that 5#/8, and DDEN# are set properly.

3) Set TEST# (pin 22) to a logic low.

4) Observe pulse duration on TG43 (pin 29).

5) Adjust RPW (pin 18) for 1/8 of the read clock (250 ns for 8 " DD, 500 ns for 5'1/4" DD, etc.).

6) Observe frequency on DIRC (pin 161.

7) Adjust variable capacitor on VCO pin for data rate (500 kHz for 8" DD, 250 kHz for 5 1/4" DD, etc.).

8) Set TEST# (pin 22) to a logic high.

Texas Instruments TM2797, TM2795, TM2793, TM2791 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual