TEXAS INSTRUMENTS TLV5608, TLV5610, TLV5629 Technical data

www.ti.com

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

DGND

DIN

SCLK

FS

PRE
OUTE
OUTF

OUTG

OUTH

AGND

DV

DD

DOUT
LDAC
MODE
REF
OUTD
OUTC
OUTB
OUTA
AV

DD

DW OR PW PACKAGE

(TOP VIEW)

查询TLV5608IDW供应商

8-CHANNEL, 12-/10-/8-BIT, 2.7-V TO 5.5-V LOW POWER

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

FEATURES APPLICATIONS

• Eight Voltage Output DACs in One Package

– TLV5610 . . . 12-Bit
– TLV5608 . . . 10-Bit
– TLV5629 . . . 8-Bit

• Programmable Settling Time vs Power

Consumption
– 1 µs In Fast Mode
– 3 µs In Slow Mode

• Compatible With TMS320 and SPI™ Serial

Ports

• Monotonic Over Temperature

• Low Power Consumption:

– 18 mW In Slow Mode at 3-V
– 48 mW In Fast Mode at 3-V

• Reference Input Buffers

• Power-Down Mode

• Buffered, High Impedance Reference Inputs

• Data Output for Daisy-Chaining

TLV5608
TLV5610
TLV5629

SLAS268E – MAY 2000 – REVISED MARCH 2004

• Digital Servo Control Loops

• Digital Offset and Gain Adjustment

• Industrial Process Control

• Machine and Motion Control Devices

• Mass Storage Devices

DESCRIPTION

The TLV5610, TLV5608, and TLV5629 are pin-compatible, eight-channel, 12-/10-/8-bit voltage output DACs
each with a flexible serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and
Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.

Additional features are a power-down mode, an LDAC input for simultaneous update of all eight DAC outputs,
and a data output which can be used to cascade multiple devices.

The resistor string output voltage is buffered by a rail-to-rail output amplifier with a programmable settling time to
allow the designer to optimize speed vs power dissipation. The buffered, high-impedance reference input can be
connected to the supply voltage.

Implemented with a CMOS process, the DACs are designed for single-supply operation from 2.7 V to 5.5 V. The
devices are available in 20-pin SOIC and TSSOP packages.

AVAILABLE OPTIONS

PACKAGE

Copyright © 2000–2004, Texas Instruments Incorporated

SPI is a trademark of Motorola, Inc.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

-40°C to 85°C TLV5608IDW TLV5608IPW 10

T

A

SMALL OUTLINE (DW) TSSOP (PW) RESOLUTION

TLV5610IDW TLV5610IPW 12

TLV5629IDW TLV5629IPW 8

www.ti.com

OUTA

12/10/8

12/10/8

Serial

Interface

12

8

REF

SCLK

DIN

FS

MODE

DOUT

DAC B, C, D, E, F, G and H

Same as DAC A

OUT

PRE

LDAC

X2

B, C, D,
E, F, G
and H

DAC A

Holding

Latch

DAC A

Latch

12/10/8

TLV5608
TLV5610
TLV5629

SLAS268E – MAY 2000 – REVISED MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

Terminal Functions

TERMINAL

NAME NO.

AGND 10 I Analog ground
AV

DD

11 I Analog power supply
DGND 1 I Digital ground
DIN 2 I Digital serial data input
DOUT 19 O Digital serial data output
DV

DD

20 I Digital power supply
FS 4 I Frame sync input

LDAC 18 I
MODE 17 I DSP/µC mode pin. High = µC mode, NC = DSP mode.

PRE 5 I Preset input
REF 16 I Voltage reference input
SCLK 3 I Serial clock input
OUTA-OUTH 6-9, 12-15 O DAC outputs A, B, C, D, E, F, G and H

2

I/O DESCRIPTION

Load DAC. The DAC outputs are only updated, if this signal is low. It is an
asynchronous input.

www.ti.com

TLV5608
TLV5610
TLV5629

SLAS268E – MAY 2000 – REVISED MARCH 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage (AV
Reference input voltage - 0.3 V to AV
Digital input voltage range - 0.3 V to DV
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

, DV

DD

to GND) 7 V

DD

A

stg

(1)

UNIT

+ 0.3 V

DD

+ 0.3 V

DD

-40°C to 85°C

-65°C to 150°C

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Supply voltage, AV

High-level digital input voltage, V

Low-level digital input voltage, V

Reference voltage, V

Load resistance, R
Load capacitance, C
Clock frequency, f
Operating free-air temperature, T

, DV

DD

DD

5-V operation 4.5 5 5.5 V
3-V operation 2.7 3 3.3 V
DV

= 2.7 V 2

IH

IL

ref

L

L

CLK

A

DD

DV

= 5.5 V 2.4

DD

DV

= 2.7 V 0.6

DD

DV

= 5.5 V 1

DD

AV

= 5 V GND 4.096 AV

DD

AV

= 3 V GND 2.048 AV

DD

2 kΩ

-40 85 °C

DD
DD

100 pF

30 MHz

V

V

V
V

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

POWER SUPPLY

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

DD

Power supply current mA

No load, V
All inputs = DV

ref

= 4.096 V,

DD

or GND

Power down supply current 0.1 µA
POR Power on threshold 2 V
PSRR Power supply rejection ratio Full scale

(1)

(1) Power supply rejection ratio at full scale is measured by varying AV

PSRR = 20 log [(E

(AV

max) - EG(AV

G

DD

min))/V

DD

max]

DD

Fast 16 21
Slow 6 8

and is given by:

DD

-60 dB

3

www.ti.com

TLV5608
TLV5610
TLV5629

SLAS268E – MAY 2000 – REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

STATIC DAC SPECIFICATIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TLV5610 12

Resolution TLV5608 10 Bits

TLV5629 8
TLV5610 Code 40 to 4095 ±2 ±6

Integral nonlinearity (INL) TLV5608 V

TLV5629 Code 6 to 255 ±0.3 ±1
TLV5610 Code 40 to 4095 ±0.5 ±1

Differential nonlinearity (DNL) TLV5608 V

TLV5629 Code 6 to 255 ±0.1 ±1

E

ZS

E

ZS

E

G

Zero-scale error (offset error at zero scale) ±30 mV

TC Zero-scale-error temperature coefficient 30 µV/°C

Gain error ±0.6

EGTC Gain error temperature coefficient 10 ppm/°C

OUTPUT SPECIFICATIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Voltage output range RL= 10 kΩ 0 AV
Output load regulation accuracy RL= 2 kΩ vs 10 kΩ ±0.3

REFERENCE INPUT

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

Reference input voltage 0 AV

I

R

Reference input resistance 100 kΩ

i

C

Reference input capacitance 5 pF

i

Reference input bandwidth V

Reference feedthrough V

= 0.4 Vpp+ 2.048 V dc, Input code = 0x800 MHz

ref

= 2 Vppat 1 kHz + 2.048 V dc

ref

DIGITAL INPUT

I

High-level digital input current VI= V

IH

I

Low-level digital input current VI= 0 V -1 µA

IL

C

Input capacitance 8 pF

i

DD

DIGITAL OUTPUT

V

High-level digital output voltage RL= 10 kΩ 2.6 V

OH

V

Low-level digital output voltage RL= 10 kΩ 0.4 V

OL

Output voltage rise time RL= 10 kΩ, CL= 20 pF, Includes propogation delay 7 20 ns

(1) Reference feedthrough is measured at the DAC output with an input code = 0x000.

= 2 V, 4V Code 20 to 1023 ±0.5 ±2 LSB

ref

= 2 V, 4V Code 20 to 1023 ±0.1 ±1 LSB

ref

Fast 2.2
Slow 1.9

(1)

-84 dB

-0.4 V

DD

% of FS

voltage

DD

1 µA

% of FS

voltage

V

4

www.ti.com

TLV5608
TLV5610
TLV5629

SLAS268E – MAY 2000 – REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS (CONTINUED)

over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

ANALOG OUTPUT DYNAMIC PERFORMANCE

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Fast 1 3

t

s(FS)

t

s(CC)

Output settling time (full scale) RL= 10 kΩ, CL= 100 pF

Output settling time, code to code RL= 10 kΩ, CL= 100 pF

SR Slew rate RL= 10 kΩ, CL= 100 pF

Glitch energy See note
Channel crosstalk 10 kHz sine, 4 V

(4)

PP

(1) Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of

0x80 to 0xFFF and 0xFFF to 0x080, respectively. Assured by design; not tested.

(2) Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of one

count. The max time applies to code changes near zero scale or full scale. Assured by design; not tested.
(3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full scale voltage.
(4) Code transition: TLV5610 - 0x7FF to 0x800, TLV5608 - 0x7FC to 0x800, TLV5629 - 0x7F0 to 0x800

(1)

Slow 3 7
Fast 0.5 1

(2)

Slow 1 2
Fast 4 10

(3)

Slow 1 3

4 nV-s

-90 dB

µs

µs

V/µs

TIMING REQUIREMENTS

DIGITAL INPUTS

MIN NOM MAX UNIT

t

su(FS-CK)

t

su(C16-FS)

t

su(FS-C17)

t

su(CK-FS)

t

wL(LDAC)

t

wH

t

wL

t

su(D)

t

h(D)

t

wH(FS)

t

wL(FS)

t

s

Setup time, FS low before next negative SCLK edge 8 ns
Setup time, 16

rising edge of FS. µC mode only
µC mode, setup time, FS high before 17

th

negative edge after FS low on which bit D0 is sampled before

th

positive SCLK. 10 ns

10 ns

DSP mode, setup time, SLCK low before FS low. 5 ns
LDAC duration low 10 ns
SCLK pulse duration high 16 ns
SCLK pulse duration low 16
Setup time, data ready before SCLK falling edge 8 ns
Hold time, data held valid after SCLK falling edge 5 ns
FS duration high 10 ns
FS duration low 10 ns

Settling time

See AC

specs

5