Texas Instruments TLV5606IDR, TLV5606IDGKR, TLV5606IDGK, TLV5606ID, TLV5606CDGKR Datasheet

features

D

10-Bit Voltage Output DAC

D

Programmable Settling Time vs Power
Consumption

3 µs in Fast Mode
9 µs in Slow Mode

D

Ultra Low Power Consumption:

900 µW Typ in Slow Mode at 3 V

2.1 mW Typ in Fast Mode at 3 V

D

Differential Nonlinearity . . . <0.2 LSB Typ

D

Compatible With TMS320 and SPI Serial
Ports

D

Power-Down Mode (10 nA)

description

The TL V5606 is a 10-bit voltage output digital-to­analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows
glueless interface to TMS320, SPI, QSPI, and
Microwire serial ports. The TLV5606 is pro­grammed with a 16-bit serial string containing 4
control and 10 data bits. Developed for a wide
range of supply voltages, the TLV5606 can
operate from 2.7 V to 5.5 V.

TLV5606

2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS259 – DECEMBER 1999

D

Buffered High-Impedance Reference Input

D

Voltage Output Range ... 2 Times the
Reference Input Voltage

D

Monotonic Over Temperature

D

Available in MSOP Package

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

D OR DGK PACKAGE

(TOP VIEW)

DIN

SCLK

CS

FS

1
2
3
4

8
7
6
5

V

DD

OUT
REFIN
AGND

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.

Implemented with a CMOS process, the TL V5606 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TL V5606C is characterized for operation from 0°C
to 70°C. The TLV5606I is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLV5606CD TLV5606CDGK

–40°C to 85°C TLV5606ID TLV5606IDGK

†

Available in tape and reel as the TL V5606CDR, TL V5606IDR,
TLV5606CDGKR, and the TLV5606IDGKR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SMALL OUTLINE

(D)

†

MSOP

(DGK)

†

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

TLV5606

I/O

DESCRIPTION

2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS259 – DECEMBER 1999

functional block diagram

_

REFIN

6

+

DIN

SCLK

CS

FS

1

2
3
4

Serial Input

Register

16 Cycle

Timer

Power-On

Reset

12

Update

10

10-Bit

Data

Latch

2

Speed/Power-Down

10

Logic

x2

Terminal Functions

TERMINAL

NAME NO.

AGND 5 Analog ground
CS 3 I Chip select. Digital input used to enable and disable inputs, active low.
DIN 1 I Serial digital data input
FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
OUT 7 O DAC analog output
REFIN 6 I Reference analog input voltage
SCLK 2 I Serial digital clock input
V

DD

8 Positive power supply

7

OUT

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage, V

Operating free-air temperature, T

IDDPower supply current
PSRR

Power supply rejection ratio

dB

TLV5606

2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS259 – DECEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5606C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5606I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

y v

High-level digital input voltage, V
Low-level digital input voltage, V
Reference voltage, V
Reference voltage, V
Load resistance, R
Load capacitance, C
Clock frequency, f

p

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ V

DD

IH

IL

to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

ref

to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

ref

L

L

CLK

p

A

VDD = 5 V 4.5 5 5.5 V
VDD = 3 V 2.7 3 3.3 V
VDD = 2.7 V to 5.5 V 2 V
VDD = 2.7 V to 5.5 V 0.8 V

2 10 kΩ

100 pF

20 MHz
TLV5606C 0 70 °C
TLV5606I –40 85 °C

causes clipping of the transfer function.

DD/2

†

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

VDD = 5 V, VREF = 2.048 V,
No load,
All inputs = AGND or VDD,

pp

Power down supply current (see Figure 12) 10 nA

pp

Power on threshold voltage, POR 2 V

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

Zero scale See Note 2 –80
Full scale See Note 3 –80

DAC latch = 0x800
VDD = 3 V, VREF = 1.024 V

No load,
All inputs = AGND or VDD,
DAC latch = 0x800

Fast 0.9 1.35 mA

Slow 0.4 0.6 mA

Fast 0.7 1.1 mA

Slow 0.3 0.45 mA

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLV5606

Reference input bandwidth

REFIN

V

1.024 V dc

2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS259 – DECEMBER 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

static DAC specifications RL = 10 kΩ, CL = 100 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 10 bits
INL Integral nonlinearity See Note 4 ± 0.5 ±1.5 LSB
DNL Differential nonlinearity See Note 5 ± 0.2 ± 1 LSB
E

Zero-scale error (offset error at zero scale) See Note 6 ±10 mV

ZS

Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

% of

E

Gain error See Note 8 ±0.6

G

Gain-error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

8. Gain error is the deviation from the ideal output (2V

9. Gain temperature coefficient is given by: EGTC = [EG(T

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

ref

max

) – EG (T

max

min

) – EZS(T

)]/V

× 106/(T

ref

min

)]/V

max

× 106/(T

ref

– T

min

– T

max

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

Voltage output range RL = 10 kΩ 0 AVDD–0.1 V

O

Output load regulation accuracy RL = 2 kΩ, vs 10 kΩ 0.1 ±0.25

FS

voltage

).

% of FS

voltage

reference input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

Input voltage range 0 VDD–1.5 V

I

R

Input resistance 10 MΩ

I

C

Input capacitance 5 pF

I

p

Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –75 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

= 0.2

pp

+

Slow 525 kHz
Fast 1.3 MHz

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

High-level digital input current VI = V

IH

I

Low-level digital input current VI = 0 V ±1 µA

IL

C

Input capacitance 3 pF

I

DD

±1 µA

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t

Output settling time, full scale

L

,

s

t

Output settling time, code to code

L

,

SR

Slew rate

L

,

L

,

V/µs

R

10 kΩ,C

100 pF

0

BW = 20 kHz

TLV5606

2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS259 – DECEMBER 1999

operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

kHz

CL = 100 pF,

CL = 100 pF,

= 100 pF,

=

p

L

R

s(FS)

s(CC)

S/N Signal to noise 62 dB
S/(N+D) Signal to noise + distortion
THD Total harmonic distortion

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

p

p

Glitch energy Code transition from 0x7FF to 0x800 10 nV–s

Spurious free dynamic range

of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

= 10 kΩ,

See Note 11
R

= 10 kΩ,

See Note 12
R

= 10 kΩ, C

See Note 13

fs = 400 KSPS fout = 1.1 kHz,

=

L

BW = 2

Fast 3 5.5
Slow 9 20
Fast 1 µs
Slow 2 µs
Fast 3.6
Slow 0.9

,

–61 dB

µ

60 dB

68 dB

digital input timing requirements

t

su(CS–FS)

t

su(FS–CK)

t

su(C16–FS)

t

su(C16–CS)

t

wH

t

wL

t

su(D)

t

h(D)

t

wH(FS)

Setup time, CS low before FS↓ 10 ns
Setup time, FS low before first negative SCLK edge 8 ns
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising

edge of FS
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising

edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS

Pulse duration, SCLK high 25 ns
Pulse duration, SCLK low 25 ns
Setup time, data ready before SCLK falling edge 8 ns

Hold time, data held valid after SCLK falling edge 5 ns
Pulse duration, FS high 20 ns

MIN NOM MAX UNIT

10 ns

10 ns

rising edge.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLV5606

2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS259 – DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

SCLK

DIN

CS

FS

t

su(D)

t

wL

123451516

t

h(D)

D15 D14 D13 D12 D1 D0

t

su(FS-CK)

t

su(CS-FS)

t

wH(FS)

t

wH

t

t

su(C16-FS)

su(C16-CS)

Figure 1. Timing Diagram

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5606

2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS259 – DECEMBER 1999

TYPICAL CHARACTERISTICS

2.004

2.002

2

1.998

1.996

– Output Voltage – V

1.994

O

V

1.992

1.990

0.2

0.18

0.16

0.14

0.12

0.1

0.08

– Output Voltage – V

0.06

O

V

0.04

0.02

OUTPUT VOLTAGE

vs

LOAD CURRENT

3 V Slow Mode, SOURCE

3 V Fast Mode, SOURCE

0 0.01 0.02 0.05 0.1 0.2 0.5

Load Current – mA

Figure 2

OUTPUT VOLTAGE

vs

LOAD CURRENT

VDD = 3 V,
V

= 1 V,

ref

Zero Code

3 V Slow Mode, SINK

3 V Fast Mode, SINK

VDD = 3 V,
V

= 1 V,

ref

Full Scale

12

4.01

4.005

4

3.995

3.99

– Output Voltage – V

3.985

O

V

3.98

3.975

0.35

0.3

0.25

0.2

0.15

– Output Voltage – V

0.1

O

V

0.05

OUTPUT VOLTAGE

vs

LOAD CURRENT

5 V Slow Mode, SOURCE

5 V Fast Mode, SOURCE

0 0.02 0.04 0.1 0.2 0.4 1

Load Current – mA

Figure 3

OUTPUT VOLTAGE

vs

LOAD CURRENT

VDD = 5 V,
V

= 2 V,

ref

Zero Code

5 V Slow Mode, SINK

5 V Fast Mode, SINK

VDD = 5 V,
V

= 2 V,

ref

Full Scale

24

0

0 0.01 0.02 0.05 0.1 0.2 0.5

Load Current – mA

Figure 4

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0

0 0.02 0.04 0.1 0.2 0.4 1

24

Load Current – mA

Figure 5

7