TEXAS INSTRUMENTS TLV560 Technical data

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

Four 10-Bit D/A Converters

Programmable Settling Time of 3 µs or 9 µs Typ

TMS320, (Q)SPI, and Microwire Compatible Serial Interface

Internal Power-On Reset

Low Power Consumption:

5.5 mW, Slow Mode – 5-V Supply

3.3 mW, Slow Mode – 3-V Supply

Reference Input Buffers

Voltage Output Range ...2× the Reference Input Voltage

Monotonic Over Temperature

Dual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)

description

The TL V5604 is a quadruple 10-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5604 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and a 10-bit DAC value.

SLAS176B – DECEMBER 1997 – REVISED JUL Y 2002

WITH POWER DOWN

Hardware Power Down (10 nA)

Software Power Down (10 nA)

Simultaneous Update

applications

Battery Powered Test Instruments

Digital Offset and Gain Adjustment

Industrial Process Controls

Machine and Motion Control Devices

Communications

Arbitrary Waveform Generation

D OR PW PACKAGE

(TOP VIEW)

LDAC

DIN

SCLK

DGND

7 8

REFINAB OUTA OUTB OUTC OUTD REFINCD AGND

TLV5604

The device has provision for two supplies: one digital supply for the serial interface (via pins DV and one for the DACs, reference buffers and output buffers (via pins AV

and AGND). Each supply is

and DGND),

independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DV

and DGND), with the DACs operating on a 5-V supply . Of course, the digital and analog supplies can be

tied together. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB

output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage then DACs C and D.

The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TL V5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

AVAILABLE OPTIONS

PACKAGE

functional block diagram

0°C to 70°C TLV5604CD TLV5604CPW

–40°C to 85°C TLV5604ID TLV5604IPW

SOIC

(D)

TSSOP

(PW)

REFINAB

SCLK

15 16 1

DAC A

+ _

10-Bit

DAC

Latch

2-Bit

Control

Data

Latch

DAC B

DIN

7 5

Power-On

Reset

Serial

Input

DAC

Select/

Control

Logic

14-Bit

Data

and

Control

Power Down/

Speed Control

OUTA

OUTB

REFINCD

AGND

DGND

LDAC

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DAC C

DAC D

OUTC

OUTD

TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

TLV5604

Supply voltage, AV

High-level digital input voltage, V

Low-level digital input voltage, V

Reference voltage, V

to REFINAB, REFINCD terminal

Operating free-air temperature

°C

PSRR

Power supply rejection ratio

See Notes 8 and 9

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

recommended operating conditions

MIN NOM MAX UNIT

Load resistance, R Load capacitance, C Serial clock rate, SCLK 20 MHz

NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.

ref

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

5-V supply 4.5 5 5.5 3-V supply 2.7 3 3.3 DVDD = 2.7 V 2 DVDD = 5.5 V 2.4 DVDD = 2.7 V 0.6 DVDD = 5.5 V 1 5-V supply (see Note 1) 0 2.048 AVDD–1.5 3-V supply (see Note 1) 0 1.024 AVDD–1.5

2 10 kΩ

100 pF

TLV5604C 0 70 TLV5604I –40 85

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 bits Integral nonlinearity (INL), end point adjusted See Note 2 ±1 LSB Differential nonlinearity (DNL) See Note 3 ±0.1 ±1 LSB

NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

Zero scale error (offset error at zero scale) See Note 4 ±12 mV Zero scale error temperature coefficient See Note 5 10 ppm/°C

min

%of FS voltage

Gain error See Note 6 ±0.6 Gain error temperature coefficient See Note 7 10 ppm/°C

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T

6. Gain error is the deviation from the ideal output (2V

7. Gain temperature coefficient is given by: EG TC = [EG(T

8. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage.

9. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.3 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.

Zero scale gain Gain

) – EZS (T

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

ref

max

) – EG (T

max

min

)]/V

× 106/(T

ref

min

)]/V

max

ref

– T

× 106/(T

min

–80 –80

max

– T

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Reference input bandwidth

REFIN

1.024 V dc

MHz

5-V supply

load, Clock running

IDDPower supply current

3-V supply

load, Clock running

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

individual DAC output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

reference input (REFINAB, REFINCD)

NOTES: 10. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

Voltage output RL = 10 kΩ 0 AVDD–0.4 V Output load regulation accuracy RL = 2 kΩ vs 10 kΩ 0.1 0.25

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage range See Note 10 0 AVDD–1.5 V Input resistance 10 MΩ Input capacitance 5 pF

Reference feed through

11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V input = 1.024 Vdc + 1 Vpp at 1 kHz.

REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 11)

= 0.2

–75 dB

Slow 0.5 Fast 1

ref(REFINAB or REFINCD)

TLV5604

% of FS

voltage

digital inputs (D0–D11, CS, WEB, LDAC, PD)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level digital input current VI = DV Low-level digital input current VI = 0 V ±1 µA Input capacitance 3 pF

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power down supply current, See Figure 12

, No

Slow 1.4 2.2 Fast 3.5 5.5 Slow 1 1.5 Fast 3 4.5

±1 µA

10 nA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5604

Output slew rate

10% to 90%

tsOutput settling time

Output settling time, code to code

400 KSPS

100 pF

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

s(c)

SNR Signal-to-noise ratio S/(N+D) Signal to noise + distortion THD Total harmonic Distortion

SFDR Spurious free dynamic range

NOTES: 12. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change

Glitch energy Code transition from 7FF to 800 10 nV-sec

of 020 hex to 3FF hex or 3FF hex to 020 hex.

13. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of one count, 1FF hex to 200 hex.

14. Limits are ensured by design and characterization, but are not production tested.

CL = 100 pF, RL = 10 kΩ,

= 2.048 V, 1024 V

ref

To ± 0.5 LSB, C RL = 10 kΩ, See Notes 12 and 14

To ± 0.5 LSB, C RL = 10 kΩ, See Note 13

Sinewave generated by DAC, Reference voltage = 1.024 at 3 V and 2.048 at 5 V ,

= 400 KSP

f f

= 1.1 kHz sinewave,

OUT

BW = 20 kHz

= 100 pF,

= 10 kΩ,

Fast 5 V/µs

Slow 1 V/µs

Fast 2.5 4

Slow 8.5 18

Fast 1

Slow 2

68 65

–68

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

TYPICAL CHARACTERISTICS

LOAD REGULATION

0.35 VDD = 5 V, V

= 2 V,

0.30

0.25

0.20

0.15

– Output Voltage – V

0.10

0.05

REF

VO = Full Scale

5 V Slow Mode, Sink

5 V Fast Mode, Sink

0 0.02 0.04 0.1 0.2 0.4 1

Load Current – mA

Figure 2

LOAD REGULATION

4.002

0.8

LOAD REGULATION

0.20 VDD = 3 V,

0.18

= 1 V,

REF

VO = Full Scale

0.16

0.14

0.12

0.10

0.08

– Output Voltage – V

0.06

0.04

0.02

0 0.01 0.02 0.05 0.1 0.2 0.5

3 V Fast Mode, Sink

Load Current – mA

Figure 3

3 V Slow Mode, Sink

0.8

3.998

3.996

3.994

3.992

– Output Voltage – V

3.988

3.986

3.984

4.00

3.99

Load Current

Figure 4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

TEMPERATURE

VDD = 3 V, V

= 1.024 V,

REF

3.5

VO = Full Scale

2.5

– Supply Current – mA

1.5

0.5 –40 –20 0 20 40 60

T – Temperature – °C

Figure 6

Fast Mode

Slow Mode

80 100

– Supply Current – mA

3.5

2.5

1.5

0.5

SUPPLY CURRENT

TEMPERATURE

Fast Mode

Slow Mode

T – Temperature – °C

Figure 7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION AND NOISE

FREQUENCY

= 1 V dc + 1 V p/p Sinewave,

ref

Output Full Scale

Fast Mode

0 5 10 20

f – Frequency – kHz

30 50 100

THD – Total Harmonic Distortion And Noise – dB

–10

–20

–30

––40

–50

–60

–70

–80

Figure 10

(WHEN ENTERING POWER-DOWN MODE)

4000

–10

–20

–30

––40

–50

–60

–70

THD – Total Harmonic Distortion And Noise – dB

–80

SUPPLY CURRENT

TIME

TOTAL HARMONIC DISTORTION AND NOISE

FREQUENCY

= 1 V dc + 1 V p/p Sinewave,

ref

Output Full Scale

Slow Mode

0 5 10 20

f – Frequency – kHz

30 50 100

Figure 11

3500

3000

Aµ

2500

2000

1500

– Supply Current –

1000

500

0 200 400 600

800 1000

t – Time – ns

Figure 12

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+ 21 hidden pages

TEXAS INSTRUMENTS TLV560 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

description

applications

functional block diagram

recommended operating conditions

static DAC specifications

individual DAC output specifications

reference input (REFINAB, REFINCD)

power supply

analog output dynamic performance

TYPICAL CHARACTERISTICS