Texas Instruments TLV5535EVM, TLV5535IPWR, TLV5535IPW Datasheet

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

8-Bit Resolution, 35 MSPS Sampling
Analog-to-Digital Converter (ADC)

D

Low Power Consumption: 90 mW Typ
Using External References

D

Wide Analog Input Bandwidth: 600 MHz Typ

D

3.3-V Single-Supply Operation

D

3.3-V TTL/CMOS-Compatible Digital I/O

D

Internal Bottom and Top Reference
Voltages

D

Adjustable Reference Input Range

D

Power-Down (Standby) Mode

D

Separate Power Down for Internal Voltage
References

D

Three-State Outputs

D

28-Pin Thin Shrink SOP (TSSOP) Packages

D

Applications
– Digital Communications (IF Sampling)
– High-Speed DSP Front-End

(TMS320C6000)
– Medical Imaging
– Video Processing (Scan Rate/Format

Conversion)
– DVD Read Channel Digitization

description

The TLV5535 is an 8-bit, 35 MSPS, high-speed A/D converter. It converts the analog input signal into 8-bit
binary-coded digital words up to a sampling rate of 35 MHz. All digital inputs and outputs are 3.3 V
TTL/CMOS-compatible.

The device consumes very little power due to the 3.3-V supply and an innovative single-pipeline architecture
implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage
references from user-supplied voltages. If no external references are available, on-chip references are
available for internal and external use. The full-scale range is 1 V

pp

up to 1.6 Vpp, depending on the analog
supply voltage. If external references are available, the internal references can be disabled independently from
the rest of the chip, resulting in an even greater power saving.

While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed
graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD
read channel digitization, medical imaging, and communications. This device is suitable for IF sampling of
communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

TSSOP-28

–40°C to 85°C TLV5535IPW

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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28
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23
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20
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18
17
16
15

DRV

DD

D0
D1
D2
D3
D4
D5
D6
D7

DRV

SS

DV

SS

CLK

OE

DV

DD

AV

SS

AV

DD

AIN
CML
PWDN_REF
AV

SS

REFBO
REFBI
REFTI
REFTO
AV

SS

BG
AV

DD

STBY

PW PACKAGE

(TOP VIEW)

Copyright  1999, Texas Instruments Incorporated

TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

SHA

DACADC

+

–

ADC

Correction Logic

Output Buffers

2222 2

D0(LSB)–D7(MSB)

2

2

SHA SHA SHA SHA SHA

The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a
resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from
each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction
logic ensures no missing codes over the full operating temperature range.

circuit diagrams of inputs and outputs

DV

DD

AV

DD

AV

DD

0.5 pF

Internal
Reference
Generator

REFTO
or
REFBO

AV

DD

REFBI

or

REFTI

OE

ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT

REFERENCE INPUT CIRCUIT D0–D7 OUTPUT CIRCUIT

DRV

DD

DRV

SS

D_Out

D

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AIN 26 I Analog input
AV

DD

16, 27 I Analog supply voltage

AV

SS

18, 23, 28 I Analog ground

BG 17 O Band gap reference voltage. A 1-µF capacitor (with an optional 0.1-µF capacitor in parallel) should be

connected between this terminal and AVSS for external filtering.
CLK 12 I Clock input. The input is sampled on each rising edge of CLK.
CML 25 O Common mode level. This voltage is equal to (A VDD – AVSS) ÷ 2. An external 0.1-µF capacitor should be

connected between this terminal and AVSS.
D0 – D7 2 – 9 O Data outputs. D7 is the MSB.
DRV

DD

1 I Supply voltage for digital output drivers

DRV

SS

10 I Ground for digital output drivers

DV

DD

14 I Digital supply voltage
OE 13 I Output enable. When high, the D0 – D7 outputs go in high-impedance mode.
DV

SS

11 I Digital ground
PWDN_REF 24 I Power down for internal reference voltages. A high on this terminal disables the internal reference circuit.
REFBI 21 I Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the

ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering
should be applied to this input. The use of a 0.1-µF capacitor connected between REFBI and AVSS is
recommended. Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.

REFBO 22 O Reference voltage bottom output. An internally generated reference is available at this terminal. It can be

connected to REFBI or left unconnected. A 1-µF capacitor between REFBO and A VSS provides sufficient
decoupling required for this output.

REFTI 20 I Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.

It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be
applied to this input. The use of a 0.1-µF capacitor between REFTI and AVSS is recommended.
Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.

REFTO 19 O Reference voltage top output. An internally generated reference is available at this terminal. It can be

connected to REFTI or left unconnected. A 1-µF capacitor between REFTO and A VSS provides sufficient
decoupling required for this output.

STBY 15 I Standby input. A high level on this input enables power-down mode.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range:AVDD to AVSS, DVDD to DVSS –0.5 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AVDD to DVDD, AVSS to DVSS –0.5 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to DVSS –0.5 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range to AVSS –0.5 V to AVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage range applied from external source to DGND –0.5 V to DV

DD

+ 0.5 V. . . . . . . . . . . . . .

Reference voltage input range to AGND: V

(REFTI)

, V

(REFTO)

, V

(REFBI)

, V

(REFBO)

–0.5 V to AVDD + 0.5 V

Operating free-air temperature range, TA: TLV5535I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions over operating free-temperature range

power supply

MIN NOM MAX UNIT

AVDD – AV

SS

Supply voltage

DVDD – DV

SS

3 3.3 3.6 V

DRVDD – DRV

SS

analog and reference inputs

MIN NOM MAX UNIT

Reference input voltage (top), V

(REFTI)

(NOM) – 0.2 2 + (AVDD – 3) (NOM) + 0.2 V

Reference input voltage (bottom), V

(REFBI)

0.8 1 1.2 V

Reference voltage differential, V

(REFTI)

– V

(REFBI)

1 + (AVDD – 3) V

Analog input voltage, V

(AIN)

V

(REFBI)

V

(REFTI)

V

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V

IH

2.0 DV

DD

V

Low-level input voltage, V

IL

DGND 0.2xDV

DD

V

Clock period, t

c

28.6 ns

Pulse duration, clock high, t

w(CLKH)

13 ns

Pulse duration, clock low, t

w(CLKL)

13 ns

electrical characteristics over recommended operating conditions, f

CLK

= 35 MSPS, external

voltage references (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AV

DD

27 34

I

DD

Operating supply current

DV

DD

AVDD = DVDD = 3.3 V, DRVDD = 3 V,

p

–

-

1.5 2.6

mA

DRV

DD

C

L

= 15 F,

V

I

= 1

MHz

, –1-dB

FS

4 6

p

PWDN_REF = L 106 139

PDPower dissipation

PWDN_REF = H 90 113

mW

P

D(STBY)

Standby power STBY = H, CLK held high or low 11 15

digital logic inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level input current on CLK

†

AVDD = DVDD = DRVDD = CLK = 3.6 V 10 µA

I

IL

Low-level input current on digital inputs
(OE

, STDBY, PWDN_REF, CLK)

AVDD = DVDD = DRVDD = 3.6 V,
Digital inputs at 0 V

10 µA

CIInput capacitance 5 pF

†

IIH leakage current on other digital inputs (OE, STDBY , PWDN_REF) is not measured since these inputs have an internal pull-down resistor of
4 KΩ to DGND.

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, f

CLK

= 35 MSPS, external

voltage references (unless otherwise noted) (continued)

logic outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage

AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA,
Digital output forced high

2.8 V

V

OL

Low-level output voltage

AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA,
Digital output forced low

0.1 V

C

O

Output capacitance 5 pF

I

OZH

High-impedance state output current to
high level

10 µA

I

OZL

High-impedance state output current to
low level

AV

DD

=

DV

DD

=

DRV

DD

= 3.6

V

10 µA

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TA = 25°C –1.5 ±0.7 1.5 LSB

Integral nonlinearity (INL), best-fit

Internal references (see Note 1)

TA = –40°C to 85°C –2.4 ±0.7 2.4 LSB
Differential nonlinearity (DNL) Internal references (see Note 2), TA = –40°C to 85°C –1 ±0.6 1.3 LSB
Zero error

AVDD = DVDD = 3.3 V, DRVDD = 3 V,

5 %FS

Full-scale error

DD DD DD

Internal references (see Note 3)

5 %FS

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The

deviation is measured from the center of each particular code to the true straight line between these two endpoints.

2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test [i.e., (last transition level – first transition level) ÷ (2n – 2)]. Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).

Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).

analog input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

C

I

Input capacitance 4 pF

TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, f

CLK

= 35 MSPS, external

voltage references (unless otherwise noted) (continued)

reference input (AVDD = DVDD = DRVDD = 3.6 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

ref

Reference input resistance 400 Ω

I

ref

Reference input current 2.5 mA

reference outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(REFTO)

Reference top offset voltage

Absolute min/max values valid

2.07 2 + [(AVDD – 3) ÷ 2] 2.21 V

V

(REFBO)

Reference bottom offset voltage

and tested for AVDD = 3.3 V

1.09 1 + [(AVDD – 3) ÷ 2] 1.21 V

dynamic performance

†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fin = 1 MHz 6.6 7.4

Effective number of bits (ENOB)

fin = 4.2 MHz 6.6 7.4

Bits
fin = 15 MHz 7
fin = 1 MHz 41.5 46

Signal-to-noise ratio + distortion (SNRD)

fin = 4.2 MHz 41.5 46

dB
fin = 15 MHz 43
fin = 1 MHz –46 –55

Total harmonic distortion (THD)

fin = 4.2 MHz –45.5 –54

dB
fin = 15 MHz –50
fin = 1 MHz 48 58

Spurious free dynamic range (SFDR)

fin = 4.2 MHz 48 58

dB
fin = 15 MHz 52

Analog input full-power bandwidth, BW See Note 4 600 MHz

p

Differential phase, DP

f

CLK

= 35 MHz, fin = 4.2 MHz,

0.6

CLK in

20 IRE amplitude vs full-scale of 140 IRE

Differential gain, DG

20 IRE am litude vs full scale of 140 IRE

0.2%

†

Based on analog input voltage of – 1-dB FS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at
f

CLK

= 35 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3 V at 25°C.

NOTE 4: The analog input bandwidth is defined as the maximum frequency of a –1-dB FS input sine that can be applied to the device for which

an extra 3-dB attenuation is observed in the reconstructed output signal.

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, f

CLK

= 35 MSPS, external

voltage references (unless otherwise noted) (continued)

timing requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Maximum conversion rate 35 MHz

f

CLK

Minimum conversion rate 10 kHz

t

d(o)

Output delay time (see Figure 1) CL = 10 pF, See Notes 5 and 6 9 ns

t

h(o)

Output hold time CL = 2 pF, See Note 5 2 ns

t

d(pipe)

Pipeline delay time (latency) See Note 6 4.5 4.5 4.5

CLK

cycles

t

d(a)

Aperture delay time 3 ns

t

j(a)

Aperture jitter

1.5 ps, rms

t

dis

Disable time, OE rising to Hi-Z

See Note 5

5 8 ns

t

en

Enable time, OE falling to valid data 5 8 ns

NOTES: 5. Output timing t

d(o)

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital

output load is not higher than 10 pF.

Output hold time t

h(o)

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The

digital output is load is not less than 2 pF.

Aperture delay t

d(A)

is measured from the 1.5 V level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing t

dis

is measured from the V

IH(MIN)

level of OE to the high-impedance state of the output data. The digital output load is

not higher than 10 pF.

OE timing ten is measured from the V

IL(MAX)

level of OE to the instant when the output data reaches V

OH(min)

or V

OL(max)

output

levels. The digital output load is not higher than 10 pF.

6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to
know when data is stable on the output pins, the output delay time t

d(o)

(i.e., the delay time through the digital output buffers) needs

to be added to the pipeline latency. Note that since the max t

d(o)

is more than 1/2 clock period at 35 MHz, data cannot be reliably

clocked in on a rising edge of CLK at this speed. The falling edge should be used.

TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

D0–D7 N–4 N–3 N–2 N–1 N N+1

N

N+1

N+2

N+3

N+4

N+5

t

j(a)

t

d(a)

V

IL

(max)

1.5 V

t

w(CLKH)

t

w(CLKL)

1/f

CLK

t

h(o)

1.5 V

t

d(o)

t

dis

t

en

CLK

OE

90%
10%

V

IH(min)

t

d(pipe)

V

OH(min)

V

OL(max)

V

IL(max)

V

IH

(min)

Figure 1. Timing Diagram

TYPICAL CHARACTERISTICS

performance plots at 25°C

–0.2

–0.1

0.0

0.1

0.2

0 50 100 150 200 250

DNL – LSB

ADC Code

Figure 2. DNL vs Input Code at 35 MSPS (with external reference, PW Package)

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

performance plots at 25°C (continued)

–0.4

–0.3

–0.2

–0.1

–0.0

0.1

0.2

0.3

0.4

0 50 100 150 200 250

INL – LSB

ADC Code

Figure 3. INL vs Input Code at 35 MSPS (with external reference, PW package)

0

5

10

15

20

25

30

35

40

45

50

0 1020304050

SNRD – dB

Analog Input Frequency – MHz

Figure 4. SNRD vs fin at 35 MSPS (external reference)

TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

performance plots at 25°C (continued)

0

1

2

3

4

5

6

7

8

0 1020304050

ENOB

Analog Input Frequency – MHz

Figure 5. ENOB vs FIN, 35 MSPS (external reference)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

0 5 10 15

Power – dBFS

f – Frequency – MHz

Figure 6. Spectral Plot fin = 1.0 MHz at 35 MSPS