TEXAS INSTRUMENTS TLV5535 Technical data

T

TLV5535

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

D

8-Bit Resolution, 35 MSPS Sampling
Analog-to-Digital Converter (ADC)

D

Low Power Consumption: 90 mW Typ
Using External References

D

Wide Analog Input Bandwidth: 600 MHz Typ

D

3.3-V Single-Supply Operation

D

3.3-V TTL/CMOS-Compatible Digital I/O

D

Internal Bottom and Top Reference
Voltages

D

Adjustable Reference Input Range

D

Power-Down (Standby) Mode

D

Separate Power Down for Internal Voltage
References

D

Three-State Outputs

D

28-Pin Thin Shrink SOP (TSSOP) Packages

D

Applications
– Digital Communications (IF Sampling)
– High-Speed DSP Front-End

(TMS320C6000)
– Medical Imaging
– Video Processing (Scan Rate/Format

Conversion)
– DVD Read Channel Digitization

description

DRV

DRV

DV

DV

PW PACKAGE

(TOP VIEW)

DD

D0
D1
D2
D3
D4
D5
D6
D7

SS
SS

CLK

OE

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14

AV

28

AV

27

AIN

26

CML

25

PWDN_REF

24

AV

23

REFBO

22

REFBI

21

REFTI

20

REFTO

19

AV

18

BG

17

AV

16
15

STBY

SS
DD

SS

SS

DD

The TLV5535 is an 8-bit, 35 MSPS, high-speed A/D converter. It converts the analog input signal into 8-bit
binary-coded digital words up to a sampling rate of 35 MHz. All digital inputs and outputs are 3.3 V
TTL/CMOS-compatible.

The device consumes very little power due to the 3.3-V supply and an innovative single-pipeline architecture
implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage
references from user-supplied voltages. If no external references are available, on-chip references are
available for internal and external use. The full-scale range is 1 V

up to 1.6 Vpp, depending on the analog

pp

supply voltage. If external references are available, the internal references can be disabled independently from
the rest of the chip, resulting in an even greater power saving.

While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed
graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD
read channel digitization, medical imaging, and communications. This device is suitable for IF sampling of
communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth.

AVAILABLE OPTIONS

A

–40°C to 85°C TLV5535IPW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PACKAGED DEVICES

TSSOP-28

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

TLV5535
8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

functional block diagram

SHA

+

–

SHA SHA SHA SHA SHA

DACADC

2222 2

Correction Logic

Output Buffers

D0(LSB)–D7(MSB)

2

ADC

The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a
resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from
each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction
logic ensures no missing codes over the full operating temperature range.

circuit diagrams of inputs and outputs

ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT

DV

DD

AV

DD

2

REFERENCE INPUT CIRCUIT D0–D7 OUTPUT CIRCUIT

AV

DD

Internal
Reference
Generator

AV

REFBI

or

REFTI

DD

REFTO
or
REFBO

D

OE

0.5 pF

DRV

DRV

DD

D_Out

SS

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TLV5535

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

Terminal Functions

TERMINAL

NAME NO.

AIN 26 I Analog input
AV

DD

AV

SS

BG 17 O Band gap reference voltage. A 1-µF capacitor (with an optional 0.1-µF capacitor in parallel) should be

CLK 12 I Clock input. The input is sampled on each rising edge of CLK.
CML 25 O Common mode level. This voltage is equal to (A VDD – AVSS) ÷ 2. An external 0.1-µF capacitor should be

D0 – D7 2 – 9 O Data outputs. D7 is the MSB.
DRV

DD

DRV

SS

DV

DD

OE 13 I Output enable. When high, the D0 – D7 outputs go in high-impedance mode.
DV

SS

PWDN_REF 24 I Power down for internal reference voltages. A high on this terminal disables the internal reference circuit.
REFBI 21 I Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the

REFBO 22 O Reference voltage bottom output. An internally generated reference is available at this terminal. It can be

REFTI 20 I Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.

REFTO 19 O Reference voltage top output. An internally generated reference is available at this terminal. It can be

STBY 15 I Standby input. A high level on this input enables power-down mode.

16, 27 I Analog supply voltage

18, 23, 28 I Analog ground

connected between this terminal and A VSS for external filtering.

connected between this terminal and A VSS.

1 I Supply voltage for digital output drivers
10 I Ground for digital output drivers
14 I Digital supply voltage

11 I Digital ground

ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering
should be applied to this input. The use of a 0.1-µF capacitor connected between REFBI and AVSS is
recommended. Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.

connected to REFBI or left unconnected. A 1-µF capacitor between REFBO and A VSS provides sufficient
decoupling required for this output.

It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be
applied to this input. The use of a 0.1-µF capacitor between REFTI and AVSS is recommended.
Additionaly, a 0.1-µF capacitor can be connected between REFTI and REFBI.

connected to REFTI or left unconnected. A 1-µF capacitor between REFTO and A VSS provides sufficient
decoupling required for this output.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range:AVDD to AVSS, DVDD to DVSS –0.5 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AVDD to DVDD, AVSS to DVSS –0.5 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to DVSS –0.5 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range to AVSS –0.5 V to AVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage range applied from external source to DGND –0.5 V to DV
Reference voltage input range to AGND: V

(REFTI)

, V

(REFTO)

, V

(REFBI)

, V

(REFBO)

–0.5 V to AVDD + 0.5 V

DD

+ 0.5 V. . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5535I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

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3

TLV5535

C

L

V

I

MHz

FS

PDPower dissipation

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

recommended operating conditions over operating free-temperature range

power supply

Supply voltage

analog and reference inputs

Reference input voltage (top), V
Reference input voltage (bottom), V
Reference voltage differential, V
Analog input voltage, V

(AIN)

(REFTI)

(REFTI)

digital inputs

High-level input voltage, V
Low-level input voltage, V
Clock period, t
Pulse duration, clock high, t

Pulse duration, clock low, t

c

IH

IL

w(CLKH)

w(CLKL)

(REFBI)

– V

AVDD – AV
DVDD – DV
DRVDD – DRV

(REFBI)

SS

SS

SS

MIN NOM MAX UNIT

(NOM) – 0.2 2 + (AVDD – 3) (NOM) + 0.2 V

0.8 1 1.2 V

V

(REFBI)

MIN NOM MAX UNIT

2.0 DV

DGND 0.2xDV

28.6 ns
13 ns

13 ns

MIN NOM MAX UNIT

3 3.3 3.6 V

1 + (AVDD – 3) V

V

(REFTI)

DD

DD

V

V
V

electrical characteristics over recommended operating conditions, f

= 35 MSPS, external

CLK

voltage references (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AV

I

DD

P

D(STBY)

DD

Operating supply current

p

Standby power STBY = H, CLK held high or low 11 15

DV
DRV

DD

DD

AVDD = DVDD = 3.3 V, DRVDD = 3 V,

= 15 F,

PWDN_REF = L 106 139
PWDN_REF = H 90 113

= 1

p

, –1-dB

–

-

digital logic inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

High-level input current on CLK

IH

Low-level input current on digital inputs

I

IL

(OE

, STDBY, PWDN_REF, CLK)

CIInput capacitance 5 pF

†

IIH leakage current on other digital inputs (OE, STDBY , PWDN_REF) is not measured since these inputs have an internal pull-down resistor of
4 KΩ to DGND.

†

AVDD = DVDD = DRVDD = CLK = 3.6 V 10 µA
AVDD = DVDD = DRVDD = 3.6 V,

Digital inputs at 0 V

27 34

1.5 2.6
4 6

10 µA

mA

mW

4

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AV

DD

DV

DD

DRV

DD

V

Integral nonlinearity (INL), best-fit

Internal references (see Note 1)

DD DD DD

TLV5535

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

electrical characteristics over recommended operating conditions, f

= 35 MSPS, external

CLK

voltage references (unless otherwise noted) (continued)

logic outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

High-level output voltage

OH

V

Low-level output voltage

OL

C

Output capacitance 5 pF

O

High-impedance state output current to

I

OZH

high level
High-impedance state output current to

I

OZL

low level

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential nonlinearity (DNL) Internal references (see Note 2), TA = –40°C to 85°C –1 ±0.6 1.3 LSB
Zero error
Full-scale error

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The

deviation is measured from the center of each particular code to the true straight line between these two endpoints.

2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test [i.e., (last transition level – first transition level) ÷ (2n – 2)]. Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).

Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).

AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA,
Digital output forced high

AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA,
Digital output forced low

=

AVDD = DVDD = 3.3 V, DRVDD = 3 V,
Internal references (see Note 3)

=

= 3.6

TA = 25°C –1.5 ±0.7 1.5 LSB
TA = –40°C to 85°C –2.4 ±0.7 2.4 LSB

2.8 V

0.1 V

10 µA

10 µA

5 %FS
5 %FS

analog input

C

Input capacitance 4 pF

I

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

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5

TLV5535

Differential phase, DP

0.6

CLK in

Differential gain, DG

20 IRE am litude vs full scale of 140 IRE

0.2%

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

electrical characteristics over recommended operating conditions, f

= 35 MSPS, external

CLK

voltage references (unless otherwise noted) (continued)

reference input (AVDD = DVDD = DRVDD = 3.6 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

Reference input resistance 400 Ω

ref

I

Reference input current 2.5 mA

ref

reference outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(REFTO)

V

(REFBO)

dynamic performance

Effective number of bits (ENOB)

Signal-to-noise ratio + distortion (SNRD)

Total harmonic distortion (THD)

Spurious free dynamic range (SFDR)

Analog input full-power bandwidth, BW See Note 4 600 MHz

†

Based on analog input voltage of – 1-dB FS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at
f

= 35 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3 V at 25°C.

CLK

NOTE 4: The analog input bandwidth is defined as the maximum frequency of a –1-dB FS input sine that can be applied to the device for which

Reference top offset voltage
Reference bottom offset voltage

Absolute min/max values valid
and tested for AVDD = 3.3 V

†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fin = 1 MHz 6.6 7.4
fin = 4.2 MHz 6.6 7.4
fin = 15 MHz 7
fin = 1 MHz 41.5 46
fin = 4.2 MHz 41.5 46
fin = 15 MHz 43
fin = 1 MHz –46 –55
fin = 4.2 MHz –45.5 –54
fin = 15 MHz –50
fin = 1 MHz 48 58
fin = 4.2 MHz 48 58
fin = 15 MHz 52

p

an extra 3-dB attenuation is observed in the reconstructed output signal.

f

= 35 MHz, fin = 4.2 MHz,

CLK

20 IRE amplitude vs full-scale of 140 IRE

2.07 2 + [(AVDD – 3) ÷ 2] 2.21 V

1.09 1 + [(AVDD – 3) ÷ 2] 1.21 V

Bits

dB

dB

dB

6

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f

See Note 5

TLV5535

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

electrical characteristics over recommended operating conditions, f
voltage references (unless otherwise noted) (continued)

timing requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CLK

t

d(o)

t

h(o)

t

d(pipe)

t

d(a)

t

j(a)

t

dis

t

en

NOTES: 5. Output timing t

Maximum conversion rate 35 MHz
Minimum conversion rate 10 kHz
Output delay time (see Figure 1) CL = 10 pF, See Notes 5 and 6 9 ns
Output hold time CL = 2 pF, See Note 5 2 ns

Pipeline delay time (latency) See Note 6 4.5 4.5 4.5
Aperture delay time 3 ns

Aperture jitter
Disable time, OE rising to Hi-Z
Enable time, OE falling to valid data 5 8 ns

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital

output load is not higher than 10 pF.
Output hold time t

digital output is load is not less than 2 pF.
Aperture delay t
The OE signal is asynchronous.
OE timing t

not higher than 10 pF.
OE timing ten is measured from the V

levels. The digital output load is not higher than 10 pF.

6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to
know when data is stable on the output pins, the output delay time t
to be added to the pipeline latency. Note that since the max t
clocked in on a rising edge of CLK at this speed. The falling edge should be used.

d(o)

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The

h(o)

is measured from the 1.5 V level of the CLK input to the actual sampling instant.

d(A)

is measured from the V

dis

level of OE to the high-impedance state of the output data. The digital output load is

IH(MIN)

level of OE to the instant when the output data reaches V

IL(MAX)

(i.e., the delay time through the digital output buffers) needs

d(o)

is more than 1/2 clock period at 35 MHz, data cannot be reliably

d(o)

= 35 MSPS, external

CLK

1.5 ps, rms
5 8 ns

OH(min)

or V

OL(max)

CLK

cycles

output

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7

TLV5535
8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

PARAMETER MEASUREMENT INFORMATION

N+3

N

N+1

90%
10%

V

IH(min)

N+5

V

t

en

IL(max)

CLK

N+2

t

d(pipe)

t

j(a)

t

t

h(o)

d(a)

1.5 V

1/f

V

V

CLK

t

w(CLKH)

D0–D7 N–4 N–3 N–2 N–1 N N+1

OE

IH

(min)

t

w(CLKL)

IL

(max)

N+4

1.5 V

t

d(o)

t

dis

Figure 1. Timing Diagram

TYPICAL CHARACTERISTICS

performance plots at 25°C

V

OH(min)

V

OL(max)

0.2

0.1

0.0

DNL – LSB

–0.1

–0.2

0 50 100 150 200 250

ADC Code

Figure 2. DNL vs Input Code at 35 MSPS (with external reference, PW Package)

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

TYPICAL CHARACTERISTICS

performance plots at 25°C (continued)

0.4

0.3

0.2

0.1
–0.0
–0.1

INL – LSB

–0.2
–0.3
–0.4

0 50 100 150 200 250

Figure 3. INL vs Input Code at 35 MSPS (with external reference, PW package)

TLV5535

SLAS221 – JUNE 1999

ADC Code

50
45

40

35

30

25

SNRD – dB

20

15

10

5
0

0 1020304050

Analog Input Frequency – MHz

Figure 4. SNRD vs fin at 35 MSPS (external reference)

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9

TLV5535
8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

TYPICAL CHARACTERISTICS

performance plots at 25°C (continued)

8

7

6

5

4

ENOB

3

2

1

0

0 1020304050

Analog Input Frequency – MHz

Figure 5. ENOB vs FIN, 35 MSPS (external reference)

0
–10
–20
–30
–40
–50
–60
–70

Power – dBFS

–80
–90

–100

0 5 10 15

f – Frequency – MHz

Figure 6. Spectral Plot fin = 1.0 MHz at 35 MSPS

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-BIT, 35 MSPS, LOW -POWER ANALOG-TO-DIGITAL CONVERTER

TYPICAL CHARACTERISTICS

performance plots at 25°C (continued)

0
–10
–20
–30
–40
–50
–60

Power – dB

–70
–80
–90

–100

0 5 10 15

Figure 7. Spectral Plot fin = 4.2 MHz at 35 MSPS

TLV5535

SLAS221 – JUNE 1999

f – Frequency – MHz

0

–10
–20
–30
–40
–50
–60

Power – dB

–70
–80
–90

–100

0 5 10 15

f – Frequency – MHz

Figure 8. Spectral Plot fin = 15.527 MHz at 35 MSPS

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11