TEXAS INSTRUMENTS TLV320DAC3120 Technical data

TLV320DAC3120

www.ti.com

Low-Power Mono Audio DAC With Embedded miniDSP

and Mono Class-D Speaker Amplifier

Check for Samples: TLV320DAC3120

1 INTRODUCTION

1.1 Features 1.2 Applications

1

• Mono Audio DAC With 95-dB SNR

• Instruction-Programmable Embedded miniDSP

• Supports 8-kHz to 192-kHz Sample Rates

• Mono Class-D BTL Speaker Driver (2.5 W Into
4 Ω or 1.6 W Into 8 Ω)

• Mono Headphone/Lineout Driver

• Two Single-Ended Inputs With Output Mixing
and Level Control

• Microphone Bias

• Built-in Digital Audio Processing Blocks With
User-Programmable Biquad, FIR Filters, and
DRC

• Programmable Digital Audio Processor for
Bass Boost/Treble/EQ With up to Six Biquads
for Playback

• Pin Control or Register Control for Digital
Playback Volume-Control Settings

• Integrated PLL Used for Programmable Digital
Audio Processor

• I2S, Left-Justified, Right-Justified, DSP, and
TDM Audio Interfaces

• I2C Control With Register Auto-Increment

• Full Power-Down Control

• Power Supplies:
– Analog: 2.7 V–3.6 V
– Digital Core: 1.65 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
– Class-D: 2.7 V–5.5 V (SPKVDD ≥ AVDD)

• 5-mm × 5-mm 32-QFN Package

• Portable Audio Devices

• eBook

• Portable Navigation Devices

1.3 Description

The TLV320DAC3120 is a low-power, highly
integrated, high-performance mono DAC with 24-bit
mono playback.

The device integrates several analog features, such
as a microphone bias, headphone drivers, and a
mono speaker driver capable of driving a 4-Ω load.
The TLV320DAC3120 has a fully programmable
miniDSP for digital audio processing. The digital
audio data format is programmable to work with
popular audio standard protocols (I2S,
left/right-justified) in master, slave, DSP, and TDM
modes. Bass boost, treble, or EQ can be supported
by the programmable digital-signal processing block.
An on-chip PLL provides the high-speed clock
needed by the digital signal-processing block. The
volume level can be controlled by either a pin control
or by register control. The audio functions are
controlled using the I2C serial bus.

The TLV320DAC3120 is available in a 32-pin QFN
package.

SLAS659–NOVEMBER 2009

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testingof all parameters.

Copyright © 2009, Texas Instruments Incorporated

Digital

Audio

Processing

and

Serial

Interface

SDIN

BCLK

WCLK

MCLK PLL

HPVDDHPVSS

SPKVDDSPKVSS

AVDDAVSS

SPKVSS

SPKVDD

VOL/MICDET

SCL

SDA

GPIOGPIO1

DAC

MIXER
P1/R35

RESET

DVDDDVSS

IOVDD

IOVSS

AIN2

AIN1

2 V/2.5 V/AVDD

MICBIAS

Note: Normally,
MCLK is PLL input;
however, BCLK or
GPIO1 can also be
PLL input.

Audio Output Stage
Power Management

De-Pop

and

Soft Start

RC CLK

P1/R33–R34

P1/R46

I C

2

Mono DAC

SPKP
SPKM

Class-D Speaker

Driver

6 dB to 24 dB

(6-dB steps)

Analog

Attenuation

0 dB to –78 dB

and Mute

(0.5-dB steps)

P1/R42

P1/R38

SPKP

SPKM

Class A/B

Headphone/Lineout

Driver

0 dB to 9 dB
(1-dB steps)

Analog

Attenuation

HPOUT

P1/R36

P1/R40

P1/R30–R31

L Data
R Data
(L+R)/2 Data

P0/R63

7-Bit ADC P0/R116

Left and Right

Volume-Control Register

P0/R117

Digital Vol

24 dB to

Mute

miniDSP

P0/R64

S

0 dB to –78 dB

and Mute

(0.5-dB steps)

B0360-01

TLV320DAC3120

SLAS659–NOVEMBER 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

www.ti.com

This data manual is designed using PDF document-viewing features that allow quick
access to information. For example, performing a global search on "page 0 / register 27"
produces all references to this page and register in a list. This makes is easy to traverse
the list and find all information related to a page and register. Note that the search string
must be of the indicated format. Also, this document includes document hyperlinks to
allow the user to quickly find a document reference. To come back to the original page,
click the green left arrow near the PDF page number at the bottom of the file. The hot-key
for this function is alt-left arrow on the keyboard. Another way to find information quickly is
to use the PDF bookmarks.

Figure 1-1. Functional Block Diagram

NOTE

2 INTRODUCTION Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

P0048-12

AVSSSPKVSS

IOVSS

SPKVDD

24123222321420519618717

8

16

25

15

26

14

27

13

28

12

29

1130

1031

932

NC

SPKM

AIN2

SPKP

AIN1

SPKVDD

MICBIAS

SPKVSS

VOL/MICDET

SPKM

SCL

DVSS

SDA

AVDD

RHB Package

(Top View)

SPKP

IOVDD

HPOUT

DVDD

HPVDD

NC

HPVSS

DIN

NC

WCLK

RESET

BCLK

GPIO1

MCLK

TLV320DAC3120

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

2 PACKAGE AND SIGNAL DESCRIPTIONS

2.1 Package/Ordering Information

PRODUCT PACKAGE TEMPERATURE ORDERING NUMBER QUANTITY

PACKAGE

DESIGNATOR

TLV320DAC3120 QFN-32 RHB –40°C to 85°C

2.2 Device Information

OPERATING TRANSPORT MEDIA,

RANGE

TLV320DAC3120IRHBT Tape and reel, 250
TLV320DAC3120IRHBR Tape and reel, 3000

Table 2-1. TERMINAL FUNCTIONS

TERMINAL

NAME NO.

AIN1 13 I Analog input #1 routed to output mixer
AIN2 14 I Analog input #2 routed to output mixer
AVDD 17 – Analog power supply
AVSS 16 – Analog ground
BCLK 7 I/O Audio serial bit clock
DIN 5 I Audio serial data input
DVDD 3 – Digital power – digital core
DVSS 18 – Digital ground
GPIO1 32 I/O General-purpose input/output and multifunction pin
HPOUT 27 O Headphone/lineout driver output
HPVDD 28 – Headphone/line driver and PLL power
HPVSS 29 – Headphone/line driver and PLL ground
IOVDD 2 – Interface power
IOVSS 1 – Interface ground
MCLK 8 I Exterrnal master clock

Copyright © 2009, Texas Instruments Incorporated PACKAGE AND SIGNAL DESCRIPTIONS 3

I/O DESCRIPTION

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

SLAS659–NOVEMBER 2009

www.ti.com

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

MICBIAS 12 O Micophone bias voltage
NC 4, 15, 30 – No connection
RESET 31 I Device reset
SCL 10 I/O I2C control-bus clock input
SDA 9 I/O I2C control-bus data input
SPKM 19, 23 O Class-D speaker driver inverting output
SPKP 22, 26 O Class-D speaker driver noninverting output
SPKVDD 21, 24 – Class-D speaker driver power supply
SPKVSS 20, 25 – Class-D speaker driver power-supply ground
VOL/MICDET 11 I Volume control or microphone/headphone/headset detection
WCLK 6 I/O Audio serial word clock

I/O DESCRIPTION

3 ELECTRICAL SPECIFICATIONS

3.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

AVDD to AVSS –0.3 to 3.9 V
DVDD to DVSS –0.3 to 2.5 V
HPVDD to HPVSS –0.3 to 3.9 V
SPKVDD to SPKVSS –0.3 to 6 V
IOVDD to IOVSS –0.3 to 3.9 V
Digital input voltage IOVSS – 0.3 to IOVDD + 0.3 V
Analog input voltage AVSS – 0.3 to AVDD + 0.3 V
Operating temperature range –40 to 85 °C
Storage temperature range –55 to 150 °C
Junction temperature (TJMax) 105 °C

QFN package

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Power dissipation (TJMax – TA)/R
R

Thermal impedance (with thermal pad soldered to board) 35 °C/W

θJA

(1)

VALUE UNIT

θJA

W

Table 3-1. System Thermal Characteristics

Power Rating at 25°C Derating Factor Power Rating at 70°C Power Rating at 85°C

2.3 W 28.57 mW/°C 1 W 0.6 W

(1) This data was taken using 2-oz. (0.071-mm thick) trace and copper pad that is soldered to a JEDEC high-K, standard 4-layer

3-in. × 3-in. (7.62-cm × 7.62-cm) PCB.

4 ELECTRICAL SPECIFICATIONS Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

(1)

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

3.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

(1)

AVDD

Referenced to AVSS
DVDD Referenced to DVSS
HPVDD Power-supply voltage range Referenced to HPVSS
SPKVDD

(1)

Referenced to SPKVSS
IOVDD Referenced to IOVSS

Speaker impedance Load applied across class-D output pins (BTL) 4 Ω
Headphone impedance AC-coupled to R

V

I

MCLK

(3)

Analog audio full-scale input
voltage

Mono line output load
impedance

AVDD = 3.3 V, single-ended 0.707 V

AC-coupled to R

Master clock frequency IOVDD = 3.3 V 50 MHz
SCL SCL clock frequency 400 kHz
T

A

Operating free-air temperature –40 85 °C

(1) To minimize battery-current leakage, the SPKVDD and SPKVDD voltage levels should not be below the AVDD voltage level.
(2) All grounds on board are tied together, so they should not differ in voltage by more than 0.2 V maximum for any combination of ground

signals. By use of a wide trace or ground plane, ensure a low-impedance connection between HPVSS and DVSS.

(3) The maximum input frequency should be 50 MHz for any digital pin used as a general-purpose clock.

(2)
(2)

(2)

(2)

(2)

L

L

2.7 3.3 3.6

1.65 1.8 1.95

2.7 3.3 3.6

2.7 5.5

1.1 3.3 3.6

16 Ω

10 kΩ

V

RMS

3.3 Electrical Characteristics

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS(audio) = 48 kHz,
CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL OSCILLATOR—RC_CLK

Oscillator frequency 8.2 MHz

VOLUME CONTROL PIN (ADC); VOL/MICDET pin enabled

Input voltage range 0 / register 116, bit D7 = 1 and page 0 / register 67, 0 V

Input capacitance 2 pF
Volume control steps 128 Steps

MICROPHONE BIAS

Voltage output V

Voltage regulation mV

VOL/MICDET pin configured as volume control (page
bit D7 = 0)

Page 1 / register 46, bits D1–D0 = 10 2.25 2.5 2.75
Page 1 / register 46, bits D1–D0 = 01 2
At 4-mA load current, page 1 / register 46, bits D1–D0

= 10 (MICBIAS = 2.5 V)
At 4-mA load current, page 1 / register 46, bits D1–D0

= 01 (MICBIAS = 2 V)

0.5 ×

AVDD

5

7

Copyright © 2009, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 5

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

SLAS659–NOVEMBER 2009

www.ti.com

Electrical Characteristics (continued)

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS(audio) = 48 kHz,
CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC HEADPHONE OUTPUT, AC-COUPLED LOAD = 16 Ω (SINGLE-ENDED),
DRIVER GAIN = 0 dB, PARASITIC CAPACITANCE = 30 pF

Full-scale output voltage

(0 dB)
SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted
THD Total harmonic distortion 0-dBFS input –85 –65 dB

THD+N 0-dBFS input –82 –60 dB

Total harmonic distortion +

noise

Mute attenuation 87 dB
PSRR Power-supply rejection ratio

P

O

Maximum output power mW

DAC LINEOUT (HP Driver in Lineout Mode)

SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted 95 dB
THD Total harmonic distortion 0-dBFS input, 0-dB gain –86 dB

THD+N 0-dBFS input, 0-dB gain –83 dB

Total harmonic distortion +

noise

DAC DIGITAL INTERPOLATION FILTER CHARACTERISTICS

See Section 5.6.1.4 for DAC interpolation filter characteristics.

DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 4 Ω (DIFFERENTIAL), 50 pF

Output voltage Vrms

Output, common-mode 1.8 V

SNR Signal-to-noise ratio 6 dB, measured as idle-channel noise, A-weighted 88 dB

THD Total harmonic distortion –65 dB

THD+N –63 dB

Total harmonic distortion + SPKVDD = 3.6 V, BTL measurement, DAC input = –6

noise dBFS, CM = 1.8 V, class-D gain = 6 dB
PSRR Power-supply rejection ratio –44 dB

Mute attenuation 110 dB

P

O

Maximum output power 1.5 W

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a

20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 X log(∆V

Output common-mode setting = 1.65 V 0.707 Vrms

(1) (2)

(3)

Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz –62 dB

80 95 dB

RL= 32 Ω, THD+N ≤ –60 dB 20
RL= 16 Ω, THD+N ≤ –60 dB 60

SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V,
DAC input = 0 dBFS, class-D gain = 6 dB, THD ≤ 2.3
–16.5 dB

SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V,
DAC input = –2 dBFS, class-D gain = 6 dB, THD ≤ 2.1
–20 dB

SPKVDD = 3.6 V, BTL measurement, DAC input =
mute, CM = 1.8 V, class-D gain = 6 dB

SPKVDD = 3.6 V, BTL measurement, class-D gain =
(with respect to full-scale output value of 2.3 Vrms)

SPKVDD = 3.6 V, BTL measurement, DAC input = –6
dBFS, CM = 1.8 V, class-D gain = 6 dB

SPKVDD = 3.6 V, BTL measurement, ripple on
SPKVDD = 200 mVp-p at 1 kHz

SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V,
class-D gain = 18 dB, THD = 10%

1

SPKVDD = 4.3 V, BTL measurement, CM = 1.8 V,
class-D gain = 18 dB, THD = 10%

SPKVDD = 5.5 V, BTL measurement, CM = 1.8 V,
class-D gain = 18 dB, THD = 10%

/ ∆V

HPL

HPVDD

).

2.5

6 ELECTRICAL SPECIFICATIONS Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

Electrical Characteristics (continued)

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS(audio) = 48 kHz,
CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC OUTPUT TO CLASS-D SPEAKER OUTPUT; LOAD = 8 Ω (DIFFERENTIAL), 50 pF

SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V,
DAC input = 0 dBFS, class-D gain = 6 dB, THD ≤ 2.2

Output voltage Vrms

Output, common-mode 1.8 V

SNR Signal-to-noise ratio 6 dB, measured as idle-channel noise, A-weighted 87 dB

THD Total harmonic distortion –67 dB

THD+N –66 dB

Total harmonic distortion + SPKVDD = 3.6 V, BTL measurement, DAC input = –6

noise dBFS, CM = 1.8 V, class-D gain = 6 dB
PSRR Power-supply rejection ratio

Mute attenuation 110 dB

P

O

Maximum output power 1 W

Output-stage leakage current SPKVDD = 4.3 V, device is powered down

for direct battery connection (power-up-reset condition)

DAC POWER CONSUMPTION

DAC power consumption based per selected processing block, see Section 5.4

(1) DAC to speaker-out PSRR is a differential measurement calculated as PSRR = 20 × log(∆V

–16.5 dB
SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V,

DAC input = –2 dBFS, class-D gain = 6 dB, THD ≤ 2.1
–20 dB

SPKVDD = 3.6 V, BTL measurement, DAC input =
mute, CM = 1.8 V, class-D gain = 6 dB

SPKVDD = 3.6 V, BTL measurement, class-D gain =
(with respect to full-scale output value of 2.3 Vrms)

SPKVDD = 3.6 V, BTL measurement, DAC input = –6
dBFS, CM = 1.8 V, class-D gain = 6 dB

SPKVDD = 3.6 V, BTL measurement, ripple on

(1)

SPKVDD = 200 mVp-p at 1 kHz

SPKVDD = 3.6 V, BTL measurement, CM = 1.8 V,
class-D gain = 18 dB, THD = 10%

SPKVDD = 4.3 V, BTL measurement, CM = 1.8 V,
class-D gain = 18 dB, THD = 10%

SPKVDD = 5.5 V, BTL measurement, CM = 1.8 V,
class-D gain = 18 dB, THD = 10%

SPK(P + M)

/ ∆V

–44 dB

0.7

1.6

80 nA

).

SPKVDD

Copyright © 2009, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 7

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

T0145-10

WCLK

BCLK

DIN

t (WS)

d

t (DI)

S

t (DI)

h

t

r

t

f

TLV320DAC3120

SLAS659–NOVEMBER 2009

Electrical Characteristics (continued)

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPKVDD = 3.6 V, DVDD = 1.8 V, fS(audio) = 48 kHz,
CODEC_CLKIN = 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUT/OUTPUT

Logic family CMOS

V

IH

IIH= 5 μA, IOVDD ≥ 1.6 V
IIH= 5 μA, IOVDD < 1.6 V IOVDD

V

IL

V

OH

V

OL

Logic level

IIL= 5 μA, IOVDD ≥ 1.6 V –0.3
IIL= 5 μA, IOVDD < 1.6 V 0
IOH= 2 TTL loads V

IOL= 2 TTL loads V

Capacitive load 10 pF

0.7 ×

IOVDD

0.8 ×

IOVDD

3.4 Timing Characteristics

3.4.1 I2S/LJF/RJF Timing in Master Mode

0.3 ×

IOVDD

0.1 ×

IOVDD

www.ti.com

V

V

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization but not tested at final test.

PARAMETER IOVDD = 1.1 V IOVDD = 3.3 V UNIT

MIN MAX MIN MAX

td(WS) WCLK delay 45 20 ns
ts(DI) DIN setup 8 6 ns
th(DI) DIN hold 8 6 ns
t

r

t

f

Rise time 25 10 ns
Fall time 25 10 ns

Figure 3-1. I2S/LJF/RJF Timing in Master Mode

8 ELECTRICAL SPECIFICATIONS Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

T0145-11

WCLK

BCLK

DIN

t (WS)

h

t (BCLK)

H

t (DI)

S

t (BCLK)

L

t (DI)

h

t (WS)

S

t

r

t

f

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

3.4.2 I2S/LJF/RJF Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization but not tested at final test.

PARAMETER UNIT

tH(BCLK) BCLK high period 35 35 ns
tL(BCLK) BCLK low period 35 35 ns
ts(WS) WCLK setup 8 6 ns
th(WS) WCLK hold 8 6 ns
ts(DI) DIN setup 8 6 ns
th(DI) DIN hold 8 6 ns
t

r

t

f

Rise time 4 4 ns
Fall time 4 4 ns

Figure 3-2. I2S/LJF/RJF Timing in Slave Mode

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

Copyright © 2009, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 9

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

T0146-09

WCLK

BCLK

DIN

t (WS)

d

t (WS)

d

t (DI)

S

t (DI)

h

t

f

t

r

TLV320DAC3120

SLAS659–NOVEMBER 2009

3.4.3 DSP Timing in Master Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization but not tested at final test.

www.ti.com

PARAMETER UNIT

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

td(WS) WCLK delay 45 20 ns
ts(DI) DIN setup 8 8 ns
th(DI) DIN hold 8 8 ns
t

r

t

f

Rise time 25 10 ns
Fall time 25 10 ns

Figure 3-3. DSP Timing in Master Mode

10 ELECTRICAL SPECIFICATIONS Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

T0146-10

WCLK

BCLK

DIN

t (WS)

h

t (WS)

h

t (BCLK)

L

t

r

t

f

t (DI)

S

t (BCLK)

H

t (DI)

h

t (WS)

S

t (WS)

S

TLV320DAC3120

www.ti.com

3.4.4 DSP Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization but not tested at final test.

SLAS659–NOVEMBER 2009

PARAMETER UNIT

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

tH(BCLK) BCLK high period 35 35 ns
tL(BCLK) BCLK low period 35 35 ns
ts(WS) WCLK setup 8 8 ns
th(WS) WCLK hold 8 8 ns
ts(DI) DIN setup 8 8 ns
th(DI) DIN hold 8 8 ns
t

r

t

f

Rise time 4 4 ns
Fall time 4 4 ns

Figure 3-4. DSP Timing in Slave Mode

Copyright © 2009, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 11

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

STO

STA STA

STO

SDA

SCL

t

BUF

t

LOW

t

SU;STA

t

HIGH

t

HD;STA

t

r

t

HD;STA

t

HD;DAT

t

SU;DAT

t

SU;STO

t

f

T0295-02

TLV320DAC3120

SLAS659–NOVEMBER 2009

3.4.5 I2C Interface Timing

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization but not tested at final test.

PARAMETER Standard-Mode Fast-Mode UNITS

MIN TYP MAX MIN TYP MAX

f

SCL

t

HD;STA

t

LOW

t

HIGH

t

SU;STA

t

HD;DAT

t

SU;DAT

t

r

t

f

t

SU;STO

t

BUF

C

b

SCL clock frequency 0 100 0 400 kHz
Hold time (repeated) START condition. 4 0.8 μs

After this period, the first clock pulse is
generated.

LOW period of the SCL clock 4.7 1.3 μs
HIGH period of the SCL clock 4 0.6 μs
Setup time for a repeated START 4.7 0.8 μs

condition
Data hold time: For I2C bus devices 0 3.45 0 0.9 μs
Data setup time 250 100 ns
SDA and SCL rise time 1000 20 + 0.1 C
SDA and SCL fall time 300 20 + 0.1 C

b
b

Set-up time for STOP condition 4 0.8 μs
Bus free time between a STOP and 4.7 1.3 μs

START condition
Capacitive load for each bus line 400 400 pF

Figure 3-5. I2C Interface Timing

www.ti.com

300 ns
300 ns

12 ELECTRICAL SPECIFICATIONS Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

0 5 10 15 20

Amplitude − dBFS

G001

AVDD = HPVDD = 3.3 V
IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

0 5 10 15 20

Amplitude − dBFS

G002

AVDD = HPVDD = 3.3 V
IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14

G003

THD+N − Total Harmonic Distortion + Noise − dB

PO − Output Power − W

HPVDD = 3.3 V
CM = 1.65 V

HPVDD = 3.6 V
CM = 1.8 V

HPVDD = 3 V
CM = 1.5 V

HPVDD = 2.7 V
CM = 1.35 V

IOVDD = 3.3 V
DVDD = 1.8 V
Driver Gain = 9 dB
RL = 16 Ω

TLV320DAC3120

www.ti.com

4 TYPICAL PERFORMANCE

4.1 DAC Performance

AMPLITUDE AMPLITUDE

vs vs

FREQUENCY FREQUENCY

SLAS659–NOVEMBER 2009

Figure 4-1. FFT - DAC to Line Output Figure 4-2. FFT - DAC to Headphone Output

Copyright © 2009, Texas Instruments Incorporated TYPICAL PERFORMANCE 13

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

Figure 4-3. Headphone Output Power

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

−70

−60

−50

−40

−30

−20

−10

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

G004

THD+N − Total Harmonic Distortion + Noise − dB

PO − Output Power − W

Driver Gain

= 6 dB

Driver Gain

= 12 dB

AVDD = HPVDD = 3.3 V
IOVDD = 3.3 V
SPKVDD = 5.5 V
DVDD = 1.8 V
RL = 4 Ω

Driver Gain

= 18 dB

Driver Gain

= 24 dB

−70

−60

−50

−40

−30

−20

−10

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

G005

THD+N − Total Harmonic Distortion + Noise − dB

PO − Output Power − W

AVDD = 3.3 V
HPVDD = 3.3 V
IOVDD = 3.3 V
DVDD = 1.8 V
Driver Gain = 18 dB
RL = 4 Ω

SPKVDD = 5.5 V

SPKVDD = 4.3 V

SPKVDD = 3.3 V

SPKVDD = 3.6 V

−70

−60

−50

−40

−30

−20

−10

0

0.0 0.5 1.0 1.5 2.0 2.5

G006

THD+N − Total Harmonic Distortion + Noise − dB

PO − Output Power − W

Driver Gain

= 6 dB

Driver Gain

= 12 dB

AVDD = HPVDD = 3.3 V
IOVDD = 3.3 V
SPKVDD = 5.5 V
DVDD = 1.8 V
RL = 8 Ω

Driver Gain

= 24 dB

Driver Gain

= 18 dB

−70

−60

−50

−40

−30

−20

−10

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

G007

THD+N − Total Harmonic Distortion + Noise − dB

PO − Output Power − W

AVDD = 3.3 V
HPVDD = 3.3 V
IOVDD = 3.3 V
DVDD = 1.8 V
Driver Gain = 18 dB
RL = 8 Ω

SPKVDD = 5.5 V

SPKVDD = 4.3 V

SPKVDD = 3.3 V

SPKVDD = 3.6 V

TLV320DAC3120

SLAS659–NOVEMBER 2009

4.2 Class-D Speaker Driver Performance

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

Figure 4-4. Max Class-D Speaker-Driver Output Figure 4-5. Class-D Speaker-Driver Output Power

Power (RL= 4 Ω) (RL= 4 Ω)

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs

OUTPUT POWER OUTPUT POWER

www.ti.com

Figure 4-6. Max Class-D Speaker-Driver Output Figure 4-7. Class-D Speaker-Driver Output Power

14 TYPICAL PERFORMANCE Copyright © 2009, Texas Instruments Incorporated

Power (RL= 8 Ω) (RL= 8 Ω)

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

0 5 10 15 20

Amplitude − dBFS

G008

AVDD = HPVDD = 3.3 V
IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

0 5 10 15 20

Amplitude − dBFS

G009

AVDD = HPVDD = 3.3 V
IOVDD = SPKVDD = 3.3 V
DVDD = 1.8 V

I − Current − mA

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

V − Voltage − V

G010

Micbias = 2 V

Micbias = 2.5 V

Micbias = AVDD (3.3 V)

TLV320DAC3120

www.ti.com

4.3 Analog Bypass Performance

AMPLITUDE AMPLITUDE

vs vs

FREQUENCY FREQUENCY

Figure 4-8. FFT - Line In Bypass to Line Output

SLAS659–NOVEMBER 2009

Figure 4-9. FFT - Line In Bypass to Headphone

Output

4.4 MICBIAS Performance

VOLTAGE

vs

CURRENT

Figure 4-10. Micbias

Copyright © 2009, Texas Instruments Incorporated TYPICAL PERFORMANCE 15

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

HPVDD

HPVSSSPKVDD SPKVSS

AVDD

AVSSSPKVSS

VOL/MICDET

MICBIAS

TLV320DAC3120

SPKVDD

22 Fm0.1 Fm0.1 Fm 22 Fm

SVDD

AVDD

AVSS

0.1 Fm

10 Fm

0.1 Fm

10 Fm

+3.3VA

1 Fm

DVDD

DVSS IOVDD IOVSS

0.1 Fm 10 Fm

+1.8VD

IOVDD

0.1 Fm 10 Fm

Host Processor

SDIN

BCLK

WCLK

MCLK

SCL

SDA

RESET

GPIO1

S0400-06

AIN1

AIN2

To External

MIC Circuitry

Analog In

SPKM
SPKM

SPKP
SPKP

HPR

HPL

8- or
Speaker

W 4-W

Stereo
Headphone
Out

R1

34.8 kW

P1

25 kW

R2

9.76 kW

TLV320DAC3120

SLAS659–NOVEMBER 2009

5 APPLICATION INFORMATION

5.1 Typical Circuit Configuration

www.ti.com

Figure 5-1. Typical Circuit Configuration

16 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

5.2 Overview

The TLV320DAC3120 is a highly integrated mono audio DAC for portable computing, communication, and
entertainment applications. A register-based architecture eases integration with microprocessor-based
systems through standard serial-interface buses. This device contains a two-wire I2C bus interface, which
allows full register access. All peripheral functions are controlled through these registers and the onboard
state machines.

The TLV320DAC3120 consists of the following blocks:

• miniDSP digital signal-processing block

• Audio DAC

• Dynamic range compressor (DRC)

• Mono headphone/lineout amplifier

• Class-D mono amplifier capable of driving 4-Ω or 8-Ω speakers

• Pin-controlled or register-controlled volume level

• Power-down de-pop and power-up soft start

• Analog inputs

• I2C control interface

• Power-down control block
Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C

interface is used to write to the control registers to configure the device.
The I2C address assigned to the TLV320DAC3120 is 001 1000. This device always operates in an I2C

slave mode. All registers are 8-bit, and all writable registers have readback capability. The device
auto-increments to support sequential addressing and can be used with I2C fast mode. Once the device is
reset, all appropriate registers are updated by the host processor to configure the device as needed by the
user.

5.2.1 Device Initialization

5.2.1.1 Reset

The TLV320DAC3120 internal logic must be initialized to a known condition for proper device function. To
initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low
for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up.
It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low.

The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the
device.

5.2.1.2 Device Start-Up Lockout Times

After the TLV320DAC3120 is initialized through hardware reset at power-up or software reset, the internal
memories are initialized to default values. This initialization takes place within 1 ms after pulling the
RESET signal high. During this initialization phase, no register-read or register-write operation should be
performed on the DAC coefficient buffers. Also, no block within the codec should be powered up during
the initialization phase.

5.2.1.3 PLL Start-Up

Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up
command of the PLL and before the clocks are available to the codec. This delay is to ensure stable
operation of the PLL and clock-divider logic.

Copyright © 2009, Texas Instruments Incorporated APPLICATION INFORMATION 17

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

SLAS659–NOVEMBER 2009

5.2.1.4 Power-Stage Reset

The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has
occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.
Each of the two power stages has its own dedicated reset bit. The headphone power-stage reset is
performed by setting page 1 / register 31, bit D7 for HPOUT. The speaker power-stage reset is performed
by setting page 1 / register 32, bit D7 for SPKP and SPKM.

5.2.1.5 Software Power Down

By default, all circuit blocks are powered down following a reset condition. Hardware power up of each
circuit block can be controlled by writing to the appropriate control register. This approach allows the
lowest power-supply current for the functionality required. However, when a block is powered down, all of
the register settings are maintained as long as power is still being applied to the device.

5.2.2 Audio Analog I/O

The TLV320DAC3120 features a mono audio DAC. It supports a wide range of analog interfaces to
support different headsets and analog outputs. The TLV320DAC3120 interfaces to output drivers (8-Ω,
16-Ω, 32-Ω).

5.3 miniDSP

The TLV320DAC3120 features a miniDSP core which is tightly coupled to the DAC. The fully
programmable algorithms for the miniDSP must be loaded into the device after power up. The miniDSP
has direct access to the digital stereo audio stream, offering the possibility for advanced, very
low-group-delay DSP algorithms. The miniDSP has 1024 programmable instructions, 896 data memory
locations, and 512 programmable coefficients (in the adaptive mode, each bank has 256 programmable
coefficients).

www.ti.com

5.3.1 Software

Software development for the TLV320DAC3120 is supported through TI's comprehensive PurePath™
Studio software development environment, a powerful, easy-to-use tool designed specifically to simplify
software development on Texas Instruments miniDSP audio platforms. The graphical development
environment consists of a library of common audio functions that can be dragged and dropped into an
audio signal flow and graphically connected together. The DSP code can then be assembled from the
graphical signal flow with the click of a mouse. See the TLV320DAC3120 product folder on www.ti.com to
learn more about PurePath Studio and the latest status on available, ready-to-use DSP algorithms.

5.4 Digital Processing Low-Power Modes

The TLV320DAC3120 device can be tuned to minimize power dissipation, to maximize performance, or to
an operating point between the two extremes to best fit the application. The choice of processing blocks,
PRB_P4 to PRB_P22 for mono playback and PRB_R4 to PRB_R18 for mono recording, also influences
the power consumption. In fact, the numerous processing blocks have been implemented to offer a choice
among configurations having a different balance of power-optimization and signal-processing capabilities.

18 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

5.4.1 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.4 mW

Table 5-1. PRB_P12 Alternative Processing Blocks, 15.4 mW

Processing Block Filter Estimated Power Change (mW)

PRB_P4 A 0.57
PRB_P5 A 1.48

PRB_P6 A 1.08
PRB_P13 B 0.56
PRB_P14 B 0.27
PRB_P15 B 0.89
PRB_P16 B 0.31

DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.54 mW

Table 5-2. PRB_P12 Alternative Processing Blocks, 15.54 mW

Processing Block Filter Estimated Power Change (mW)

PRB_P4 A 0.37

PRB_P5 A 1.23

PRB_P6 A 1.15
PRB_P13 B 0.43
PRB_P14 B 0.13
PRB_P15 B 0.85
PRB_P16 B 0.21

5.4.2 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.49 mW

Table 5-3. PRB_P12 Alternative Processing Blocks, 14.49 mW

Processing Block Filter Estimated Power Change (mW)

PRB_P4 A –0.04
PRB_P5 A 0.2

PRB_P6 A –0.01
PRB_P13 B 0.1
PRB_P14 B 0.05
PRB_P15 B –0.03
PRB_P16 B 0.07

Copyright © 2009, Texas Instruments Incorporated APPLICATION INFORMATION 19

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

SLAS659–NOVEMBER 2009

DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.42 mW

Table 5-4. PRB_P12 Alternative Processing Blocks, 14.42 mW

Processing Block Filter Estimated Power Change (mW)

PRB_P4 A 0.16

PRB_P5 A 0.3

PRB_P6 A 0.2
PRB_P13 B 0.15
PRB_P14 B 0.07
PRB_P15 B 0.18
PRB_P16 B 0.09

5.5 Analog Signals

The TLV320DAC3120 analog signals consist of:

• Microphone bias (MICBIAS)

• Analog inputs AIN1 and AIN2, which can be used to pass-through or mix analog signals to output
stages

• Analog outputs class-D speaker driver and headphone/lineout driver providing output capability for the
DAC, AIN1, AIN2, or a mix of the three

www.ti.com

5.5.1 MICBIAS

The TLV320DAC3120 includes a microphone bias circuit which can source up to 4 mA of current, and is
programmable to a 2-V, 2.5-V, or AVDD level. The level can be controlled by writing to page 1 /
register 46, bits D1–D0. This functionality is shown in Table 5-5.

Table 5-5. MICBIAS Settings

D1 D0 FUNCTIONALITY

0 0 MICBIAS output is powered down.
0 1 MICBIAS output is powered to 2 V.
1 0 MICBIAS output is powered to 2.5 V.
1 1 MICBIAS output is powered to AVDD.

During normal operation, MICBIAS can be set to 2.5 V for better performance. However, depending on the
model of microphone that is selected, optimal performance might be obtained at another setting, so the
performance at a given setting should be verified.

The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current
consumption occurs when MICBIAS is set at AVDD.

5.5.2 Analog Inputs AIN1 and AIN2

AIN1 (pin 13) and AIN2 (pin 14) are inputs to the output mixer along with the DAC output. Page 1 /
register 36 provides control signals for determining the signals routed through the output mixer. The output
of the output mixer then can be attenuated or amplified through the class-D and/or headphone/lineout
drivers.

20 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

5.6 Audio DAC and Audio Analog Outputs

The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital
delta-sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is
between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated
within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include
mono headphone/lineout and mono class-D speaker outputs. Because the TLV320DAC3120 contains a
mono DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right
channels as [(L + R) ÷ 2], selected by page 0 / register 63, bits D5–D4. See Figure 1-1 for the signal flow.

5.6.1 DAC

The TLV320DAC3120 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of
the mono DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction
filter. The DAC is designed to provide enhanced performance at low sampling rates through increased
oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma
modulator and observed in the signal images strongly suppressed within the audio band to beyond 20
kHz. To handle multiple input rates and optimize power dissipation and performance, the
TLV320DAC3120 allows the system designer to program the oversampling rates over a wide range from 1
to 1024 by configuring page 0 / register 13 and page 0 / register 14. The system designer can choose
higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data
rates.

The TLV320DAC3120 DAC channel includes a built-in digital interpolation filter to generate oversampled
data for the delta-sigma modulator. The interpolation filter can be chosen from three different types,
depending on required frequency response, group delay, and sampling rate.

DAC power up is controlled by writing to page 0 / register 63, bit D7 for the mono channel. The
mono-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7.

5.6.1.1 DAC Processing Blocks

The TLV320DAC3120 implements signal-processing capabilities and interpolation filtering via processing
blocks. These fixed processing blocks give users the choice of how much and what type of signal
processing they may use and which interpolation filter is applied.

The choices among these processing blocks allows the system designer to balance power conservation
and signal-processing flexibility. Table 5-6 gives an overview of all available processing blocks of the DAC
channel and their properties. The resource-class column gives an approximate indication of power
consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog
power consumption of the drivers (HPVDD) may differ.

The signal-processing blocks available are:

• First-order IIR

• Scalable number of biquad filters

The processing blocks are tuned for common cases and can achieve high image rejection or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR and biquad filters have fully user-programmable coefficients.

Copyright © 2009, Texas Instruments Incorporated APPLICATION INFORMATION 21

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

Interp.
Filter A

BiQuad

C

BiQuad

B

BiQuad

A

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

Filter

A,B

DRCHPF

BiQuad

F

BiQuad

E

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

IIR

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

Filter

A,B

BiQuad

F

BiQuad

E

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

IIR

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

TLV320DAC3120

SLAS659–NOVEMBER 2009

Table 5-6. Overview – DAC Predefined Processing Blocks

Processing First-Order Number of Resource

Block No. IIR Available Biquads Class

PRB_P4 A Mono No 3 No 4
PRB_P5 A Mono Yes 6 Yes 6

PRB_P6 A Mono Yes 6 No 6
PRB_P12 B Mono Yes 0 No 3
PRB_P13 B Mono No 4 Yes 4
PRB_P14 B Mono No 4 No 4
PRB_P15 B Mono Yes 6 Yes 6
PRB_P16 B Mono Yes 6 No 4
PRB_P20 C Mono Yes 0 No 2
PRB_P21 C Mono Yes 4 Yes 3
PRB_P22 C Mono Yes 4 No 2

Interpolation Filter Channel DRC

5.6.1.2 DAC Processing Blocks – Signal Chain Details

5.6.1.2.1 Three Biquads, Filter A

www.ti.com

Figure 5-2. Signal Chain for PRB_P4

5.6.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B

Figure 5-3. Signal Chain for PRB_P5 and PRB_P15

5.6.1.2.3 Six Biquads, First-Order IIR, Filter A or B

Figure 5-4. Signal Chain for PRB_P6 and PRB_P16

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

22 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Interp.

Filter

B,C

IIR

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

FilterB

DRCHPF

to

Modulator

Digital

Volume

Ctrl

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

from

Interface

´

Interp.

FilterB

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

FilterC

DRCHPF

IIR

to

Modulator

Digital

Volume

Ctrl

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

from

Interface

´

Interp.

FilterC

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

IIR

to

modulator

Digital

Volume

Ctrl

from

Interface

´

TLV320DAC3120

www.ti.com

5.6.1.2.4 IIR, Filter B or C

Figure 5-5. Signal Chain for PRB_P12 and PRB_P20

5.6.1.2.5 Four Biquads, DRC, Filter B

Figure 5-6. Signal Chain for PRB_P13

5.6.1.2.6 Four Biquads, Filter B

SLAS659–NOVEMBER 2009

Figure 5-7. Signal Chain for PRB_P14

5.6.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C

Figure 5-8. Signal Chain for PRB_P21

5.6.1.2.8 Four Biquads, First-Order IIR, Filter C

Figure 5-9. Signal Chain for PRB_P22

Product Folder Link(s): TLV320DAC3120

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated APPLICATION INFORMATION 23

LargestPositiveNumber:

=0.111 1111 1111 111
=0.999969482421875=1.0 – 1LSB

1

LargestNegativeNumber:

=1.0000 0000 0000 000
=0x8000= –1.0(bydefinition)

1 1 1

1 1 1

S.xxxx xxxx xxxx xxx.. x x x

SignBit

2 Bit

–1

2 Bit

–4

2 Bit

–15

Fraction

Point

TLV320DAC3120

SLAS659–NOVEMBER 2009

5.6.1.3 DAC User-Programmable Filters

Depending on the selected processing block, different types and orders of digital filtering are available. Up
to six biquad sections are available for specific processing blocks.

The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If
adaptive filtering is chosen, the coefficient banks can be switched in real time.

When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed
for either read or write.

However, the TLV320DAC3120 offers an adaptive filter mode as well. Setting page 8 / register 1,
bit D2 = 1 turns on double buffering of the coefficients. In this mode, filter coefficients can be updated
through the host and activated without stopping and restarting the DAC. This enables advanced adaptive
filtering applications.

In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC
is running and adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the
coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At
the same time, page 8 / register 1, bit D1 toggles.

The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use.
Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use.
While the device is running, coefficient updates are always made to the buffer not in use by the DAC,

regardless of the buffer to which the coefficients have been written.

www.ti.com

Table 5-7. Adaptive-Mode Filter-Coefficient Buffer Switching

DAC Powered Up Page 8, Reg 1, Bit D1 I2C Writes to Updates

No 0 None Page 8, Reg 2–3, buffer A Page 8, Reg 2–3, buffer A
No 0 None Page 12, Reg 2–3, buffer Page 12, Reg 2–3, buffer B

Yes 0 Buffer A Page 8, Reg 2–3, buffer A Page 12, Reg 2–3, buffer B
Yes 0 Buffer A Page 12, Reg 2–3, buffer Page 12, Reg 2–3, buffer B

Yes 1 Buffer B Page 8, Reg 2–3, buffer A Page 8, Reg 2–3, buffer A
Yes 1 Buffer B Page 12, Reg 2–3, buffer Page 8, Reg 2–3, buffer A

Coefficient Buffer in

Use

B

B

B

The user-programmable coefficients for the DAC processing blocks are defined on pages 8 and 9 for
buffer A and pages 12 and 13 for buffer B.

The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit
registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a
range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 5-10.

24 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): TLV320DAC3120

Figure 5-10.

Submit Documentation Feedback

1

0 1

15 1

1

N N z

H(z)

2 D z

-

-

+

=

-

1 2

0 1 2

15 1 2

1 2

N 2 N z N z

H(z)

2 2 D z D z

- -

- -

+ ´ +

=

- ´ -

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

5.6.1.3.1 First-Order IIR Section

The IIR is of first order and its transfer function is given by

The frequency response for the first-order IIR section with default coefficients is flat.

Table 5-8. DAC IIR Filter Coefficients

Filter Filter Coefficient Default (Reset) Values

First-order IIR N0 Page 9 / registers 2–3 0x7FFF (decimal 1.0 – LSB value)

N1 Page 9 / registers 4–5 0x0000
D1 Page 9 / registers 6–7 0x0000

DAC Coefficient,

Mono Channel

5.6.1.3.2 Biquad Section

The transfer function of each of the biquad filters is given by

Table 5-9. DAC Biquad Filter Coefficients

(1)

(2)

Filter Coefficient Mono DAC Channel Default (Reset) Values

Biquad A N0 Page 8 / registers 2–3 0x7FFF (decimal 1.0 – LSB value)

N1 Page 8 / registers 4–5 0x0000
N2 Page 8 / registers 6–7 0x0000
D1 Page 8 / registers 8–9 0x0000
D2 Page 8 / registers 10–11 0x0000

Biquad B N0 Page 8 / registers 12–13 0x7FFF (decimal 1.0 – LSB value)

N1 Page 8 / registers 14–15 0x0000
N2 Page 8 / registers 16–17 0x0000
D1 Page 8 / registers 18–19 0x0000
D2 Page 8 / registers 20–21 0x0000

Biquad C N0 Page 8 / registers 22–23 0x7FFF (decimal 1.0 – LSB value)

N1 Page 8 / registers 24–25 0x0000
N2 Page 8 / registers 26–27 0x0000
D1 Page 8 / registers 28–29 0x0000
D2 Page 8 / registers 30–31 0x0000

Biquad D N0 Page 8 / registers 32–33 0x7FFF (decimal 1.0 – LSB value)

N1 Page 8 / registers 34–35 0x0000
N2 Page 8 / registers 36–37 0x0000
D1 Page 8 / registers 38–39 0x0000
D2 Page 8 / registers 40–41 0x0000

Biquad E N0 Page 8 / registers 42–43 0x7FFF (decimal 1.0 – LSB value)

N1 Page 8 / registers 44–45 0x0000
N2 Page 8 / registers 46–47 0x0000
D1 Page 8 / registers 48–49 0x0000
D2 Page 8 / registers 50–51 0x0000

Copyright © 2009, Texas Instruments Incorporated APPLICATION INFORMATION 25

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

1

3 4

5 6

7

2

Magnitude – dB

FrequencyNormalizedtof

S

DACChannelResponseforInterpolationFilter A
(RedLineCorrespondsto –65dB)

TLV320DAC3120

SLAS659–NOVEMBER 2009

Table 5-9. DAC Biquad Filter Coefficients (continued)

Filter Coefficient Mono DAC Channel Default (Reset) Values

Biquad F N0 Page 8 / registers 52–53 0x7FFF (decimal 1.0 – LSB value)

N1 Page 8 / registers 54–55 0x0000
N2 Page 8 / registers 56–57 0x0000
D1 Page 8 / registers 58–59 0x0000
D2 Page 8 / registers 60–61 0x0000

5.6.1.4 DAC Interpolation Filter Characteristics

5.6.1.4.1 Interpolation Filter A

Filter A is designed for an fSup to 48 ksps with a flat pass band of 0 kHz–20 kHz.

Table 5-10. Specification for DAC Interpolation Filter A

Parameter Condition Value (Typical) Unit

Filter-gain pass band 0 … 0.45 f
Filter-gain stop band 0.55 fS… 7.455 f
Filter group delay 21/f

S

S

±0.015 dB
–65 dB

S

www.ti.com

s

5.6.1.4.2 Interpolation Filter B

Filter B is specifically designed for an fSup to 96 ksps. Thus, the flat pass-band region easily covers the
required audio band of 0 kHz–20 kHz.

Filter-gain pass band 0 … 0.45 f
Filter-gain stop band 0.55 fS… 3.45 f
Filter group delay 18/f

26 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Parameter Condition Value (Typical) Unit

Figure 5-11. Frequency Response of DAC Interpolation Filter A

Table 5-11. Specification for DAC Interpolation Filter B

±0.015 dB
–58 dB

S

S

S

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

s

DACChannelResponseforInterpolationFilterB
(RedLineCorrespondsto –58dB)

0.5 1 1.5 2 2.5 3 3.5

FrequencyNormalizedtof

S

0

–10

–20

–30

–40

–50

–60

–70

–80

Magnitude – dB

0

–10

–20

–30

–40

–50

–60

–70

Magnitude – dB

0 0.2 0.4 0.6 0.8 1 1.2 1.4

FrequencyNormalizedtof

S

DACChannelResponseforInterpolationFilterC
(RedLineCorrespondsto –43dB)

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

Figure 5-12. Frequency Response of Channel Interpolation Filter B

5.6.1.4.3 Interpolation Filter C

Filter C is specifically designed for the 192-ksps mode. The pass band extends up to 0.4 × f
(corresponds to 80 kHz), more than sufficient for audio applications.

S

Figure 5-13. Frequency Response of DAC Interpolation Filter C

Table 5-12. Specification for DAC Interpolation Filter C

Parameter Condition Value (Typical) Unit

Filter-gain pass band 0 … 0.35 f
Filter-gain stop band 0.6 fS… 1.4 f
Filter group delay 13/f

5.6.2 DAC Digital-Volume Control

The DAC has a digital volume-control block which implements programmable gain. Each channel has an
independent volume control that can be varied from 24 dB to –63.5 dB in 0.5-dB steps. The mono-channel
DAC volume can be controlled by writing to page 0 / register 65, bits D7–D0. DAC muting and setting up a
master gain control to control the mono channel is done by writing to page 0 / register 64, bits D3 and D1.
The gain is implemented with a soft-stepping algorithm, which only changes the actual volume by

Copyright © 2009, Texas Instruments Incorporated APPLICATION INFORMATION 27

S

S

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

±0.03 dB
–43 dB

S

s

TLV320DAC3120

SLAS659–NOVEMBER 2009

0.125 dB per input sample, either up or down, until the desired volume is reached. The rate of
soft-stepping can be slowed to one step per two input samples by writing to page 0 / register 63, bits
D1–D0. Note that the default source for volume-control level settings is controlled by register writes to
page 0 / register 65. Use of the VOL/MICDET pin to control the DAC volume is ignored until the
volume-control source selected has been changed to pin control (page 0 / register 116, bit D7 = 1). This
functionality is shown in Figure 1-1.

During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This
may be important if the host must mute the DAC before making a significant change, such as changing
sample rates. In order to help with this situation, the device provides a flag back to the host via a
read-only register, page 0 / register 38, bit D4 for the mono channel. This information alerts the host when
the part has completed the soft-stepping, and the actual volume has reached the desired volume level.
The soft-stepping feature can be disabled by writing to page 0 / register 63, bits D1–D0.

If soft-stepping is enabled, the CODEC_CLKIN signal should be kept active until the DAC power-up flag is
cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and
CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an
internal oscillator.)

5.6.3 Volume-Control Pin

The range of voltages used by the 7-bit SAR ADC is shown in the Electrical Characteristics table.
The volume-control pin is not enabled by default, but it can be enabled by writing 1 to page 0 /

register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if
page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63,
bits D1–D0.

www.ti.com

When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and
updates the digital volume control. (It overwrites the current value of the volume control.) The new volume
setting which has been applied due to a change of voltage on the volume control pin can be read on
page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source can be selected on page 0 /
register 116, bit D6. The update rate can be programmed on page 0 / register 116, bits D2–D0 for this
7-bit SAR ADC.

The VOL/MICDET pin gain mapping is shown in Table 5-13.

Table 5-13. VOL/MICDET Pin Gain Mapping

VOL/MICDET PIN SAR OUTPUT DIGITAL GAIN APPLIED

0 18 dB
1 17.5 dB
2 17 dB

: :
35 0.5 dB
36 0.0 dB
37 –0.5 dB

: :
89 –26.5 dB
90 –27 dB
91 –28 dB

: :

125 –62 dB
126 –63 dB
127 Mute

28 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

1

0 1

HPF

15 1

1

N N z

H (z)

2 D z

-

-

+

=

-

1

0 1

LPF

15 1

1

N N z

H (z)

2 D z

-

-

+

=

-

TLV320DAC3120

www.ti.com

SLAS659–NOVEMBER 2009

The VOL/MICDET pin connection and functionality are shown in Figure 1-1.
As shown in Table 5-13, the VOL/MICDET pin has a range of volume control from 18 dB down to –63 dB,

and mute. However, if less maximum gain is required, then a smaller range of voltage should be applied
to the VOL/MICDET pin. This can be done by increasing the value of R2 relative to the value of (P1 + R1),
so that more voltage is available at the bottom of P1. The circuit should also be designed such that for the
values of R1, R2, and P1 chosen, the maximum voltage (top of the potentiometer) does not exceed
AVDD/2 (see Figure 5-1). The recommended values for R1, R2, and P1 for several maximum gains are
shown in Table 5-14. Note that In typical applications, R1 should not be 0 Ω, as the VOL/MICDET pin
should not exceed AVDD/2 for proper ADC operation.

Table 5-14. VOL/MICDET Pin Gain Scaling

R1 P1 R2 DIGITAL GAIN RANGE

(kΩ) (kΩ) (kΩ) (dB)

25 25 0 0 V to 1.65 V 18 dB to –63 dB
33 25 7.68 0.386 V to 1.642 V 3 dB to –63 dB

34.8 25 9.76 0.463 V to 1.649 V 0 dB to –63 dB

ADC VOLTAGE

for AVDD = 3.3 V

(V)

5.6.4 Dynamic Range Compression

Typical music signals are characterized by crest factors, the ratio of peak signal power to average signal
power, of 12 dB or more. To avoid audible distortions due to clipping of peak signals, the gain of the DAC
channel must be adjusted so as not to cause hard clipping of peak signals. As a result, during nominal
periods, the applied gain is low, causing the perception that the signal is not loud enough. To overcome
this problem, DRC in the TLV320DAC3120 continuously monitors the output of the DAC digital volume
control to detect its power level relative to 0 dBFS. When the power level is low, DRC increases the input
signal gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously
reduces the applied gain to avoid hard clipping. This results in sounds more pleasing to the ear as well as
sounding louder during nominal periods.

The DRC functionality in the TLV320DAC3120 is implemented by a combination of processing blocks in
the DAC channel as described in Section 5.6.1.2.

DRC can be disabled by writing to page 0 / register 68, bits D6–D5.
DRC typically works on the filtered version of the input signal. The input signals have no audio information

at dc and extremely low frequencies; however, they can significantly influence the energy estimation
function in DRC. Also, most of the information about signal energy is concentrated in the low-frequency
region of the input signal.

To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the
DRC low-pass filter. These filters are implemented as first-order IIR filters given by

(3)

(4)

The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable
through register write as given in Table 5-15.

Copyright © 2009, Texas Instruments Incorporated APPLICATION INFORMATION 29

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120

TLV320DAC3120

SLAS659–NOVEMBER 2009

Table 5-15. DRC HPF and LPF Coefficients

Coefficient Location

HPF N0 C71 page 9 / registers 14 to 15
HPF N1 C72 page 9 / registers 16 to 17
HPF D1 C73 page 9 / registers 18 to 19
LPF N0 C74 page 9 / registers 20 to 21
LPF N1 C75 page 9 / registers 22 to 23
LPF D1 C76 page 9 / registers 24 to 25

The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_fS,
and a low-pass filter with a cutoff at 0.00033 × DAC_fS.

The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The
absolute value of the DRC-LPF filter is used for energy estimation within the DRC.

The gain in the DAC digital volume control is controlled by page 0 / registers 65 and 66. When the DRC is
enabled, the applied gain is a function of the digital volume-control register setting and the output of the
DRC.

The DRC parameters are described in sections that follow.

5.6.4.1 DRC Threshold

The DRC threshold represents the level of the DAC playback signal at which the gain compression
becomes active. The output of the digital volume control in the DAC is compared with the set threshold.
The threshold value is programmable by writing to page 0 / register 68, bits D4–D2. The threshold value
can be adjusted between –3 dBFS and –24 dBFS in steps of 3 dB. Keeping the DRC threshold value too
high may not leave enough time for the DRC block to detect peaking signals, and can cause excessive
distortion at the outputs. Keeping the DRC threshold value too low can limit the perceived loudness of the
output signal.

www.ti.com

The recommended DRC threshold value is –24 dB.
When the output signal exceeds the set DRC threshold, the interrupt flag bits at page 0 / register 44,

bits D3–D2 are updated. These flag bits are sticky in nature, and are reset only after they are read back
by the user. The non-sticky versions of the interrupt flags are also available at page 0 / register 46, bits
D3–D2.

5.6.4.2 DRC Hysteresis

DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be
programmed to represent values between 0 dB and 3 dB in steps of 1 dB. It is a programmable window
around the programmed DRC threshold that must be exceeded for disabled DRC to become enabled, or
enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the DRC
hysteresis is set to 3 dB, then if the gain compression in DRC is inactive, the output of the DAC digital
volume control must exceed –9 dBFS before gain compression due to the DRC is activated. Similarly,
when the gain compression in the DRC is active, the output of the DAC digital volume control must fall
below –15 dBFS for gain compression in the DRC to be deactivated. The DRC hysteresis feature prevents
the rapid activation and de-activation of gain compression in DRC in cases when the output of the DAC
digital volume control rapidly fluctuates in a narrow region around the programmed DRC threshold. By
programming the DRC hysteresis as 0 dB, the hysteresis action is disabled.

The recommended value of DRC hysteresis is 3 dB.

30 APPLICATION INFORMATION Copyright © 2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TLV320DAC3120