TEXAS INSTRUMENTS TLV320AIC32 Technical data

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TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

FEATURES DESCRIPTION

• Stereo Audio DAC

– 100 dB A Signal-to-Noise Ratio – 16/20/24/32-Bit Data – Supports Rates From 8 kHz to 96 kHz – 3D/Bass/Treble/EQ/De-Emphasis Effects enabling stereo 48-kHz DAC playback as low as 14

• Stereo Audio ADC

– 92 dB A Signal-to-Noise Ratio – Supports Rates From 8 kHz to 96 kHz

• Six Audio Input Pins – Six Stereo Single-Ended Inputs stereo-microphone pre-amp, and automatic gain

• Six Audio Output Drivers – Stereo 8- Ω , 500 mw/Channel Speaker Drive

Capability

– Stereo Fully-Differential or Single-Ended

Headphone Drivers

– Fully Differential Stereo Line Outputs

• Low Power: 14-mW Stereo, 48-kHz Playback With 3.3-V Analog Supply

• Programmable Input/Output Analog Gains

• Automatic Gain Control (AGC) for Record

• Programmable Microphone Bias Level

• Programmable PLL for Flexible Clock

Generation

• I2C Control Bus

• Audio Serial Data Bus Supports I2S,

Left/Right-Justified, DSP, and TDM Modes

• Extensive Modular Power Control

• Power Supplies:

– Analog: 2.7 V – 3.6 V – Digital Core: 1.525 V – 1.95 V – Digital I/O: 1.1 V – 3.6 V

• Available Packages: 5 × 5 mm, 32-Pin QFN

The TLV320AIC32 is a low-power stereo-audio codec with a stereo headphone amplifier, as well as multiple inputs and outputs, programmable in single-ended or fully-differential configurations. Extensive register-based power control is included,

mW from a 3.3-V analog supply, making it ideal for portable, battery-powered audio and telephony applications.

The record path of the TLV320AIC32 contains integrated microphone bias, digitally-controlled

control (AGC), with mix/mux capability among the multiple analog inputs. The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.

The TLV320AIC32 contains four high-power output drivers as well as two fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16- Ω headphones using ac-coupling capacitors, or stereo 16- Ω headphones in a cap-less output configuration. In addition, pairs of drivers can be used to drive 8- Ω speakers in a BTL configuration at 500 mW per channel.

The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32 kHz, 44.1 kHz, and 48 kHz rates. The stereo-audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers providing up to +59.5 dB analog gain for low-level microphone inputs.

The serial control bus supports the I2C protocol, while the serial-audio data bus is programmable for I2S, left/right justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with special attention paid to the most popular cases of 12 MHz, 13 MHz, 16 MHz,

19.2 MHz, and 19.68 MHz system clocks.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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LINE_OUT_L+

LINE_OUT_L-

LINE_OUT_R+

LINE_OUT_R-

HPR+

HPL-/HPLCOM

HPL+

MIC2/LINE2L

MIC1/LINE1L

MIC1/LINE1R

MIC3/LINE3R

MIC3/LINE3L

PGA

0/+59.5dB

0.5dB steps

ADC

Audio Serial

Bus

DAC

DIN

DOUT

BCLK

WCLK

I C2Control

Bus

Audio Clock

Generation

MCLK

Bias/

Reference

MICBIAS

Voltage Supplies

AVDD_DAC

AVSS_DAC

DRVDD

DVDD

DVSS

IOVDD

Volume Ctl

& Effects

Volume Ctl

& Effects

DRVDD

DRVSS

SCL

SDA

AVSS_ADC

RESETB

MIC2/LINE2R

VCM

HPR-/HPRCOM/ SPKFC

VCM

PGA

0/+59.5dB

0.5dB steps

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

The TLV320AIC32 operates from an analog supply of 2.7 V – 3.6 V, a digital core supply of 1.525 V –

1.95 V, and a digital I/O supply of 1.1 V – 3.6 V. The

device is available in a 5 × 5 mm, 32-lead QFN package.

SIMPLIFIED BLOCK DIAGRAM

Figure 1. Simplified Codec Block Diagram

PACKAGE/ORDERING INFORMATION

OPERATING

RANGE

TLV320AIC32IRHBR Tape and Reel, 3000

PRODUCT PACKAGE TEMPERATURE ORDERING NUMBER

TLV320AIC32 QFN-32 RHB –40 ° C to 85 ° C TLV320AIC32IRHBT Tape and Reel, 250

PACKAGE TRANSPORT

DESIGNATOR MEDIA, QUANTITY

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(bottomview)

Thisisatest

DEVICE INFORMATION

PIN ASSIGNMENTS

TERMINAL FUNCTIONS

TERMINAL

NAME QFN NO. I/O

MCLK 1 I Master clock input BCLK 2 I/O Audio serial data bus bit clock input/output WCLK 3 I/O Audio serial data bus word clock input/output DIN 4 I Audio serial data bus data input DOUT 5 O Audio serial data bus data output DVSS 6 I/O Digital core / I/O Ground Supply, 0 V IOVDD 7 I/O Digital I/O voltage supply, 1.1 V – 3.6 V SCL 8 I/O I2C serial clock input SDA 9 I/O I2C serial data input/output MIC1L/LINE1L 10 I Left input 1 MIC1R/LINE1R 11 I Right input 1 MIC2L/LINE2L 12 I Left input 2 MIC2R/LINE2R 13 I Right input 2 MIC3L/LINE3L 14 I Left input 3 MICBIAS 15 O Microphone bias voltage output MIC3R/LINE3R 16 I Right input 3 AVSS1 17 I Analog ADC ground supply, 0 V DRVDD 18 O Analog ADC and output driver voltage supply, 2.7 V – 3.6 V HPLOUT 19 O High power output driver (left +) HPLCOM 20 O High power output driver (left - or multi-functional) DRVSS 21 O Analog output driver ground supply, 0 V HPRCOM 22 O High power output driver (right - or multi-functional) HPROUT 23 O High power output driver (right +) DRVDD 24 O Analog output driver voltage supply, 2.7 V – 3.6 V AVDD 25 I Analog DAC voltage supply, 2.7 V – 3.6 V AVSS2 26 I Analog DAC ground supply, 0 V LEFT_LOP 27 O Left line output (+) LEFT_LOM 28 O Left line output (-) RIGHT_LOP 29 O Right lineo output (+)

DESCRIPTION

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

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TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME QFN NO. I/O

RIGHT_LOM 30 O Right line output (-) RESET 31 Reset DVDD 32 I Digital core voltage supply, 1.525 V – 1.95 V

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

AVDD to AVSS1/2, DRVDD to DRVSS –0.3 to 3.9 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD to DRVDD –0.1 to 0.1 V Digital input voltage to DVSS –0.3 V to IOVDD+0.3 V Analog input voltage to AVSS1/2 –0.3 V to AVDD+0.3 V Operating temperature range -40 to +85 ° C Storage temperature range -65 to +105 ° C

TJMax Junction temperature 105 ° C

Power dissipation (T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

Thermal impedance 44 ° C/W

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

DESCRIPTION

VALUE UNIT

Max – TA) / θ

DISSIPATION RATINGS

TA= 25 ° C TA= 75 ° C TA= 85 ° C

POWER RATING POWER RATING POWER RATING

(1)

DERATING FACTOR

1.82 W 22.7 mW/ ° C 681 mW 454 mW

(1) This data was taken using 2 oz. trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in × 3 in PCB.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

AVDD, Analog supply voltage 2.7 3.3 3.6 V DRVDD1/2

DVDD IOVDD V

(1) Analog voltage values are with respect to AVSS1, AVSS2, DRVSS; digital voltage values are with respect to DVSS.

(1)

Digital core supply voltage 1.525 1.8 1.95 V Digital I/O supply voltage 1.1 1.8 3.6 V Analog full-scale 0dB input voltage (DRVDD1 = 3.3 V) 0.707 V Stereo line-output load resistance 10 k Ω Stereo headphone-output load resistance 16 Ω Digital output load capacitance 10 pF Operating free-air temperature –40 85 ° C

RMS

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SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

ELECTRICAL CHARACTERISTICS

At 25 ° C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUDIO ADC

Input signal level (0-dB) Single-ended input 0.707 V Signal-to-noise ratio, Fs = 48 kHz, 0 dB PGA gain, MIC1/LINE1 inputs

A-weighted Dynamic range, A-weighted

THD Total harmonic distortion

Power supply rejection ratio 234 Hz, 100 mVpp on AVDD, DRVDD 46 dB

ADC channel separation 1 kHz, –2 dB MIC2L to MIC2R –99 dB

ADC gain error 1 kHz input, 0 dB PGA gain 0.7 dB ADC programmable gain

amplifier maximum gain ADC programmable gain

amplifier step size

Input resistance k Ω

Input capacitance MIC1/LINE1 inputs 10 pF Input level control minimum

attenuation setting Input level control maximum

attenuation setting Input level control attenuation

step size

ADC DIGITAL DECIMATION FILTER, Fs = 48 kHz

Filter gain from 0 to 0.39 Fs ± 0.1 dB Filter gain at 0.4125 Fs –0.25 dB Filter gain at 0.45 Fs –3 dB Filter gain at 0.5 Fs –17.5 dB Filter gain from 0.55 Fs to 64 Fs –75 dB Filter group delay 17/Fs Sec

MICROPHONE BIAS

Bias voltage Programmable settings, load = 750 Ω V

(1) (2)

selected and AC-shorted to ground Fs = 48 kHz, 1-kHz –60 dB full-scale input applied at

(1) (2)

MIC1/LINE1 inputs, 0-dB PGA gain Fs = 48 kHz, 1-kHz –2dB full-scale input applied at

MIC1/LINE1 inputs, 0-dB PGA gain

1 kHz, –2 dB MIC3L to MIC3R –80

1 kHz, –2 dB MIC1L to MIC1R –-73

1-kHz input tone, R

MIC1/LINE1 inputs, routed to single ADC Input mix attenuation = 0 dB

MIC2/LINE2 inputs, input mix attenuation = 0 dB 20 MIC3/LINE3 inputs, input mix attenuation = 0 dB 20 MIC1/LINE1 inputs,

input mix attenuation = –12 dB MIC2/LINE2 inputs,

input mix attenuation = –12 dB MIC3/LINE3 inputs,

input mix attenuation = –12 dB

< 50 Ω 59.5 dB

SOURCE

80 92 dB

–90 –75 dB

0.003% 0.017%

0.5 dB

1.5 dB

2.0

2.25 2.5 2.75 AVDD-

0.2

TLV320AIC32

RMS

92 dB

0 dB

12 dB

(1) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a

20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

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TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

ELECTRICAL CHARACTERISTICS (continued)

At 25 ° C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Current sourcing 2.5 V setting 4 mA

AUDIO DAC Differential Line output, load = 10 k Ω , 50 pF

Full-scale differential output 0-dB gain to line outputs. DAC output common-mode voltage setting = 1.35 V, output level control gain = 0-dB

Signal-to-noise ratio, Fs = 48 kHz, 0-dB gain to line outputs, zero signal A-weighted

Dynamic range, A-weighted 100 dB

(3)

applied, referenced to full-scale input level Fs = 48 kHz, 0-dB gain to line outputs,

1 kHz –60 dB signal applied Total harmonic distortion Fs = 48 kHz, 1 kHz 0 dB input signal applied –93 –75 dB Power supply rejection ratio 234 Hz, 100 mVpp on AVDD, DRVDD1/2 81 dB DAC channel separation (left to

right)

1-kHz, 0-dB –100 dB DAC interchannel gain mismatch 1 kHz input, 0dB gain 0.1 dB

DAC Gain Error 1 kHz input, 0dB gain –0.4 dB

DAC DIGITAL INTERPOLATION FILTER

Fs = 48-kHz

Passband High-pass filter disabled 0.45 × Fs Hz Passband ripple High-pass filter disabled ± 0.06 dB Transition band 0.45 × Fs 0.55 × Fs Hz Stopband 0.55 × Fs 7.5 × Fs Hz Stopband attenuation 65 dB Group delay 21/Fs Sec

STEREO HEADPHONE DRIVER AC-coupled output configuration

0-dB full-scale output voltage 0.707 V

0-dB gain to high power outputs. Output

common-mode voltage setting = 1.35 V

(4)

First option 1.35 Programmable output common

mode voltage (applicable to Line V Outputs also)

Second option 1.50

Third option 1.65

Fourth option 1.8 Maximum programmable output

level control gain Programmable output level

control gain step size

Maximum output power mW

Signal-to-noise ratio, A-weighted

(5)

RL= 32 Ω 15

RL= 16 Ω 30

(3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16- Ω

single-ended load.

(4) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16- Ω

single-ended load.

(5) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to

20-kHz bandwidth.

1.414 V

4.0 V

90 100 dB

9 dB

1 dB

94 dB

RMS

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ELECTRICAL CHARACTERISTICS (continued)

At 25 ° C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1-kHz output, PO= 5 mW, RL= 32 Ω

1-kHz output, PO= 10 mW, RL= 32 Ω Total harmonic distortion dB%

1-kHz output, PO= 10 mW, RL= 16 Ω

1-kHz output, PO= 20 mW, RL= 16 Ω

Channel separation 1 kHz, 0 dB input 90 dB Power supply rejection ratio 217 Hz, 100 mVpp on AVDD, DRVDD1/2 48 dB Mute attenuation 1-kHz output 107 dB

DIGITAL I/O

Input low level IIL= +5- µ A –0.3 V

Input high level

Output low level IIH= 2 TTL loads V

Output high level IOH= 2 TTL loads V

(6)

IIH= +5- µ A V

0.7 ×

IOVDD

0.8 ×

IOVDD

SUPPLY CURRENT Fs = 48-kHz

Stereo line playback mA

Mono record Fs = 48-kHz, PLL and AGC off mA

Stereo record Fs = 48-kHz, PLL and AGC off mA

PLL mA

AVDD+DRVDD 3.0

DVDD 2.0

AVDD+DRVDD 2

DVDD 2.7

AVDD+DRVDD 4

DVDD 3.3

AVDD+DRVDD 1.2

DVDD 1

Fs = 48-kHz, PLL off, headphone drivers off

Additional power consumed when PLL is powered

AVDD+DRVDD LINE2LP/RP only routed to 3.3 Headphone amplifier single-ended headphones, DAC mA

DVDD 0

and PLL off, no signal applied

AVDD+DRVDD All supply voltages applied, all 0.1 Power down blocks programmed in lowest µ A

DVDD 0.5

power state

–77

0.014 –76

0.016 –73

0.022 –71

0.028

TLV320AIC32

0.3 ×

IOVDD

0.1 ×

IOVDD

(6) When IOVDD < 1.6V, minimum VIH is 1.1V.

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WCLK

SDOUT

BCLK

SDIN

(WS)

(DO-WS)

(DO-BCLK)

(DI)

WCLK

SDOUT

BCLK

SDIN

(WS)

(DO-BCLK)

(DI)

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

AUDIO DATA SERIAL INTERFACE TIMING DIAGRAM

Figure 2. I2S/LJF/RJF Timing in Master Mode

TIMING CHARACTERISTICS

(1)

All specifications typical at 25 ° C, DVDD = 1.8 V

PARAMETER UNIT

td(WS) ADWS/WCLK delay time 50 15 ns td(DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns t

(DO-BCLK)

BCLK to DOUT delay time 50 15 ns

ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t

Rise time 30 10 ns Fall time 30 10 ns

(1) All timing specifications are measured at characterization but not tested at final test.

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

Figure 3. DSP Timing in Master Mode

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WCLK

SDOUT

BCLK

SDIN

(DO-BCLK)

(WS)

(BCLK)

(WS)

(DO-WS)

(BCLK)

(DI)

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

TIMING CHARACTERISTICS

All specifications typical at 25 ° C, DVDD = 1.8 V

td(WS) ADWS/WCLK delay time 50 15 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t

(1) All timing specifications are measured at characterization but not tested at final test.

Rise time 30 10 ns Fall time 30 10 ns

(1)

PARAMETER UNIT

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

Figure 4. I2S/LJF/RJF Timing in Slave Mode

TIMING CHARACTERISTICS

All specifications typical at 25 ° C, DVDD = 1.8 V

tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 6 ns th(WS) ADWS/WCLK hold time 10 6 ns td(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only) TBD TBD ns t

(DO-BCLK) ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t

(1) All timing specifications are measured at characterization but not tested at final test.

BCLK to DOUT delay time 50 20 ns

Rise time 8 4 ns Fall time 8 4 ns

(1)

PARAMETER UNIT

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IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

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WCLK

SDOUT

BCLK

SDIN

(DO-BCLK)

(BCLK)

(DI)

(WS)

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

Figure 5. DSP Timing in Slave Mode

TIMING CHARACTERISTICS

(1)

All specifications typical at 25 ° C, DVDD = 1.8 V

PARAMETER UNIT

tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 8 ns th(WS) ADWS/WCLK hold time 10 8 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t

Rise time 8 4 ns Fall time 8 4 ns

(1) All timing specifications are measured at characterization but not tested at final test.

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

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-90

-80

-70

-60

-50

-40

-30

-20

0.015 0.02 0.025 0.03 0.035 0.04

Capless,VDD=3.6V

Capless,VDD=2.7V

AC-Coupled,VDD=3.6V

AC-Coupled,VDD=2.7V

TotalHarmonic Distortion -d

Power-W

AC-Coupled,

VDD=2.7V

Capless,

VDD=2.7V

Capless,

VDD=3.6V

-20

-30

-40

-50

-60

-70

-80

-90

TotalHarmonicDistortion

0.005 0.00

0.01 0.01 0.02

0.02

Power-W

AC-Coupled,

VDD=3.6V

-140.00

-120.00

-100.00

-80.00

-60.00

-40.00

-20.00

0.00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Frequency-kHz

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

TYPICAL CHARACTERISTICS

Figure 6. Headphone Power vs THD, 16 Ω Load Figure 7. Headphone Power vs THD, 32 Ω Load

Figure 8. DAC to Line Output FFT Plot

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TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

OVERVIEW

The TLV320AIC32 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications. Available in a 5 x 5 mm, 32-lead QFN, the product integrates a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable applications.

The TLV320AIC32 consists of the following blocks:

• Stereo audio multi-bit delta-sigma DAC (8 kHz – 96 kHz)

• Stereo audio multi-bit delta-sigma ADC (8 kHz – 96 kHz)

• Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, de-emphasis)

• Six audio inputs

• Four high-power audio output drivers (headphone/speaker drive capability)

• Three fully differential line output drivers

• Fully programmable PLL

• Headphone/headset jack detection with interrupt

HARDWARE RESET

The TLV320AIC32 requires a hardware reset after power-up for proper operation. After all power supplies are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not performed, the 'AIC32 may not respond properly to register reads/writes.

DIGITAL CONTROL SERIAL INTERFACE

The register map of the TLV320AIC32 actually consists of multiple pages of registers, with each page containing 128 registers. The register at address zero on each page is used as a page-control register, and writing to this register determines the active page for the device. All subsequent read/write operations will access the page that is active at the time, unless a register write is performed to change the active page. Only two pages of registers are implemented in this product, with the active page defaulting to page 0 upon device reset.

For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for addresses 1 to 127 will access registers in page 0. If registers on page 1 must be accessed, the user must write the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page

1. After this write, it is recommended the user also read back the page control register, to safely ensure the change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now access registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to register 0, the page control register, to change the active page back to page 0. After a recommended read of the page control register, all further read/write operations to addresses 1 to 127 will now access page 0 registers again.

I2C CONTROL INTERFACE

The TLV320AIC32 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pull-up resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the TLV320AIC32 can only act as a slave device.

An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receivers shift register.

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DA(6) DA(0) RA(7) RA(0) D(7) D(0)

Start

(M)

7-bit Device Address

(M)

Write

(M)

Slave

Ack

(S)

8-bit Register Address

(M)

Slave

Ack

(S)

8-bit Register Data

(M)

Stop

(M)

Slave

Ack

(S)

SDA

SCL

(M) => SDA Controlled by Master (S) => SDA Controlled by Slave

DA(6) DA(0) RA(7) RA(0)

Start

(M)

7-bit Device Address

(M)

Write

(M)

Slave

Ack

(S)

8-bit Register Address

(M)

Slave

Ack

(S)

SDA

SCL

DA(6) DA(0)

7-bit Device Address

(M)

Read

(M)

Slave

Ack

(S)

D(7) D(0)

8-bit Register Data

(S)

Stop

(M)

Master No Ack

(M)

Repeat

Start

(M)

(M) => SDA Controlled by Master (S) => SDA Controlled by Slave

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

OVERVIEW (continued)

The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start a communication. They do this by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device.

Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it will receive a not–acknowledge because no device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320AIC32 also responds to and acknowledges a General Call, which consists of the master issuing a command with a slave address byte of 00H.

In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Figure 17. I2C Write

Figure 18. I2C Read

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BCLK

WCLK

SDIN/

SDOUT

1 00 1 0

1/fs

LSBMSB

LeftChannel RightChannel

2 2

n−1

n−3

n−2

n−1

n−3

n−2

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

OVERVIEW (continued)

Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues a ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the next 8 clocks the data of the next incremental register.

DIGITAL AUDIO DATA SERIAL INTERFACE

Audio data is transferred between the host processor and the TLV320AIC32 via the digital audio data serial interface, or audio bus. The audio bus of the TLV320AIC32 can be configured for left or right justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors

The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in general the number of bit clocks per frame will be two times the data width. For example, if data width is chosen as 16-bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode will be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32 × Fs or 64 × Fs. In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame will not all be of equal period, due to the device not having a clean 40 × Fs or 48 × Fs clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (being 40 × Fs or 48 × Fs), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC32 further includes programmability to tri-state the DOUT line during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.

When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface will be put into a tri-state output condition.

RIGHT JUSTIFIED MODE

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

Figure 19. Right Justified Serial Bus Mode Operation

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n-1 n-2 n-3 n-1 n-2 n-3

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

OVERVIEW (continued)

LEFT JUSTIFIED MODE

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

Figure 20. Left Justified Serial Data Bus Mode Operation

I2S MODE

In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 21. I2S Serial Data Bus Mode Operation

DSP MODE

In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.

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BCLK

WCLK

SDIN/

SDOUT

n−2 n−3 1 0 n−1 n−2 1 0

1/fs

LSBMSB

Left Channel Right Channel

n−1

MSB LSB

n−4 2 n−3 2

MSBLSB

N-1 N-2 1 0 N-1 N-2 1 0

word

clock

bit clock

data

in/out

RightChannelData

LeftChannelData

N-1 N-2 1 0 N-1 N-2 1 0

word

clock

bit clock

data

in/out

DSP Mode

LeftJustifiedMode

offset

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

OVERVIEW (continued)

Figure 22. DSP Serial Bus Mode Operation

TDM DATA TRANSFER

Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data output driver (DOUT) can also be programmed to tri-state during all bit clocks except when valid data is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the bus except where it is expected based on the programmed offset.

Note that the location of the data when an offset is programmed is different, depending on what transfer mode is selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in the frame. This differs from left-justified mode, where the left and right channel data will always be a half-frame apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left and right channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in Figure 23 for the two cases.

Figure 23. DSP Mode and Left Justified Modes, Showing the

Effect of a Programmed Data Word Offset

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K*R/P

2/Q

PLL_CLKIN

CODEC

CODEC_CLKIN

PLL_OUT

K = J.D J = 1,2,3,…..,62,63 D= 0000,0001,….,9998,9999 R= 1,2,3,4,….,15,16 P= 1,2,….,7,8

Q=2,3,…..,16,17

MCLK BCLK

CLKDIV_IN PLL_IN

WCLK= Fsref/Ndac

ADC_FSDAC_FS

Ndac=1,1.5,2,…..,5.5,6

DAC DRA => Ndac = 0.5

CODEC_CLK=256*Fsref

CLKDIV_OUT

1/8

PLLDIV_OUT

CLKDIV_CLKIN

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

OVERVIEW (continued)

AUDIO DATA CONVERTERS

The TLV320AIC32 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at different sampling rates in various combinations, which are described further below.

The data converters are based on the concept of an Fsref rate that is used internal to the part, and it is related to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, Fsref will be either 44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and also to enable high quality playback of low sampling rate data, without high frequency audible noise being generated.

The sampling rate of the ADC and DAC can be set to Fsref/NDAC or 2 × Fsref/NDAC, with NDAC being 1, 1.5, 2,

2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6.

AUDIO CLOCK GENERATION

The audio converters in the TLV320AIC32 need an internal audio master clock at a frequency of 256 × Fsref, which can be obtained in a variety of manners from an external clock signal applied to the device.

A more detailed diagram of the audio clock section of the TLV320AIC32 is shown in Figure 24 .

Figure 24. Audio Clock Generation Processing

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OVERVIEW (continued)

The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK input can also be used to generate the internal audio master clock.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is disabled,

Fsref = CLKDIV_IN / (128 × Q)

Where Q = 2, 3, … , 17

CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7-D6.

NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and Fsref should fall within 39 kHz to 53 kHz.

When the PLL is enabled,

Fsref = (PLLCLK_IN × K × R) / (2048 × P), where

P = 1, 2, 3, … , 8 R = 1, 2, … , 16 K = J.D J = 1, 2, 3, … , 63 D = 0000, 0001, 0002, 0003, … , 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000 If K = 7.12, then J = 7, D = 1200 If K = 14.03, then J = 14, D = 0300 If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

2 MHz ≤ ( PLLCLK_IN / P ) ≤ 20 MHz 80 MHz ≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz 4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz 80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz 4 ≤ J ≤ 11 R = 1

Example:

MCLK = 12 MHz and Fsref = 44.1 kHz Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and Fsref = 48.0 kHz Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

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OVERVIEW (continued)

The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve Fsref = 44.1 kHz or 48 kHz.

Fsref = 44.1 kHz MCLK (MHz) P R J D ACHIEVED FSREF % ERROR

2.8224 1 1 32 0 44100.00 0.0000

5.6448 1 1 16 0 44100.00 0.0000

12.0 1 1 7 5264 44100.00 0.0000

13.0 1 1 6 9474 44099.71 0.0007

16.0 1 1 5 6448 44100.00 0.0000

19.2 1 1 4 7040 44100.00 0.0000

19.68 1 1 4 5893 44100.30 –0.0007

48.0 4 1 7 5264 44100.00 0.0000

Fsref = 48 kHz MCLK (MHz) P R J D ACHIEVED FSREF % ERROR

2.048 1 1 48 0 48000.00 0.0000

3.072 1 1 32 0 48000.00 0.0000

4.096 1 1 24 0 48000.00 0.0000

6.144 1 1 16 0 48000.00 0.0000

8.192 1 1 12 0 48000.00 0.0000

12.0 1 1 8 1920 48000.00 0.0000

13.0 1 1 7 5618 47999.71 0.0006

16.0 1 1 6 1440 48000.00 0.0000

19.2 1 1 5 1200 48000.00 0.0000

19.68 1 1 4 9951 47999.79 0.0004

48.0 4 1 8 1920 48000.00 0.0000

STEREO AUDIO ADC

The TLV320AIC32 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in operation, the device requires an audio master clock be provided and appropriate audio clock generation be setup within the part.

In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to support the case where only mono record capability is required. In addition, both channels can be fully powered or entirely powered down.

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 Fs to the final output sampling rate of Fs. The decimation filter provides a linear phase output response with a group delay of 17/Fs. The –3 dB bandwidth of the decimation filter extends to 0.45 Fs and scales with the sample rate (Fs). The filter has minimum 75dB attenuation over the stopband from 0.55 Fs to 64 Fs. Independent digital highpass filters are also included with each ADC channel, with a corner frequency that can be independently set to three different settings or can be disabled entirely.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC32 integrates a second order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides sufficient anti-aliasing filtering without requiring additional external components.

The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to

59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming (see registers Page-0/Reg-19 and 22). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and upon

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power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part after the ADC power down register is written to ensure the soft-stepping to mute has completed. When the ADC powerdown flag is no longer set, the audio master clock can be shut down.

AUTOMATIC GAIN CONTROL (AGC)

An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Note that completely independent AGC circuitry is included with each ADC channel with entirely independent control over the algorithm from one channel to the next. This is attractive in cases where two microphones are used in a system, but may have different placement in the end equipment and require different dynamic performance for optimal system operation.

Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TLV320AIC32 allows programming of eight different target gains, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Since the device reacts to the signal absolute average and not to peak levels, it is recommended that the larger gain be set with enough margin to avoid clipping at the occurrence of loud sounds.

Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 8 ms to 20 ms.

Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied in the range from 100 ms to 500 ms.

Noise gate threshold determines the level below which if the input speech average value falls, AGC considers it as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every FS and sets the noise threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This ensures that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is set, the status of gain applied by the AGC and the saturation flag should be ignored.

Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold. It can be programmed from 0 dB to +59.5 dB in steps of 0.5 dB.

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Decay Time

Input

Signal

Output

Signal

AGC

Gain

Attack

Time

TLV320AIC32

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Figure 25. Typical Operation of the AGC Algorithm During Speech Recording

Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the Fsref value programmed in the control registers. However, if the Fsref is set in the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different Fsref in practice, then the time constants would not be correct.

STEREO AUDIO DAC

The TLV320AIC32 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × Fsref and changing the oversampling ratio as the input sample rate is changed. For an Fsref of 48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for an Fsref rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.

The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is enabled in the DAC.

Allowed Q values = 4, 8, 9, 12, 16 Q values where equivalent Fsref can be achieved by turning on PLL Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16.0 and PLL enabled) Q = 10, 14 (set P = 5, 7 and K = 8.0 and PLL enabled)

DIGITAL AUDIO PROCESSING

The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing. The de-emphasis function is implemented by a programmable digital filter block with fully programmable coefficients (see Page-1/Reg-21-26 for left channel, Page-1/Reg-47-52 for right channel). If de-emphasis is not required in a particular application, this programmable filter block can be used for some other purpose. The de-emphasis filter transfer function is given by:

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H(z) +

N0) N1 z

32768* D1 z

N0) 2 N1 z

) N2 z

32768* 2 D1 z*1* D2 z

Ǔǒ

N3) 2 N4 z

) N5 z

32768* 2 D4 z*1* D5 z

LB1 LB2

RB1 RB2

TLV320AIC32

SLAS479B – AUGUST 2005 – REVISED AUGUST 2006

where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients that should be loaded to implement standard de-emphasis filters are given in Table 1 .

Table 1. De-Emphasis Coefficients for Common Audio Sampling Rates

SAMPLING FREQUENCY N0 N1 D1

32-kHz 16950 –1220 17037

44.1-kHz 15091 –2877 20555

(1)

48-kHz

(1) Default De-emphasis Coeffiicients

In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth order digital IIR filter with programmable coefficients (one set per channel). This filter is implemented as cascade of two biquad sections with frequency response given by:

The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structure of the filtering when configured for independent channel processing is shown below in Figure 26 , with LB1 corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly corresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5. The RB1 and RB2 filters refer to the first and second right-channel biquad filters, respectively.

14677 –3283 21374

(1)

(2)

Figure 26. Structure of the Digital Effects Processing for Independent Channel Processing

The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications. The default N and D coefficients in the part are given in Table 2 and implement a shelving filter with 0-dB gain from DC to approximately 150 Hz, at which point it rolls off to a 3-dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D coefficients are represented by 16-bit two’s complement numbers with values ranging from –32768 to 32767.

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LB1

RB2

Atten

LB2L

TOLEFT CHANNEL

TO RIGHT CHANNEL

TLV320AIC32

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Table 2. Default Digital Effects Processing Filter Coefficients,

When in Independent Channel Processing Configuration

Coefficients

N0 = N3 N1 = N4 N2 = N5 D1 = D4 D2=D5

27619 -27034 26461 32131 -31506

The digital processing also includes capability to implement 3-D processing algorithms by providing means to process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo output playback. The architecture of this processing mode, and the programmable filters available for use in the system, is shown in Figure 27 . Note that the programmable attenuation block provides a method of adjusting the level of 3-D effect introduced into the final stereo output. This combined with the fully programmable biquad filters in the system enables the user to fully optimize the audio effects for a particular system and provide extensive differentiation from other systems using the same device.

Figure 27. Architecture of the Digital Audio Processing When 3-D Effects are Enabled

It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified. While new coefficients are being written to the device over the control port, it is possible that a filter using partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of effects can be entirely avoided.

DIGITAL INTERPOLATION FILTER

The digital interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter stages. The filter provides a linear phase output with a group delay of 21/Fs. In addition, programmable digital interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at multiples of 8-kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and still audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation filter is designed to maintain at least 65-dB rejection of images that land below 7.455 Fs. In order to utilize the programmable interpolation capability, the Fsref should be programmed to a higher rate (restricted to be in the range of 39 kHz to 53 kHz when the PLL is in use), and the actual Fs is set using the NDAC divider. For example, if Fs = 8 kHz is required, then Fsref can be set to 48 kHz, and the DAC Fs set to Fsref/6. This ensures that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.

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DELTA-SIGMA AUDIO DAC

The stereo audio DAC incorporates a third order multi-bit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a 6-tap analog FIR filter followed by a continuous time RC filter. The analog FIR operates at a rate of 128 × Fsref (6.144 MHz when Fsref = 48 kHz,

5.6448 MHz when Fsref = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.

AUDIO DAC DIGITAL VOLUME CONTROL

The audio DAC includes a digital volume control block which implements a programmable digital gain. The volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for each channel. The volume level of both channels can also be changed simultaneously by the master volume control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by one step per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to one step per two input samples through a register bit.

Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the device provides a flag back to the host via a read-only register bit that alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is enabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When this flag is set, the internal soft-stepping process and power down sequence is complete, and the MCLK can then be stopped if desired.

The TLV320AIC32 also includes functionality to detect when the user switches on or off the de-emphasis or digital audio processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of the digital effects processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC. The circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired volume level. At power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.

ANALOG OUTPUT COMMON-MODE ADJUSTMENT

The output common-mode voltage and output range of the analog output are determined by an internal bandgap reference, in contrast to other codecs that may use a divided version of the supply. This scheme is used to reduce the coupling of noise that may be on the supply (such as 217-Hz noise in a GSM cellphone) into the audio signal path.

However, due to the possible wide variation in analog supply range (2.7 V – 3.6 V), an output common-mode voltage setting of 1.35 V, which would be used for a 2.7 V supply case, will be overly conservative if the supply is actually much larger, such as 3.3 V or 3.6 V. In order to optimize device operation, the TLV320AIC32 includes a programmable output common-mode level, which can be set by register programming to a level most appropriate to the actual supply range used by a particular customer. The output common-mode level can be varied among four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to

1.8 V (most appropriate for high supply ranges, near 3.6 V). Note that there is also some limitation on the range of DVDD voltage as well in determining which setting is most appropriate.

Table 3. Appropriate Settings

CM SETTING RECOMMENDED AVDD, DRVDD RECOMMENDED DVDD

1.35 2.7 V – 3.6 V 1.525 V – 1.95 V

1.50 3.0 V – 3.6 V 1.65 V – 1.95 V

1.65 V 3.3 V – 3.6 V 1.8 V – 1.95 V

1.8 V 3.6 V 1.95 V

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TEXAS INSTRUMENTS TLV320AIC32 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES DESCRIPTION

SIMPLIFIED BLOCK DIAGRAM

DEVICE INFORMATION

PIN ASSIGNMENTS

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

AUDIO DATA SERIAL INTERFACE TIMING DIAGRAM

TIMING CHARACTERISTICS

TIMING CHARACTERISTICS

TIMING CHARACTERISTICS

TIMING CHARACTERISTICS

TYPICAL CHARACTERISTICS

OVERVIEW

HARDWARE RESET

DIGITAL CONTROL SERIAL INTERFACE

I2C CONTROL INTERFACE

DIGITAL AUDIO DATA SERIAL INTERFACE

RIGHT JUSTIFIED MODE

LEFT JUSTIFIED MODE

I2S MODE

DSP MODE

TDM DATA TRANSFER

AUDIO DATA CONVERTERS

AUDIO CLOCK GENERATION

STEREO AUDIO ADC

AUTOMATIC GAIN CONTROL (AGC)

STEREO AUDIO DAC

DIGITAL AUDIO PROCESSING

DIGITAL INTERPOLATION FILTER

DELTA-SIGMA AUDIO DAC

AUDIO DAC DIGITAL VOLUME CONTROL

ANALOG OUTPUT COMMON-MODE ADJUSTMENT