TEXAS INSTRUMENTS TLV320AIC3105 Technical data

    

LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY

FEATURES APPLICATIONS

• Stereo Audio DAC

– 102-dBA Signal-to-Noise Ratio – 16/20/24/32-Bit Data – Supports Rates From 8 kHz to 96 kHz – 3D/Bass/Treble/EQ/De-Emphasis Effects – Flexible Power Saving Modes and

Performance are Available

• Stereo Audio ADC – 92-dBA Signal-to-Noise Ratio – Supports Rates From 8 kHz to 96 kHz – Digital Signal Processing and Noise Filtering

Available During Record

• Six Audio Input Pins – Six Stereo Single-Ended Inputs

• Six Audio Output Drivers – Stereo Fully Differential or Single-Ended

Headphone Drivers

– Fully Differential Stereo Line Outputs

• Low Power: 14-mW Stereo 48-kHz Playback

With 3.3-V Analog Supply

• Ultralow-Power Mode with Passive Analog

Bypass

• Programmable Input/Output Analog Gains

• Automatic Gain Control (AGC) for Record

• Programmable Microphone Bias Level

• Programmable PLL for Flexible Clock

Generation

• I2C Control Bus

• Audio Serial Data Bus Supports I2S,

Left/Right-Justified, DSP, and TDM Modes

• Extensive Modular Power Control

• Power Supplies:

– Analog: 2.7 V–3.6 V. – Digital Core: 1.525 V–1.95 V – Digital I/O: 1.1 V–3.6 V

• Package: 5-mm × 5-mm 32-Pin QFN

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

• Digital Cameras

• Smart Cellular Phones

DESCRIPTION

The TLV320AIC3105 is a low-power stereo audio codec with multiple single-ended inputs and and a stereo headphone amplifier. The output stages are programmable in single-ended or fully differential configurations. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 14 mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications.

The record path of the TLV320AIC3105 contains integrated microphone bias, digitally controlled stereo microphone preamplifier, and automatic gain control (AGC), with mix/mux capability among the multiple analog inputs. Programmable filters are available during record which can remove audible noise that can occur during optical zooming in digital cameras. The playback path includes mix/mux capability from the stereo DAC and selected inputs, through programmable volume controls, to the various outputs.

The TLV320AIC3105 contains four high-power output drivers as well as two fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16- Ω headphones using ac-coupling capacitors, or stereo 16- Ω headphones in a capacitorless output configuration.

The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1-kHz, and 48-kHz rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level microphone inputs. The TLV320AIC3105 provides an extremely high range of programmability for both attack (8–1,408 ms) and for decay (0.05–22.4 seconds). This extended AGC range allows the AGC to be tuned for many types of applications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

For battery saving applications where neither analog nor digital signal processing are required, the device can be put in a special analog signal passthrough mode. This mode significantly reduces power consumption, as most of the device is powered down during this passthrough operation.

The serial control bus supports the I2C protocol, while the serial audio data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.

The TLV320AIC3105 operates from an analog supply of 2.7 V–3.6 V, a digital core supply of 1.525 V–1.95 V, and a digital I/O supply of 1.1 V–3.6 V. The device is available in a 5-mm × 5-mm 32-pin QFN package.

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dio Serial Bus Interface

C Serial

Con

trol Bus

Bias/

ference

MICBIAS

SCL

SDA

RESET

Volta

ge Supplies

udio Clock

neration

MCLK

MIC2L/LINE2L

LINE2L

IC3L/LINE3L/MICDET

MIC1L/LINE1L

NE1L

0/+5

9.5dB

0.5d

teps

ADC

VCM

DAC

Volume

ntrol

Eff

ects

DIN

DOUT

BCLK

WCLK

DINL

DINR

DOUTL

DOUTR

MIC2R/LINE2R

INE2R

MIC3R/LINE3R

ADC

PGA

0/+59.5dB

0.5dB

Steps

MIC1R/LINE1R

INE1R

Volume

Con

trol

Effects

AGC

SW-D2

SW-D1

SW-D3

SW-D4

DVDD

DRVDD

DRVSS

DVSS IOVDD

AVSS_ADC

AVDD_DAC

AVSS_DAC

HPROUT

HPRCOM

HPLCOM

HPLOUT

LEF

T_LOP

LEFT

_LOM

LIN

E1L

LINE2L

-L0

-L1

SW-L2

RIGHT_LOP

RIG

HT_LOM

LINE1R

LINE2R

SW-R0

SW-R1

SW-R2

B0152-01

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

SIMPLIFIED BLOCK DIAGRAM

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P0048-02

SDADVDD

DRVDD

MCLK

1242233224215206197188

1427

1526

1625

MIC1L/LINE1L

BCLK

MIC1R/LINE1R

WCLK

MIC2L/LINE2L

DIN

MIC2R/LINE2R

DOUT

MIC3L/LINE3L/MICDET

DVSS

MICBIAS

IOVDD

MIC3R/LINE3R

SCL

RHBPACKAGE

(BOTTOMVIEW)

RESET

HPROUT

RIGHT_LOM

HPRCOM

RIGHT_LOP

DRVSS

LEFT_LOM

HPLCOM

LEFT_LOP

HPLOUT

AVSS2

DRVDD

AVDD

AVSS1

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

PACKAGING/ORDERING INFORMATION

PRODUCT PACKAGE DESIGNATOR TEMPERATURE NUMBER MEDIA, QUANTITY

TLV320AIC3105 QFN-32 RHB –40 ° C to 85 ° C

PACKAGE OPERATING ORDERING TRANSPORT

RANGE

TLV320AIC3105IRHBT Tape and reel, 250

TLV320AIC3105IRHBR Tape and reel, 2500

PIN ASSIGNMENTS

Connect device thermal pad to DRVSS.

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SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME QFN NO. I/O

AVDD 25 I Analog DAC voltage supply, 2.7 V–3.6 V AVSS1 17 I Analog ADC ground supply, 0 V AVSS2 26 I Analog DAC ground supply, 0 V BCLK 2 I/O Audio serial data bus bit clock input/output DIN 4 I Audio serial data bus data input DOUT 5 O Audio serial data bus data output DRVDD 18 O Analog ADC and output driver voltage supply, 2.7 V–3.6 V DRVDD 24 O Analog output driver voltage supply, 2.7 V–3.6 V DRVSS 21 O Analog output driver ground supply, 0 V DVDD 32 I Digital core voltage supply, 1.525 V–1.95 V DVSS 6 I/O Digital core / I/O ground supply, 0 V HPLCOM 20 O High-power output driver (left – or multifunctional) HPLOUT 19 O High-power output driver (left +) HPRCOM 22 O High-power output driver (right – or multifunctional) HPROUT 23 O High-power output driver (right +) IOVDD 7 I/O Digital I/O voltage supply, 1.1 V–3.6 V LEFT_LOM 28 O Left line output (–) LEFT_LOP 27 O Left line output (+) MCLK 1 I Master clock input MIC1L/LINE1L 10 I Left input 1 MIC1R/LINE1R 11 I Right input 1 MIC2L/LINE2L 12 I Left input 2 MIC2R/LINE2R 13 I Right input 2 MIC3L/LINE3L/MICDET 14 I Left input 3; can support microphone detection MIC3R/LINE3R 16 I Right input 3 MICBIAS 15 O Microphone bias voltage output RESET 31 Reset RIGHT_LOM 30 O Right line output (–) RIGHT_LOP 29 O Right line output (+) SCL 8 I/O I2C serial clock input SDA 9 I/O I2C serial data input/output WCLK 3 I/O Audio serial data bus word clock input/output

DESCRIPTION

TLV320AIC3105

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

AVDD to AVSS, DRVDD to DRVSS –0.3 to 3.9 V AVDD to DRVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V AVDD to DRVDD –0.1 to 0.1 V Digital input voltage to DVSS –0.3 to IOVDD + 0.3 V Analog input voltage to AVSS –0.3 to AVDD + 0.3 V Operating temperature range –40 to 85 ° C Storage temperature range –65 to 105 ° C

TJMax Junction temperature 105 ° C

Power dissipation (T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

(2) ESD complicance tested to EIA/JESD22-A114-B and passed.

PACKAGE THERMAL RATINGS

(1) R

Thermal impedance 44 ° C/W

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

PARAMETER TLV320AIC3105IRHB

(1)

(C/W) 8.43

θ JC

is the thermal resistance from junction to thermal pad. It is required to limit the power dissipation within the package to 500 mW in

θ JC

all cases, including temperatures below 25 ° C.

(1) (2)

VALUE UNIT

Max – TA)/ θ

SYSTEM THERMAL CHARACTERISTICS

(1)

Power Rating at 25 ° C, mW Power Rating, mW Derating Factor, ° C/W

High-K Board 500 500 at 80 ° C 48

Low-K Board 500 500 at 30 ° C 148

(1) It is required to limit the power dissipation within the package to 500 mW in all cases, including temperatures below 25 ° C. This data is

based on using a JEDEC standard four-layer 3-in. × 3-in. (7.62-mm × 7.62-mm) PCB with 2-oz. (0.071-mm thick) trace and copper pad that is soldered directly to the device.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

AVDD, DRVDD1/2

(1)

DVDD

(1)

IOVDD V

(1) Analog voltage values are with respect to AVSS1, AVSS2, DRVSS; digital voltage values are with respect to DVSS.

(1)

Analog supply voltage 2.7 3.3 3.6 V Digital core supply voltage 1.525 1.8 1.95 V Digital I/O supply voltage 1.1 1.8 3.6 V Analog full-scale 0-dB input voltage (DRVDD1 = 3.3 V) 0.63 V Stereo line output load resistance 10 k Ω Stereo headphone output load resistance 16 Ω Digital output load capacitance 10 pF Operating free-air temperature –40 85 ° C

RMS

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

ELECTRICAL CHARACTERISTICS

At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS= 48 kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUDIO ADC

Input signal level (0 dB) Single-ended input 0.707 V Signal-to-noise ratio

Dynamic range

THD Total harmonic distortion –89 –75 dB

PSRR Power-supply rejection ratio dB

Input channel separation 1-kHz, –2 dB full-scale signal, MIC1L to MIC1R –71 dB Gain error 0.82 dB ADC programmable gain

amplifier maximum gain ADC programmable gain

amplifier step size

Input resistance k Ω

Input capacitance MIC1/LINE1 inputs 10 pF Input level control minimum

attenuation setting Input level control maximum

attenuation setting Input level control attenuation

step size

ANALOG PASSTHROUGH MODE

Input-to-output switch resistance Ω

ADC DIGITAL DECIMATION FILTER, fS= 48 kHz

Filter gain from 0 to 0.39 f Filter gain at 0.4125 f Filter gain at 0.45 f Filter gain at 0.5 f Filter gain from 0.55 fSto 64 f Filter group delay 17/f

(1) (2)

fS= 48 ksps, 0 dB PGA gain, inputs ac-shorted to ground, A-weighted

fS= 48 ksps; 0-dB PGA gain –60-dB full-scale, 1-kHz input signal

fS= 48 ksps; 0-dB PGA gain; 1-kHz, –2-dB full-scale input signal

217-Hz signal applied to DRVDD 55 1-kHz signal applied to DRVDD 44

fS= 48 ksps, 0 dB PGA gain, –2 dB full-scale 1-kHz input signal

1-kHz input tone 59.5 dB

MIC1L/MIC1R inputs routed to single ADC Input multiplex attenuation = 0 dB

MIC1L/MIC1R inputs routed to single ADC Input multiplex attenuation = 12 dB

MIC2L/MIC2R inputs routed to single ADC Input multiplex attenuation = 0 dB

MIC2L/MIC2R inputs routed to single ADC Input multiplex attenuation = 12 dB

MIC3L/MIC3R inputs routed to single ADC Input multiplex attenuation = 0 dB

MIC3L/MIC3R inputs routed to single ADC Input multiplex attenuation = 12 dB

MIC1/LIN1 to LINEOUT, Rds ON 330 MIC2/LIN2 to LINEOUT, Rds ON 330

80 92 dB

± 0.1 dB

–0.25 dB

–17.5 dB

93 dB

0.5 dB

0 dB

12 dB

1.5 dB

–3 dB

–75 dB

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a

20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

RMS

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

ELECTRICAL CHARACTERISTICS (continued)

At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS= 48 kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

MICROPHONE BIAS

Programmable setting = 2 V 2

Bias voltage V

Current sourcing Programmable setting = 2.5 V 4 mA

AUDIO DAC – Differential Line Output, Load = 10 k Ω

Full-scale output voltage

SNR Signal-to-noise ratio 90 102 dB

Dynamic range 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz, 99 dB

THD Total harmonic distortion –95 –75 dB

PSRR Power-supply rejection ratio dB

DAC channel separation 0-dB full-scale input signal, between left and right LINEOUT 86 dB DAC interchannel gain mismatch 1-kHz input, 0-dB gain 0.1 dB

DAC gain error –0.2 dB

AUDIO DAC – Single-Ended Line Output, Load = 10 k Ω

Full-scale output voltage 0.707 V

SNR Signal-to-noise ratio 97 dB

THD Total harmonic distortion –84 dB

DAC gain error 0.55 dB

AUDIO DAC – Single-Ended Headphone Output, Load = 16 Ω

Full-scale output voltage 0.707 V

SNR Signal-to-noise ratio

Dynamic range 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz, 97 dB

THD Total harmonic distortion –71 –65 dB

PSRR Power-supply rejection ratio dB

DAC channel separation 89 dB

DAC gain error –0.85 dB

Programmable setting = 2.5 V 2.3 2.455 2.7 Programmable setting = DRVDD

0-dB full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V

No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz, A-weighted

–60-dB, 1-kHz full-scale input signal, output volume control = A-weighted

0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz

217-Hz signal applied to DRVDD, AVDD_DAC 78 1-kHz signal applied to DRVDD, AVDD_DAC 80

0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz

0-dB full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V

No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz, A-weighted

0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz

0-dB full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V

No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz, A-weighted

No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz, DAC 97 dB current-boost mode

–60-dB, 1-kHz full-scale input signal, output volume control = A-weighted

0-dB, 1-kHz full-scale input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS= 48 kHz

217-Hz signal applied to DRVDD, AVDD_DAC 43 1-kHz signal applied to DRVDD, AVDD_DAC 41 0-dB full-scale input signal, between left and right headphone

out 0-dB, 1-kHz full-scale input signal, output volume control = 0

dB, output common-mode setting = 1.35 V, fS= 48 kHz

DRVDD –

0.24

1.414 V 4 V

96 dB

RMS

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ELECTRICAL CHARACTERISTICS (continued)

At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS= 48 kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AUDIO DAC – Lineout and Headphone Out Drivers

First option 1.35

Output common mode V

Output volume control maximum setting

Output volume control step size 1 dB

DAC DIGITAL INTERPOLATION – FILTER fS= 48 kHz

Pass band 0 0.45 f Pass-band ripple ± 0.06 dB Transition band 0.45 f Stop band 0.55 f Stop-band attenuation 65 dB Group delay 21/f

STEREO HEADPHONE DRIVER – AC-COUPLED OUTPUT CONFIGURATION

0-dB full-scale output voltage 0.707 V

Programmable output common-mode voltage V (applicable to line outputs also)

Maximum programmable output level control gain

Programmable output level control gain step size

Maximum output power mW

Signal-to-noise ratio

(3)

Total harmonic distortion dB%

Channel separation 1-kHz, 0-dB input 90 dB Power supply rejection ratio 217 Hz, 100 mVpp on AVDD, DRVDD1/2 48 dB Mute attenuation 1-kHz output 107 dB

DIGITAL I/O

Input low level –0.3 0.3 IOVDD V

Input high level V

Output low level 0.1 IOVDD V Output high level V

Second optiin 1.5 Third option 1.65 Fourth option 1.8

9 dB

S S

(3)

0-dB gain to high-power outputs. Output common-mode voltage setting = 1.35 V

First option 1.35 Second option 1.5 Third option 1.65 Fourth option 1.8

9 dB

1 dB

RL= 32 Ω 15 RL= 16 Ω 30 A-weighted 94 dB

1-kHz output, PO= 5 mW, RL= 32 Ω

1-kHz output, PO= 10 mW, RL= 32 Ω

1-kHz output, PO= 10 mW, RL= 16 Ω

1-kHz output, PO= 20 mW, RL= 16 Ω

IOVDD > 1.6 V

0.7

IOVDD

–77

0.014

–76

0.016

–73

0.022

–71

0.028

IOVDD ≤ 1.6 V 1.1

0.8

IOVDD

TLV320AIC3105

0.55 f

7.5 f

RMS

(3) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to

20-kHz bandwidth.

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

ELECTRICAL CHARACTERISTICS (continued)

At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, fS= 48 kHz, 16-bit audio data (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT CONSUMPTION – DRVDD, IOVDD = AVDD_DAC = 3.3 V, DVDD = 1.8 V

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

+ I

DRVDD

AVDD_DAC

DVDD

RESET held low μ A

Mono ADC record, fS= 8 ksps, I2S slave, AGC off, no signal

Stereo ADC record, fS= 8 ksps, I2S slave, AGC off, no signal

Stereo ADC record, fS= 48 ksps, I2S slave, AGC off, no signal

Stereo DAC playback to Lineout, analog mixer bypassed, fS= 48 ksps, I2S slave

Stereo DAC playback to Lineout, fS= 48 ksps, I2S slave, no signal

Stereo DAC playback to stereo single-ended headphone, fS= 48 ksps, I2S slave, no signal

Stereo Linein to stereo Lineout, no signal

Extra power when PLL enabled

All blocks powered down. Headset detection enabled, headset not inserted.

0.1

0.2

2.15

0.48

4.1

0.62

4.31

2.45

3.5

2.3

4.9

2.3

6.7

2.3

3.11

1.4

0.9

μ A

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AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS

T0145-01

WCLK

BCLK

SDOUT

SDIN

t (DO-BCLK)

t (DO-WS)

t (WS)

t (DI)

All specifications at +25 ° C, DVDD = 1.8 V.

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

PARAMETER UNIT

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

td(WS) ADWS/WCLK delay time 50 15 ns td(DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t

Rise time 30 10 ns Fall time 30 10 ns

NOTE: All timing specifications are measured at characterization but not tested at final test.

Figure 1. I2S/LJF/RJF Timing in Master Mode

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T0146-01

WCLK

BCLK

SDOUT

SDIN

t (DO-BCLK)

t (WS)

t (DI)

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

All specifications at +25 ° C, DVDD = 1.8 V.

PARAMETER UNIT

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

td(WS) ADWS/WCLK delay time 50 15 ns td(DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t

Rise time 30 10 ns Fall time 30 10 ns

NOTE: All timing specifications are measured at characterization but not tested at final test.

Figure 2. DSP Timing in Master Mode

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T0145-02

WCLK

BCLK

SDOUT

SDIN

t (WS)

t (BCLK)

t (DO-BCLK)

t (DO-WS)

t (DI)

t (BCLK)

t (DI)

t (WS)

All specifications at +25 ° C, DVDD = 1.8 V.

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

PARAMETER UNIT

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 6 ns th(WS) ADWS/WCLK hold time 10 6 ns td(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only) 25 35 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t

Rise time 8 4 ns Fall time 8 4 ns

NOTE: All timing specifications are measured at characterization but not tested at final test.

Figure 3. I2S/LJF/RJF Timing in Slave Mode

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T0146-02

WCLK

BCLK

SDOUT

SDIN

t (WS)

t (BCLK)

t (WS)

t (BCLK)

t (DO-BCLK)

t (DI)

t (BCLK)

t (DI)

t (WS)

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

All specifications at +25 ° C, DVDD = 1.8 V.

PARAMETER UNIT

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 8 ns th(WS) ADWS/WCLK hold time 10 8 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns t t

r f

Rise time 8 4 ns Fall time 8 4 ns

NOTE: All timing specifications are measured at characterization but not tested at final test.

Figure 4. DSP Timing in Slave Mode

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TYPICAL CHARACTERISTICS

P − Headphone Power − mW

−80

−70

−60

−50

−40

−30

−20

−10

0 10 20 30 40 50 60 70 80 90 100

THD − Total Harmonic Distortion − dB

G001

Load = 16 Ω AC-Coupled

HPL

DRVDD = 2.7 V

HPR

DRVDD = 2.7 V

HPR

DRVDD = 3.3 V

HPL

DRVDD = 3.3 V

HPL

DRVDD = 3.6 V

HPR

DRVDD = 3.6 V

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0 2 4 6 8 10 12 14 16 18 20

Amplitude − dB

G003

Figure 5. Headphone Power vs THD, 16- Ω Load

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

Figure 6. DAC to Line Output FFT Plot

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f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0 2 4 6 8 10 12 14 16 18 20

Amplitude − dB

G004

0 10 20 30 40 50 60

PGA Gain Setting − dB

SNR − Signal-to-Noise Ratio − dB

G006

Input = −65 dBFS

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

TYPICAL CHARACTERISTICS (continued)

Figure 7. Line Input to ADC FFT Plot

Figure 8. ADC SNR vs PGA Gain Setting, –65-dBFS Input

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0.85

0.8

0.75

0.7

0.65

0.6

0.55

0.5

0.45

0.4 0 10 20 30 40 50 60 70

PGA Setting(dB)

GainError(dB)

Left ADC

Right ADC

G009

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD − Supply Voltage − V

MICBIAS Output Voltage − V

G007

MICBIAS = AVDD

MICBIAS = 2.5 V

MICBIAS = 2 V

TYPICAL CHARACTERISTICS (continued)

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

Figure 9. ADC Gain Error vs PGA Gain Setting

Figure 10. MICBIAS Output Voltage vs AVDD

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1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

−45 −35 −25 −15 −5 5 15 25 35 45 55 65 75 85 TA − Ambient Temperature − °C

MICBIAS Output Voltage − V

G008

MICBIAS = AVDD

MICBIAS = 2.5 V

MICBIAS = 2 V

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

TYPICAL CHARACTERISTICS (continued)

Figure 11. MICBIAS Output Voltage vs Ambient Temperature

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TLV320AIC3105

MIC2L/LINE2L

MIC1L/LINE1L

MIC1R/LINE1R

MIC3L/LINE3L/MICDET

MIC2R/LINE2R

0.1 Fm

MICBIAS

0.1 Fm

AVDD_DAC

AVSS_DAC

DRVDD

DVDD

DVSS

IOVDD

DRVDD

DRVSS

1.525V – 1.95V

1 Fm

0.1 Fm

1 Fm

LEFT_LOP

EFT_LOM

RIGHT_ROP

GHT_ROM

HPROUT

HPLCOM

RCOM

2kW

0.1 Fm

10 Fm

0.47 Fm

2kW

PLOUT

MIC3R/LINE3R

0.47 Fm

LINE_R

LINE_L

8 W

SCL

IOVDD

ESET

CLK

WCLK

AVSS_ADC

IOVDD

(1.1V – 3.3V)

AVDD

–

(2.7V 3.6V)

External AudioPower Amplifiers TPA2012D2(StereoClass-Din WCSP) TPA2010D1 (MonoClass-DinWCSP) TPA2005D1 (MonoClass-DinBGA, QFN, MSOP)

DSP

AppsProcessor

S0208-01

Tuner

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

TYPICAL CHARACTERISTICS (continued)

TYPICAL CIRCUIT CONFIGURATION

Figure 12. Typical Connections for Capless Headphone and External Speaker Amp

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TLV320AIC3105

MIC2L/LINE2L

MIC1L/LINE1L

MIC1R/LINE1R

MIC3L/LINE3L/MICDET

MIC2R/LINE2R

0.1 Fm

MICBIAS

0.1 Fm

AVDD_DAC

AVSS_DAC

DRVDD

DVDD

DVSS

IOVDD

DRVDD

DRVSS

1.525V – 1.95V

1 Fm

0.1 Fm

1 Fm

LEFT_LOP

LEFT_LOM

RIGHT_ROP

RIGHT_ROM

PROUT

HPLCOM

HPRCOM

2kW

0.1 Fm

10 Fm

0.47 Fm

2kW

HPLOUT

MIC3R/LINE3R

0.47 Fm

LINE_R

LINE_L

SDA

IOVDD

RESET

MCLK

BCLK

WCLK

DOUT

DIN

AVSS_ADC

IOVDD

(1.1V – 3.3V)

AVDD

–

(2.7V 3.6V)

DSP

AppsProcessor

Tuner

S0215-01

220 Fm

8 W

External Audio Power Amplifiers TPA2012D2 (Stereo Class-D in WCSP) TPA2010D1 (Mono Class-D in WCSP) TPA2005D1 (Mono Class-D in BGA, QFN, MSOP)

LINE_OUT_R–

LINE_OUT_R+

LINE_OUT_L–

LINE_OUT_L+

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

TYPICAL CHARACTERISTICS (continued)

Figure 13. Typical Connections for AC-Coupled Headphone Out With Separate Line Outputs and External

Speaker Amplifier

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

OVERVIEW

The TLV320AIC3105 is a highly flexible, low-power, stereo audio codec with extensive feature integration, intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications. Available in a 5-mm × 5-mm, 32-lead QFN, the product integrates a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered, portable applications.

The TLV320AIC3105 consists of the following blocks:

• Stereo audio multibit delta-sigma DAC (8 kHz–96 kHz)

• Stereo audio multibit delta-sigma ADC (8 kHz–96 kHz)

• Programmable digital audio effects processing (3-D, bass, treble, midrange, EQ, notch filter, de-emphasis)

• Six audio inputs

• Four high-power audio output drivers (headphone drive capability)

• Two fully differential line output drivers

• Fully programmable PLL

• Headphone/headset jack detection available as register status bit

HARDWARE RESET

The TLV320AIC3105 requires a hardware reset after power up for proper operation. After all power supplies are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not performed, the TLV320AIC3105 may not respond properly to register reads/writes.

DIGITAL CONTROL SERIAL INTERFACE

The register map of the TLV320AIC3105 actually consists of multiple pages of registers, with each page containing 128 registers. The register at address zero on each page is used as a page-control register, and writing to this register determines the active page for the device. All subsequent read/write operations access the page that is active at the time, unless a register write is performed to change the active page. Only two pages of registers are implemented in this product, with the active page defaulting to page 0 on device reset.

For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for addresses 1 to 127 access registers in page 0. If registers on page 1 must be accessed, the user must write the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page 1. After this write, it is recommended the user also read back the page control register, to safely ensure the change in page control has occurred properly. Future read/write operations to addresses 1 to 127 now access registers in page 1. When page-0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to register 0, the page control register, to change the active page back to page 0. After a recommended read of the page control register, all further read/write operations to addresses 1 to 127 access page-0 registers again.

I2C CONTROL INTERFACE

The TLV320AIC3105 supports the I2C protocol and responds to the I2C address of 001 1000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the TLV320AIC3105 can only act as a slave device.

An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receivers shift register.

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DA(6) DA(0) RA(7) RA(0) D(7) D(0)

T0147-01

SDA

SCL

(M) – SDA ControlledbyMaster (S) – SDA ControlledbySlave

Start

(M)

Write

(M)

Slave

Ack

(S)

Slave

Ack

(S)

Slave

Ack

(S)

Stop

(M)

7-BitDevice Address

(M)

8-BitRegister Address

(M)

8-BitRegisterdata

(M)

DA(6) DA(0) RA(7) RA(0)

SDA

SCL

DA(6) DA(0) D(7) D(0)

(M) – SDA ControlledbyMaster (S) – SDA ControlledbySlave

Start

(M)

Write

(M)

Slave

Ack

(S)

Slave

Ack (S)

Slave

Ack

(S)

Master No Ack

(M)

Stop

(M)

Repeat

Start

(M)

Read

(M)

7-BitDevice Address

(M)

8-BitRegister Address

(M)

8-BitRegisterData

(S)

7-BitDevice Address

(M)

T0148-01

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

OVERVIEW (continued)

The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start a communication. They do this by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device.

Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320AIC3105 also responds to and acknowledges a General Call, which consists of the master issuing a command with a slave address byte of 00H.

Figure 14. I2C Write

Figure 15. I2C Read

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

OVERVIEW (continued)

In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues an acknowledge, the slave takes over control of SDA bus and transmit for the next 8 clocks the data of the next incremental register.

I2C BUS DEBUG IN A GLITCHED SYSTEM

Occasionally, some systems may encounter noise or glitches on the I2C bus. In the unlikely event that this affects bus performance, then it can be useful to use the I2C Debug register. This feature terminates the I2C bus error allowing this I2C device and system to resume communications. The I2C bus error detector is enabled by default. The TLV320AIC3105 I2C error detector status can be read from page 0, register 107, bit D0. If desired, the detector can be disabled by writing to page 0, register 107, bit D2.

DIGITAL AUDIO DATA SERIAL INTERFACE

Audio data is transferred between the host processor and the TLV320AIC3105 via the digital audio data serial interface, or audio bus. The audio bus of the TLV320AIC3105 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors

The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32 × fSor 64 × fS. In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal period, due to the device not having a clean 40 × fSor 48 × fSclock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (being 40 × fSor 48 × fS), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3105 further includes programmability to place the DOUT line in the high-impedance state during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.

When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a high-impedance state.

RIGHT-JUSTIFIED MODE

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

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BCLK

WCLK

T0149-01

1/fs

LSBMSB

LeftChannel

RightChannel

2 2

SDIN/SDOUT

n–1 n–1n–2 n–2n–3

n–3

BCLK

WCLK

1 1

0 00

T0150-01

1/fs

LSBMSB

LeftChannel

RightChannel

2 2

SDIN/SDOUT

n–1 n–1 n–1n–2 n–2 n–2n–3 n–3

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

Figure 16. Right-Justified Serial Data Bus Mode Operation

OVERVIEW (continued)

LEFT-JUSTIFIED MODE

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

Figure 17. Left-Justified Serial Data Bus Mode Operation

I2S MODE

In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

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BCLK

WCLK

1 1

0 0

T0151-01

1/fs

LSBMSB

LeftChannel

RightChannel

2 2

SDIN/SDOUT

n–1 n–1 n–1

1ClockBeforeMSB

n–2 n–2

n–3 n–3

BCLK

WCLK

0 0

T0152-01

1/fs

LSB LSBLSB MSB MSB

LeftChannel

RightChannel

1 12 2

SDIN/SDOUT

n–1 n–1n–1n–2

n–3 n–3n–4

n–2

OVERVIEW (continued)

Figure 18. I2S Serial Data Bus Mode Operation

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

DSP MODE

In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 19. DSP Serial Data Bus Mode Operation

TDM DATA TRANSFER

Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks except when valid data is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the bus except where it is expected based on the programmed offset.

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N–1

1N–1N–2

N–2

Right-ChannelData

Left-ChannelData

••••

•••• ••

DSP Mode

Left-JustifiedMode

Offset

Offset Offset

T0153-01

WordClock

BitClock

DataIn/Out

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

OVERVIEW (continued)

Note that the location of the data when an offset is programmed is different, depending on what transfer mode is selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in the frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frame apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- and right-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in Figure 20 for the two cases.

Figure 20. DSP Mode and Left-Justified Modes, Showing the

Effect of a Programmed Data Word Offset

AUDIO DATA CONVERTERS

The TLV320AIC3105 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at different sampling rates in various combinations, which are described further below.

The data converters are based on the concept of an f the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f

44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and also to enable high quality playback of low sampling rate data, without high frequency audible noise being generated.

The sampling rate of the ADC and DAC can be set to f

2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3105, the NDAC and NADC should be set to the same value, as the device only supports a common sample rate for the ADC and DAC channels. Therefore, NCODEC = NDAC = NDAC, and this is programmed by setting the value of bits D7–D4 equal to the value of bits D3–D0 in page 0, register 2.

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rate that is used internal to the part, and it is related to

S(ref)

/NDAC or 2 × f

S(ref)

/NDAC, with NDAC being 1, 1.5, 2,

S(ref)

is either

S(ref)

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K*R/P

2/Q

PLL_CLKIN

CODEC

CODEC_CLKIN

PLL_OUT

Q=2,3,….., 16,17

MCLK BCLK

CLKDIV_IN PLL_IN

B0153-01

DAC f

ADC f

CODEC_CLK=256 f´

S(ref)

CLKDIV_OUT

1/8

PLLDIV_OUT

CLKDIV_CLKIN

K=J.D

J=1,2,3,....,62,63

D=0000,0001,....,9998,9999

R=1,2,3,4,....,15,16

P =1,2,....,7,8

WCLK= /NCODEC

CODEC =DAC = ADC

SetNCODEC=NADC=NDAC=1,1.5,2,....,5.5,6

DACDRA =>NDAC=0.5 ADCDRA =>NADC=0.5

f f f

S(ref)

S S S

TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

OVERVIEW (continued)

AUDIO CLOCK GENERATION

The audio converters in the TLV320AIC3105 need an internal audio master clock at a frequency of 256 × f which can be obtained in a variety of manners from an external clock signal applied to the device.

A more detailed diagram of the audio clock section of the TLV320AIC3105 is shown in Figure 21 .

S(ref)

Figure 21. Audio Clock Generation Processing

The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK input can also be used to generate the internal audio master clock.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is disabled,

S(ref)

= CLKDIV_IN/(128 × Q)

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

OVERVIEW (continued)

Where Q = 2, 3, … , 17

CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7–D6.

NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and f be the same as the NADC setting. The NDAC ratio is set on page 0, register 2. The NDAC is set equal to NADC by setting the value of bits D7–D4 equal to that of bits D3–D0.)

When the PLL is enabled,

= (PLLCLK_IN × K × R)/(2048 × P), where

S(ref)

P = 1, 2, 3, … , 8 R = 1, 2, … , 16 K = J.D J = 1, 2, 3, … , 63 D = 0000, 0001, 0002, 0003, … , 9998, 9999 PLLCLK_IN can be MCLK or BCLK, selected by page 0, register 102, bits D5–D4

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000 If K = 7.12, then J = 7, D = 1200 If K = 14.03, then J = 14, D = 0300 If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

2 MHz ≤ ( PLLCLK_IN/P ) ≤ 20 MHz 80 MHz ≤ (PLLCLK _IN × K × R/P ) ≤ 110 MHz 4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN/P ≤ 20 MHz 80 MHz ≤ PLLCLK _IN × K × R/P ≤ 110 MHz 4 ≤ J ≤ 11 R = 1

Example:

MCLK = 12 MHz and f Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve f = 44.1 kHz or 48 kHz.

= 44.1 kHz

S(ref)

MCLK (MHz) P R J D ACHIEVED f

2.8224 1 1 32 0 44,100 0

5.6448 1 1 16 0 44,100 0 12 1 1 7 5264 44,100 0 13 1 1 6 9474 44,099.71 –0.0007 16 1 1 5 6448 44,100 0

19.2 1 1 4 7040 44,100 0

19.68 1 1 4 5893 44,100.3 0.0007

should fall within 39 kHz to 53 kHz. (In the TLV320AIC3105, the NDAC setting must

S(ref)

= 44.1 kHz

S(ref)

= 48 kHz

S(ref)

% ERROR

S(ref)

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TLV320AIC3105

SLAS513A – FEBRUARY 2007 – REVISED JULY 2007

OVERVIEW (continued)

48 4 1 7 5264 44,100 0

= 48 kHz

S(ref)

MCLK (MHz) P R J D ACHIEVED f

2.048 1 1 48 0 48,000 0

3.072 1 1 32 0 48,000 0

4.096 1 1 24 0 48,000 0

6.144 1 1 16 0 48,000 0

8.192 1 1 12 0 48,000 0 12 1 1 8 1920 48,000 0 13 1 1 7 5618 47,999.71 –0.0006 16 1 1 6 1440 48,000 0

19.2 1 1 5 1200 48,000 0

19.68 1 1 4 9951 47,999.79 –0.0004 48 4 1 8 1920 48,000 0

S(ref)

STEREO AUDIO ADC

The TLV320AIC3105 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in operation, the device requires that an audio master clock be provided and appropriate audio clock generation be set up within the device.

In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to support the case where only mono record capability is required. In addition, both channels can be fully powered or entirely powered down.

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 fSto the final output sampling rate of fS. The decimation filter provides a linear phase output response with a group delay of 17/f scales with the sample rate (fS). The filter has minimum 75-dB attenuation over the stop band from 0.55 fSto 64 fS. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that can be independently set.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3105 integrates a second-order analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides sufficient antialiasing filtering without requiring additional external components.

The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to

59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC power-down flag is no longer set, the audio master clock can be shut down.

. The –3-dB bandwidth of the decimation filter extends to 0.45 fSand

% ERROR

STEREO AUDIO ADC HIGH-PASS FILTER

Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The TLV320AIC3105 has a programmable first-order high-pass filter which can be used for this purpose. The digital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0, N1, and D1. The transfer function of the digital high-pass filter is of the form:

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TEXAS INSTRUMENTS TLV320AIC3105 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES APPLICATIONS

DESCRIPTION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DESCRIPTION (CONTINUED)

PIN ASSIGNMENTS

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL RATINGS

SYSTEM THERMAL CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS

TYPICAL CHARACTERISTICS

TYPICAL CIRCUIT CONFIGURATION

OVERVIEW

HARDWARE RESET

DIGITAL CONTROL SERIAL INTERFACE

I2C CONTROL INTERFACE

I2C BUS DEBUG IN A GLITCHED SYSTEM

DIGITAL AUDIO DATA SERIAL INTERFACE

RIGHT-JUSTIFIED MODE

LEFT-JUSTIFIED MODE

I2S MODE

DSP MODE

TDM DATA TRANSFER

AUDIO DATA CONVERTERS

AUDIO CLOCK GENERATION

STEREO AUDIO ADC

STEREO AUDIO ADC HIGH-PASS FILTER