TEXAS INSTRUMENTS TLV320AIC28 Technical data

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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SLAS418A − FEBRUARY 2004 − REVISED SEPTEMBER 2004

 

FEATURES

D Stereo Audio DAC and Mono Audio ADC

Support Rates Up to 48 ksps

D High Quality 95-dB Stereo Audio Playback

Performance

D MIC Preamp and Hardware Automatic Gain

Control With Up to 59.5-dB Gain

D Stereo 16- Headphone Amplifier With

Capless Output Option

D 400-mW 8- Audio Power Amp With Direct

Battery Supply Connection

D 32- Differential Earpiece Driver D Integrated PLL For Flexible Audio Clock

Generation

D Low Power 19-mW Stereo Audio Playback at

48 ksps and 3.3-V Analog Supply level

D Programmable Digital Audio Bass/Treble/

EQ/De-Emphasis

D Auto-Detection of Jack Insertion, Headset

Type, and Button Press

D Direct Battery Measurement Accepts Up to

6-V Input

D On-Chip Temperature and Auxiliary Input

Measurement

D Programmable Measurement Converter

Resolution, Speed, Averaging, and Timing

D SPI and I

S Serial Interfaces

D Full Power-Down Control

APPLICATIONS

D Personal Digital Assistants D Cellular Smartphones D Digital Still Cameras D Digital Camcorders D MP3 Players

DESCRIPTION

The TLV320AIC28 is a low-power, high-performance audio codec with 16/20/24/32-bit 95-dB stereo playback, mono record functionality at up to 48 ksps. Two microphone inputs include independent programmable bias voltages, built-in pre-amps, and hardware automatic gain control, with single-ended or fully-differential signal input capabilities.

The stereo 16-Ω headphone drivers on the AIC28 support capless as well as ac-coupled output configurations. An 8-Ω BTL differential speaker driver provides up to 400 mW of power and 98-dB SNR, while a differential driver is also available for d r i v i n g a 3 2 - Ω speaker or telephone earpiece. A programmable digital audio effects processor enables bass, treble, midrange, or equalization playback processing. The digital audio data format is programmable to work with popular audio standard protocols (I left/right justified) in master or slave mode, and also includes an on-chip programmable PLL for flexible clock generation capability. Highly configurable software power control is provided, enabling 48 ksps stereo audio playback to 16-Ω headphones at 19 mW with a 3.3-V analog supply level.

The AIC28 offers a 12-bit measurement ADC and internal reference voltage. It includes an on-chip temperature sensor capable of reading 0.3°C resolution, as well as a battery measurement input capable of reading battery voltages up to 6 V, while operating at an analog supply as low as 3 V. The AIC28 is available in a 48-lead 7 x 7 mm QFN package.

S, DSP,

D 48-Pin QFN Package

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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US Patent No. 624639



TLV320AIC28

QFN-48

RGZ

−40°C to +85°C

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE

PIN ASSIGNMENTS

PACKAGE

DESIGNATOR

IOVDD

PWR_DN

RESET

GPIO2 GPIO1

AVDD2

AVSS2

AVDD1

NC NC NC NC

DVSS

48 47 46 45 44 43 42 41 40 39 38 37

1 2 3 4 5 6 7 8 9 10 11 12

14 15 16 17 18 19 20 21 22 23 24

OPERATING

TEMPERATURE RANGE

QFN PACKAGE

(TOP VIEW)

DVDD

BCLK

WCLK

SDIN

SDOUT

MCLK

SCLK

ORDERING NUMBER TRANSPORT MEDIA

TLV320AIC28IRGZ Rails, 52

TLV320AIC28IRGZR Tape and Reel, 2500

MISO

MOSISSDAV

DRVSS2

OUT8P

BVDD

OUT8N

DRVSS1

VGND

SPKFC

DRVDD

SPK2

SPK1

OUT32N

MIC_DETECT_IN

VREF

AVSS1

VBAT

AUX2

AUX1

CP_IN

CP_OUT

BUZZ_IN

MICIN_HED

MICIN_HND

MICBIAS_HED

MICBIAS_HND



QFN package

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Terminal Functions

PIN NAME DESCRIPTION PIN NAME DESCRIPTION

1 IOVDD IO Supply 25 MIC_DETECT_IN Microphone detect input 2 PWR_DN Hardware power down 26 OUT32N Receiver driver output 3 RESET Hardware reset 27 SPK1 Headset driver output/receiver driver output 4 GPIO2 General purpose IO 28 SPK2 Headset driver output 5 GPIO1 General purpose IO 29 DRVDD Headphone driver power supply 6 AVDD2 PLL analog power supply 30 SPKFC Driver feedback/ speaker detect input 7 AVSS2 Analog ground 31 VGND Virtual ground for audio output 8 AVDD1 Audio ADC, DAC, reference, SAR

ADC analog power supply

9 NC No connect 33 OUT8N Loudspeaker driver output 10 NC No connect 34 BVDD Battery power supply 11 NC No connect 35 OUT8P Loudspeaker driver output 12 NC No connect 36 DRVSS2 Driver ground 13 AVSS1 Analog ground 37 DAV Auxiliary data available output 14 VREF Reference voltage for SAR ADC 38 SS SPI Slave select input 15 VBAT Battery monitor input 39 MOSI SPI Serial data input 16 AUX2 Secondary auxiliary input 40 MISO SPI Serial data output 17 AUX1 First auxiliary input 41 SCLK SPI Serial clock input 18 BUZZ_IN Buzzer input 42 MCLK Master clock 19 CP_OUT Output to cell phone module 43 SDOUT Audio data output 20 CP_IN Input from cell phone module 44 SDIN Audio data input 21 MICIN_HND Handset microphone input 45 WCLK Audio word clock 22 MICBIAS_HND Handset microphone bias voltage 46 BCLK Audio bit clock 23 MICIN_HED Headset microphone input 47 DVDD Digital core supply 24 MICBIAS_HED Headset microphone bias voltage 48 DVSS Digital core and IO ground

32 DRVSS1 Driver ground

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

AVDD1/2 to AVSS1/2 −0.3 V to 3.9 V DRVDD to DRVSS1/2 −0.3 V to 3.9 V BVDD to DRVSS1/2 −0.3 V to 4.5 V IOVDD to DVSS −0.3 V to 3.9 V Digital input voltage to DVSS −0.3 V to IOVDD + 0.3 V Analog input (except VBAT) voltage to AVSS1/2 −0.3 V to AVDD + 0.3 V VBAT input voltage to AVSS1/2 −0.3 V to 6 V AVSS1/2 to DR VSS1/2 to DVSS −0.1 V to 0.1 V AVDD1/2 to DR VDD −0.1 V to 0.1 V Operating temperature range −40°C to 85°C Storage temperature range −65°C to 105°C Junction temperature (TJ Max) 105°C

Power dissipation (TJ Max − TA)/θ

Thermal impedance (with thermal pad soldered to board) 27°C/W

Lead temperature Infrared (15 sec) 240°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

If the AIC28 is used to drive high power levels to an 8-Ω load for extended intervals at an ambient temperature above 80°C, multiple vias should be used to electrically and thermally connect the thermal pad on the QFN package to an internal heat dissipating ground plane on the user’s PCB.

(1), (2)

UNITS



Voltage range

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ELECTRICAL CHARACTERISTICS

At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BATTERY MONITOR INPUTS

Input voltage range 0.5 6.0 V Input leakage current Battery conversion not selected ±1 µA

Variation across temperature after system

Accuracy

AUXILIARY A/D CONVERTER

Resolution Programmable: 8-, 10-,12-bits 8 12 Bits No missing codes 12-Bit resolution 11 Bits Integral nonlinearity −5 5 LSB Offset error −6 6 LSB Gain error −6 6 LSB Noise 50 µVrms VOLTAGE REFERENCE (VREF)

Voltage range

Reference drift Internal VREF = 1.25 V 50 ppm/°C Current drain

AUDIO CODEC ADC DECIMATION FILTER CHARACTERISTICS

Filter gain from 0 to 0.39 Fs ±0.1 dB Filter gain at 0.4125 Fs −0.25 dB Filter gain at 0.45 Fs −3.0 dB Filter gain at 0.5 Fs −17.5 dB Filter gain from 0.55 Fs to 64 Fs −75 dB Group delay 17/Fs sec

calibration at 4 V battery voltage and room temperature

VREF output programmed = 2.5 V 2.3 2.5 2.7 VREF output programmed = 1.25 V 1.25 External reference 1.1 2.5 V

Extra current drawn when the internal reference is turned on.

= 2.5 V , Fs (Audio) = 48 kHz, unless otherwise noted

ref

±15 mV

750 µA



PSRR

Input resistance

Voltage range

PSRR

Voltage range

PSRR

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ELECTRICAL CHARACTERISTICS (continued)

At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, Int. V noted (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

MICROPHONE INPUT TO ADC

Full-scale input voltage (0 dB) 0.707 Vrms Input common mode 1.5 V

SNR THD 0.63 Vrms input, 0-dB gain −81 −72 dB

Mute attenuation

Input capacitance 10 pF

HEADSET MICROPHONE BIAS

Voltage range

Sourcing current Voltage drop <25 mV 5 mA

HANDSET MICROPHONE BIAS

Sourcing current Voltage drop <25 mV 5 mA

DAC INTERPOLATION FILTER

Pass band 20 0.45Fs Hz Pass band ripple ±0.06 dB Transition band 0.45Fs 0.5501Fs Hz Stop band 0.5501Fs 7.455Fs Hz Stop band attenuation 65 dB Filter group delay 21/Fs Sec De-emphasis error ±0.1 dB

(1)

ADC PSRR measurement is calculated as:

MICIN_HED 1020 Hz sine wave input, Fs = 48 ksps

Measured as idle channel noise, 0 dB gain, A-weighted

217 Hz, 100 mV on AVDD1/2 1020 Hz, 1 0 0 m V o n AVDD1/2 Output code with 0.63 Vrms sine wave input at

1 kHz Only ADC on 15 50 kΩ ADC and Sidetone on 8 16 kΩ

Register 1DH/Page 2, D7−D8=00 3.3 Register 1DH/Page 2, D7−D8=01 2.5 Register 1DH/Page 2, D7−D8=1X 2 217 Hz, 100 mV on AVDD1/2 55 217 Hz, 100 mV on BVDD 74 1020 Hz, 1 0 0 m V o n AVDD1/2 55 1020 Hz, 100 mV on BVDD 74

(1)

= 2.5 V, Fs (Audio) = 48 kHz, unless otherwise

ref

80 90 dBA

55 dB 55 dB

0000H

PSRR + 20 log

where VSIG

VSIG

sup

ADCOUT

is the ac signal applied on AVDD1/2, which is 100 mVPP at 1020 Hz, and

sup

ADCOUT

Amplitude of Digital Output

Max Possible Digital Amplitude



PSRR PSRR

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ELECTRICAL CHARACTERISTICS (continued)

At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, V (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DAC HEADPHONE OUTPUT Load = 16 Ω (single-ended), 50 pF

Full-scale output voltage (0dB) 0.848 Vrms Output common mode 1.5 V SNR Measured as idle channel noise, A-weighted 85 95 dBA THD −1 dBFS Input, 0-dB gain −80 −60 dB

217 Hz, 100 mV on AVDD1/AVDD2/DRVDD

1020 Hz, 100 mV on

AVDD1/AVDD2/DRVDD Interchannel isolation Coupling from ADC to DAC 80 dB Mute attenuation 100 dB Maximum output power Per channel 44 mW Digital volume control −63.5 0 dB Digital volume control step size 0.5 dB Channel separation Between SPK1 and SPK2 −75 dB DAC SPEAKER OUTPUT Load = 8 Ω (differential), 50 pF Full-scale output voltage (0 dB) 1.838 Vrms Output common mode 1.75 V SNR Measured as idle channel noise, A-weighted 90 98 dBA THD −1 dBFS Input, 0-dB gain −74 −55 dB

217 Hz, 100 mV on AVDD1/2 70

217 Hz, 100 mV on BVDD 70

1020 Hz, 1 0 0 m V o n AVDD1/2 70

1020 Hz, 100 mV on BVDD 70 Interchannel isolation Coupling from ADC to DAC 90 dB Mute attenuation 100 dB Maximum output power 400 mW

CELLPHONE

MIC INPUT TO CPOUT

Full-scale input voltage (0 dB) 0.707 Vrms Input common mode 1.5 V Full-scale output voltage (0 dB) 0.707 Vrms Output common mode 1.5 V SNR Measured as idle channel noise, A-weighted 80 89 dBA THD 0 dBFS Input, 0-dB gain −73 −60 dB

PSRR

Interchannel isolation CP_IN to CP_OUT 75 dB Mute attenuation CP_OUT muted 100 dB

(1)

DAC PSRR measurement is calculated as:

1020-Hz Sine wave input on MICIN_HND,

load on CP_OUT = 10 kΩ, 50 pF

217 Hz, 100 mV on AVDD1/AVDD2/DRVDD 43

1020 Hz, 100 mV on

AVDD1/AVDD2/DRVDD

(1)

= 2.5 V , Fs (Audio) = 48 kHz, unless otherwise noted

ref

55 dB

VSIG

PSRR + 20 log

sup

SPK1ń2



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ELECTRICAL CHARACTERISTICS (continued)

At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, V (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CP_IN TO 32Ω RECEIVER (SPK1−OUT32N)

Full-scale input voltage (0 dB) 0.707 Vrms Input common mode 1.5 V Full-scale output voltage (0 dB) 1.697 Vrms Output common mode 1.5 V SNR Measured as idle channel noise, A-weighted 85 97 dBA THD 0 dBFs input, 0 dB gain −77 −60 dB

PSRR

Interchannel isolation MICIN to RECEIVER 75 dB Mute attenuation 100 dB Maximum output power 82 mW

DIGIT AL INPUT/OUTPUT

Logic family CMOS Logic level: V

Capacitive load 10 pF

1020-Hz Sine wave input on CP_IN, Load on SPK1−OUT32N = 32 Ω (differential), 50 pF

217 Hz, 100 mV on AVDD1/AVDD2/DRVDD 43 1020 Hz, 100 mV on

AVDD1/AVDD2/DRVDD

IIH = +5 µA 0.7IOVDD V IIL = +5 µA −0.3 0.3IOVDD V IOH = 2 TTL loads 0.8IOVDD V IOL = 2 TTL loads 0.1IOVDD V

= 2.5 V , Fs (Audio) = 48 kHz, unless otherwise noted

ref



IOVDD

Analog supply current – audio play back only

(1)

Analog supply current − mic record only

(1)

(2)

Total current

µA

Default current

(3)

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SLAS418A − FEBRUARY 2004 − REVISED SEPTEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

At +25°C, AVDD1, AVDD2, DRVDD, IOVDD = 3.3 V, BVDD = 3.9 V, DVDD = 1.8 V, V (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY REQUIREMENTS

Power supply voltage AVDD1, AVDD2 3 3.3 3.6 V DRVDD 3 3.3 3.6 V BVDD 3 4.2 V IOVDD Max MCLK = 100 MHz 2 3.6 V

Max MCLK = 50 MHz 1.1 3.6 V DVDD 1.65 1.8 1.95 V

IAVDD1 with loudspeaker output (no signal),

PLL off

IBVDD with loudspeaker output (no signal),

PLL off

IAVDD1 with headphone output (no signal),

VGND off, PLL off

IDRVDD with headphone output (no signal),

VGND off, PLL off Digital supply current – audio play back only IDVDD, PLL off 2.5 mA

IAVDD1, headset mic, PLL of f 5.2 mA Analog supply current − mic record only

Digital supply current – mic record only IDVDD, PLL off 1.4 mA Analog supply current IAVDD2, PLL on 1.3 mA Digital supply current IDVDD, PLL on 0.9 mA

Total current

(1)

Mic record currents measured with no load on MICBIAS.

(2)

Current measured with MICBIAS_HED voltage programmed to 2 V (Page 2, Register 1DH, BIt D8=1).

(3)

Default currents measured with device in default mode after reset.

IBVDD, headset mic, PLL off 270 µA

IAVDD1, handset mic, PLL of f 5.6 mA

Hardware power down 27

Only headset/button detection enabled 50

Only auto temperature measurement with

5.59 min delay

Headset/button detection and auto

temperature measurement with 5.59 min

delay

IAVDD1 + IAVDD2 66

IBVDD 9

= 2.5 V , Fs (Audio) = 48 kHz, unless otherwise noted

ref

3.1

7.5

2.5

3.5

µA

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FUNCTIONAL BLOCK DIAGRAM



SLAS418A − FEBRUARY 2004 − REVISED SEPTEMBER 2004

AVDD1 AVDD2 DRVDD BVDD DVDD IOVDD

VBAT

VREF

MICBIAS_HED

MIC_DETECT_IN

MICBIAS_HND

AUX1 AUX2

MICIN_HED MICIN_HND

CP_IN

BUZZ_IN

OUT8P OUT8N

OUT32N

SPK1

Temperature Measurement

2.0/2.5/3.3

To Detection

block

2.0/2.5

−1

Battery

Monitor

12 to −34.5dB (0.5dB steps)

0 to −45dB

(3dB steps)

12 to −34.5dB (0.5dB steps)

−1

0 to 59.5dB

(0.5dB steps)

Sidetone

SAR ADC

0 to 59.5dB

(0.5dB steps)

Internal

Reference

AGC

To ADC and DAC

Σ−∆

DAC

Σ−∆

ADC

PLL

Headset

detect and

Button detect

0 to −63.5dB

(0.5dB steps)

OSC

Vol Ctl

SPI

Interface

Digital

Audio

Processing

and Serial

Interface

SCLK SS

MOSI MISO

DAV

RESET

MCLK

PWR_DN

SDOUT

WCLK

SDIN

BCLK

SPK2

CP_OUT

SPKFC

VGND

1.5V

To Detection block

AVSS2 DRVSS1 DRVSS2 DVSSAVSS1

Σ−∆

DAC

0 to −63.5dB (0.5dB steps)

Vol Ctl

GPIO

Interface

GPIO1 GPIO2



PARAMETER

UNITS

SLAS418A − FEBRUARY 2004 − REVISED SEPTEMBER 2004

SPI TIMING DIAGRAM

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/SS

SPISELZ

S S

SCLK

S S

SPISELZ

SPICLK

MISO

S E

SPISELZ

MOSI

SPISELZ

Lead

sck

wsck

MSB IN BIT6...1 LSB IN

wsck

MSBOUT BIT6...1 LSBOUT

TYPICAL TIMING REQUIREMENTS

All specifications typical at 25°C, DVDD = 1.8 V(1)

t t t t t t t t t t t t

(1)

wsck Lead Lag td a dis su hi ho v r f

SCLK Pulse width 30 18 ns Enable Lead Time 18 15 ns Enable Lag Time 18 15 ns Sequential Transfer Delay 18 15 ns Slave MISO access time 18 15 ns Slave MISO disable time 18 15 ns MOSI data setup time 6 6 ns MOSI data hold time 6 6 ns MISO data hold time 4 4 ns MISO data valid time 25 13 ns Rise Time 6 4 ns Fall Time 6 4 ns

These parameters are based on characterization and are not tested in production.

Lag

IOVDD = 1.1 V IOVDD = 3.3 V

dis

MIN MAX MIN MAX



PARAMETER

(1)

UNITS

PARAMETER

(1)

UNITS

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AUDIO INTERFACE TIMING DIAGRAMS

WCLK

(WS)

BCLK

SDOUT

SDIN

(DO−WS)

Figure 1. DSP Timing in Master Mode

Typical Timing Requirements (see Figure 1)

td(WS) WCLK delay 30 15 ns td(DO−WS) WCLK to DOUT delay (for LJF mode) 30 15 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

Rise time 18 6 ns Fall time 18 6 ns

(DO−BCLK)

(DI)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

WCLK

BCLK

SDOUT

SDIN

(WS)

(DO−BCLK)

(DI)

Figure 2. DSP Timing in Master Mode

Typical Timing Requirements (see Figure 2)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

td(WS) WCLK delay 30 15 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

Rise time 18 6 ns Fall time 18 6 ns



PARAMETER

(1)

UNITS

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WCLK

(WS)

BCLK

SDOUT

SDIN

tL(BCLK)

tP(BCLK)

tH(BCLK)

Figure 3. I2S/LJF/RJF Timing in Slave Mode

Typical Timing Requirements (see Figure 3)

tH(BCLK) BCLK high period 40 35 ns tL(BCLK) BCLK low period 40 35 ns ts(WS) WCLK setup 6 6 ns th(WS) WCLK hold 6 6 ns td (DO−WS) WCLK to DOUT delay (for LJF mode) 30 18 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

Rise time 5 4 ns Fall time 5 4 ns

(WS)

(DO−WS)

(DO−BCLK)

(DI)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX



PARAMETER

(1)

UNITS

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WCLK

(WS)

(DO−BCLK)

(DI)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

BCLK

SDOUT

SDIN

tH(BCLK)

tP(BCLK)

(WS)

tL(BCLK)

(WS)

Figure 4. DSP Timing in Slave Mode

Typical Timing Requirements (see Figure 4)

tH(BCLK) BCLK high period 40 35 ns tL(BCLK) BCLK low period 40 35 ns tP(BCLK) BCLK period 80 80 ns ts(WS) WCLK setup 6 6 ns th(WS) WCLK hold 6 6 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

Rise time 5 4 ns Fall time 5 4 ns

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SLAS418A − FEBRUARY 2004 − REVISED SEPTEMBER 2004

TYPICAL CHARACTERISTICS

1.5 AV

/AV

DD2

= 3.3 V ,

LSB

0.5

−0.5

−1

TA = 25C,

IR = 2.5 V

DD1

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−1.5 0

500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 5. SAR INL (TA = 25C, Internal Reference = 2.5 V, 12 bit, AVDD1/AVDD2 = 3.3 V)

/AV

= 3.3 V ,

DD2

500 1000 1500 2000 2500 3000 3500 4000

CODE

LSB

−0.5

0.5

−1

DD1

TA = 25C, IR = 2.5 V

Figure 6. SAR DNL (TA = 25C, Internal Reference = 2.5 V, 12 bit, AVDD1/AVDD2 = 3.3 V)

2.4 AV

/AV

2.2

1.8

1.6

1.4

1.2

DD1

TA = 25C

DD2

= 3.3 V ,

Power − mW

0.8

0.6

0.4

0.2

10 20 30 40 50 60 70 80

Sampling Rate − Ksps

Figure 7. SAR ADC Power Consumption vs Speed (TA = 25C, External Reference, AUX Conversion,

AVDD1/AVDD2 = 3.3 V)

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−20

−40

−60

−80

−100

−120

−140

−160

500 1000 1500 2000 2500 3000 3500 4000

f − Frequency − Hz

/AV

DD1

TA = 25C,

DD2

= 3.3 V ,

Figure 8. ADC FFT Plot at 8 ksps (TA = 25C, −1 dB, 1 kHz input, AVDD1/AVDD2 = 3.3 V)

−20

−40

−60

−80

−100

−120

−140

−160

5000 10000 15000 20000

f − Frequency − Hz

/AV

DD1

TA = 25C,

DD2

= 3.3 V ,

Figure 9. ADC FFT Plot at 48 ksps (TA = 25C, −1 dB, 1 kHz input, AVDD1/AVDD2 = 3.3 V)

/AV

DD1

TA = 25C,

89.5

88.5

87.5

Dynamic Range − dB

86.5

8 18283848

= 3.3 V ,

DD2

Sampling Rate − Ksps

Figure 10. ADC Dynamic Range vs Sampling Rate (TA = 25C, AVDD1/AVDD2 = 3.3 V)

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−20

−40

−60

−80

−100

−120

−140

−160

/AV

DD2

= 3.3 V ,

f − Frequency − Hz

DD1

TA = 25C, RL = 16 

0 5000 10000 15000 20000

Figure 11. DAC FFT Plot (TA = 25C, −1 dB, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V, R

−77 AV

/AV

DD2

= 3.3 V ,

−78

−79

−80

−81

DD1

TA = 25C, RL = 16 

= 16 Ω)

−82

−83

THD − Total Hormonic Distortion − dB

−84

5 1015202530354045

Power − mW

Figure 12. THD vs Power on SPK1/2 (TA = 25C, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V, R

= 16 Ω)

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−60 AV

/AV

DD1

BVDD = 3.9 V TA = 25C,

−65

RL = 8 

−70

−75

−80

−85

THD − Total Hormonic Distortion − dB

−90

0 50 100 150 200 250 300 350 400

Figure 13. THD vs Power on Loudspeaker Driver (TA = 25C, 1 kHz Input, AVDD1/AVDD2/DRVDD = 3.3 V,

BVDD = 3.9 V, R

/DRDD = 3.3 V ,

DD2

Power − mW

= 8 Ω)

450

400

350

300

250

Max Power Output − mW

200

150

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 BVDD − V

Figure 14. Loudspeaker Driver Output Power vs BVDD (TA = 25C, 1 kHz Input,

AVDD1/AVDD2/DRVDD = 3.3 V, R

= 8 Ω, THD v −40 dB)

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OVERVIEW

The AIC28 is a highly integrated stereo audio DAC and mono audio ADC for portable computing, communication and entertainment applications. The AIC28 has a register-based architecture where all peripheral functions are controlled through the registers and on-board state machines.

The AIC28 consists of the following blocks:

D Audio Codec D Headset and Button Detection D Battery Monitors D Auxiliary Inputs D Temperature Monitor

Communication to the AIC28 is via a standard SPI serial interface. This interface requires that the Slave Select signal (SS) be driven low to communicate with the AIC28. Data is then shifted into or out of the AIC28 under control of the host microprocessor, which also provides the serial data clock.

Control of the AIC28 and its functions is accomplished by writing to different registers in the AIC28. A simple command protocol is used to address the 16-bit registers. Registers control the operation of the SAR ADC and audio codec.

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OPERATION—AUDIO CODEC

AUDIO ANALOG I/O

The AIC28 has stereo audio DAC and mono audio ADC. It has a wide range of analog interfaces to support different headsets and analog outputs. The AIC28 has features to interface output drivers (8-Ω, 16-Ω, 32-Ω) and Microphone PGA to Cell-phone. The AIC28 also has a virtual ground (VGND) output, which can be optionally used to connect to the ground terminal of a speaker of headphone to eliminate the ac-coupling capacitor needed at the speaker or headphone output. A special circuit has also been included in the AIC28 to insert a short keyclick sound into the stereo audio output, even when the audio DAC is powered down. They keyclick sound is used to provide feedback to the used when a particular button is pressed or item is selected. The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency, duration, and amplitude.

AUDIO DIGITAL I/O INTERFACE

Digital audio data samples can be transmitted between the AIC28 and the CPU via the serial bus (BCLK, WCLK, SDOUT, SDIN) that can be configured to transfer digital data in four different formats: Right justified (RJF), Left justified (LJF), I2S and DSP. The four modes are MSB first and operate with variable word length between 16/20/24/32 bits. The AIC28’s audio codec can operate in master or slave mode, depending on its register settings. The word-select signal (WCLK) and bit clock signal (BCLK) are configured as outputs when the bus is in master mode. They are configured as inputs when the bus is in slave mode. The WCLK is representative of the sampling rate of the audio ADC/DAC and is synchronized with SDOUT. Although the SDOUT signal can contain two channels of information (a left and right channel), the AIC28 sends the same ADC data in both channels.

D ADC/DAC Sampling Rate

The audio-control-1 register (Register 00H, Page 2) determines the sampling rates of DAC and ADC. The sampling frequency is scaled down from the reference rate (Fsref). The reference rate is usually either 44.1 kHz or 48 kHz which can be selectable using bit D13 of the register Audio Control 3 (06H/Page2). The ADC and DAC can operate with either common WCLK (equal sampling rates) or separate GPIO1 (For ADC) and WCLK (For DAC) for unequal sampling rates. When the audio codec is powered up, it is by default configured as an I2S slave with both the DAC and ADC operating at Fsref.

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D Word Select Signals

The word select signal (WCLK) indicates the channel being transmitted:

— WCLK = 0: left channel for I — WCLK = 1: right channel for I2S mode.

For other modes refer to the timing diagrams below.

D Bitclock (BCLK) Signal

In addition to being programmable as master or slave mode, the BCLK can also be configured in two transfer modes, 256-S transfer mode and continuous transfer mode, which are described below. These modes are set using bit D12 of control register 06H/page 2.

D 256-S Transfer Mode

In the 256-S mode, the BCLK rate always equals 256 times the WCLK frequency. In the 256-S mode, the combination of ADC/DAC sampling rate equal to Fsref (as selected by bit D5D0 of control register 00H/page

2) and left-justified mode is not supported. If IOVDD is equal to 1.1 V, then ADC/DAC sampling rate should be less than 39 kHz for all modes except the left justified mode where it should be less than 24 kHz.

D Continuous Transfer Mode

In the continuous transfer mode, the BCLK rate always equals two-word length times the frequency of WCLK.

S mode;

D Right Justified Mode

In right-justified mode, the LSB of left channel is valid on the rising edge of BCLK preceding, the falling edge on WCLK. Similarly the LSB of right channel is valid on the rising edge of BCLK preceding the rising edge of WCLK.

1/fs

WCLK

BCLK

Left Channel Right Channel

SDIN/

SDOUT

n n−1 1 00 n n−1 1 0

n−2 2 2n−2

LSBMSB

Figure 15. Timing Diagram for Right-Justified Mode

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D Left Justified Mode

In left-justified mode, the MSB of right channel is valid on the rising edge of BCLK, following the falling edge on WCLK. Similarly the MSB of left channel is valid on the rising edge of BCLK following the rising edge of WCLK.

WCLK

BCLK

Left Channel Right Channel

SDIN/

SDOUT

D I

S Mode

In I2S mode, the MSB of left channel is valid on the second rising edge of BCLK, after the falling edge on WCLK. Similarly the MSB of right channel is valid on the second rising edge of BCLK, after the rising edge of WCLK.

n n−1 1 0 n n−1 1 0

Figure 16. Timing Diagram for Left-Justified Mode

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1/fs

n n−1n−2 2 n−2 2

LSBMSB

1/fs

WCLK

BCLK

1 clock before MSB

Left Channel Right Channel

SDIN/

SDOUT

n n−1 1 0 n n−1 1 0

n−2 2 n−2 2

LSBMSB

Figure 17. Timing Diagram for Right-Justified Mode

D DSP Mode

In DSP mode, the falling edge of WCLK starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of BCLK.

1/fs

WCLK

BCLK

Left Channel Right Channel

SDIN/

SDOUT

n n−1 1 0 n n−1 1 0

n−2 2 n−2 2 n−2

LSBMSB

MSB LSB

n n−11 0

MSBLSB

Figure 18. Timing Diagram for DSP Mode

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AUDIO DATA CONVERTERS

The AIC28 includes a stereo audio DAC and a mono audio ADC. Both ADC and DAC can operate with a maximum sampling rate of 53 kHz and support all audio standard rates of 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz. By utilizing the flexible clock generation capability and internal programmable interpolation, a wide variety of sampling rates up to 53 kHz can be obtained from many possible MCLK inputs. In addition, the DAC and ADC can independently operate at different sampling rates as indicated in control register 00H/page 2.

When the ADC or DAC is operating, the AIC28 requires an applied audio MCLK input. The user should also set bit D13 of control register 06H/page 2 to indicate which Fsref rate is being used. If the codec ADC or DAC is powered up, then the auxiliary ADC uses MCLK and BCLK for its internal clocking, and the internal oscillator is powered down to save power.

Typical audio DACs can suffer from poor out-of-band noise performance when operated at low sampling rates, such as 8 kHz or 11.025 kHz. The AIC28 includes programmable interpolation circuitry to provide improved audio performance at such low sampling rates, by first upsampling low-rate data to a higher rate, filtering to reduce audible images, and then passing the data to the internal DAC, which is actually operating at the Fsref rate. This programmable interpolation is determined using bit D5D3 of control register 00H/page 2.

For example, if playback of 11.025 kHz data is required, the AIC28 can be configured such that Fsref = 44.1 kHz. Then using bit D5D3 of control register/page 2, the DAC sampling rate (Fs) can be set to Fsref/4, or FS = 11.025 kHz. In operation, the 11.025 kHz digital input data is received by the AIC28, upsampled to 44.1 kHz, and filtered for images. It is then provided to the audio DAC operating at 44.1 kHz for playback. In reality, the audio DAC further upsamples the 44.1 kHz data by a ratio of 128 x and performes extensive interpolation filtering and processing on this data before conversion to a stereo analog output signal.

Phase Locked Loop (PLL)

The AIC28 has an on chip PLL to generate the needed internal ADC and DAC operational clocks from a wide variety of clocks that may be available in the system. The PLL supports an MCLK varying from 2 MHz to 100 MHz and is register programmable to enable generation of required sampling rates with fine precision.

ADC and DAC sampling rates are given by

DAC_Fs +

Fsref

and

ADC_Fs +

Fsref

Where, Fsref must fall between 39 kHz and 53 kHz, and N1, N2=1, 1.5, 2, 3, 4, 5, 5.5, 6 are register programmable.

The PLL can be enabled or disabled using register programming.

D When PLL is disabled

Fsref +

Q = 2, 3…17

— Note: For ADC, with N2 = 1.5 or 5.5, odd values of Q are not allowed. — In this mode, the MCLK can operate up to 100 MHz, and Fsref should fall between 39 kHz

and 53 kHz.

MCLK

128 Q

D When PLL is enabled

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Fsref +

P = 1, 2, 3 … 8 K = J.D J = 1, 2, 3 ….64 D = 0, 1, 2 … 9999 P, J and D are register programmable.where J is integer part of K before the decimal point, and D is four-digit fractional part of K after the decimal point, including lagging zeros.

MCLK K

2048 P

Examples: If K = 8.5, then J = 8, D = 5000 If K = 7.12, then J = 7, D = 1200 If K = 7.012, then J = 7, D = 120

The PLL is programmed through Registers 1BH and 1CH of Page 2.

D When PLL is enabled and D = 0, the following conditions must be satisfied

2MHzv

80 MHz v

MCLK

MCLK K

4Ă v J vĂ55

v 20 MHz

v 110 MHz

D When PLL is enabled D ≠ 0, the following conditions must be satisfied

10 MHz v

MCLK

v 20 MHz

80 MHz v

MCLK K

v 110 MHz

4Ă v J vĂ11

Example 1:

For MCLK = 12 MHz and Fsref = 44.1 kHz P = 1, K = 7.5264 J = 7, D = 5264

Example 2:

For MCLK = 12 MHz and Fsref = 48 kHz P = 1, K = 8.192 J = 8, D = 1920

MONO AUDIO ADC

Analog Front End

The analog front end of the audio ADC consists of an analog MUX and a programmable gain amplifier (PGA). The MUX can connect either of the Headset Input (MICIN_HED), Handset Input (MICIN_HND), AUX1 and AUX2 signal through the PGA to the ADC for audio recording. The Cell-phone Input (CP_IN) can also be connected to ADC through a PGA at the same time. This enables recording of conversation during a cell-phone call. The AIC28 also has an option of choosing MICIN_HED/MICIN_HND and AUX1/AUX2 as differential input pair. The AIC28 also includes two microphone bias circuits which can source up to 5 mA of current, and are programmable to a 2 V, 2.5 V or 3.3 V level for Headset and 2 V or 3.3 V level for handset.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog anti-aliasing filtering are very relaxed. The AIC28 integrates a second order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.

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The PGA, for microphone and AUX Inputs, allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping. This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. Upon reset, the PGA gain defaults to a mute condition, and upon power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag (D0 control register 04H/Page 2) is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can be disabled by programming D15=1 in register 1DH of Page 2. When soft stepping is enabled and ADC power down register is written, MCLK should be running to ensure that soft-stepping to mute has completed. MCLK can be shut down once Mic PGA power down flag is set.

The PGA, for Cell phone Input (CP_IN) allows gain control from –34.5 dB to 12 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft−stepping. This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. Upon reset, the PGA gain defaults to a mute condition, and upon power down, the PGA soft-steps the volume to mute before shutting down. A read−only flag (D7 control register 1FH/Page 2) is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can be disabled by the programming D12=1 in register 1DH of Page 2. When soft-stepping is enabled and ADC power down register is written, MCLK should be running to ensure that soft-stepping to mute has completed. MCLK can be shut down once Cell PGA power down flag is set.

Delta-Sigma ADC

The analog-to-digital converter has a delta-sigma modulator with a 128 times oversampling ratio. The ADC can support maximum output rate of 53 kHz.

Decimation Filter

The audio ADC includes an integrated digital decimation filter that removes high frequency content and downsamples the audio data from an initial sampling rate of 128 times Fs to the final output sampling rate of Fs. The decimation filter provides a linear phase output response with a group delay of 17/Fs. The –3 dB bandwidth of the decimation filter extends to 0.45 Fs and scales with the sample rate (Fs).

Programmable High Pass Filter

The ADC channel has a programmable high-pass filter whose cutoff frequency can be programmed through control register. By default the high pass filter is off. The high-pass filter is a first order IIR filter. This filter can be used to remove the DC component of the input signal and offset of the ADC channel.

Automatic Gain Control (AGC)

The AIC28 includes Automatic gain control (AGC) for Microphone Inputs (MICIN_HED or MICIN_HND) and Cell-phone input (CP_IN). AGC can be used to maintain nominally constant output signal amplitude when recording speech signals. This circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and max PGA applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The AIC28 allows programming of eight different target gains, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Since the AIC28 reacts to the signal absolute average and not to peak levels, it is recommended that the target gain be set with enough margin to avoid clipping at the occurrence of loud sounds.

Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 8 ms to 20 ms.

Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied in the range from 100 ms to 500 ms.

Noise threshold is the minimum amplitude for the input signal that the AGC considers as a valid signal. If the average amplitude of the incoming signal falls below this value, the AGC considers it as silence and brings down the gain to 0 dB in steps of 0.5 dB for every FS. This will also set the noise threshold flag. The gain stays at

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0 dB until the average amplitude of the input signal rises above the noise threshold value. This ensures that noise does not get amplified in the absence of a valid input speech signal. Noise threshold level is programmable from −30dB to −90 dB for microphone input, and from −30 dB to −60 dB for cell-phone input. When AGC Noise Threshold is set to −70 dB, −80 dB, or −90 dB, the microphone input Max PGA applicable setting must be greater than or equal to 11.5 dB, 21.5 dB, or 31.5 dB respectively. This operation includes debounce and hysteresis to avoid the AGC gain from cycling between high gain and 0 dB when the signal amplitude is near the noise threshold level. When the noise threshold flag is set, status of gain applied by AGC and saturation flag should be ignored.

Maximum input gain applicable allows user to restrict maximum gain applied by the AGC. This can be used for limiting PGA gain in situations where environment noise is greater than programmed noise threshold. Microphone input Max PGA can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB. Cell-phone input Max PGA can be programmed from −34.5 dB to −0.5 dB in steps of 0.5 dB, as well as +12 dB.

See Table 1 for various AGC programming options. AGC can be used only if microphone input or Cell-phone input is routed to the ADC channel. When both microphone input and Cell-phone input are connected to the ADC, AGC is automatically disabled.

Input

Signal

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Output

Signal

AGC Gain

Decay Time

Figure 19. AGC Characteristics

Target Gain

Attack

Time

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Table 1. AGC Settings

MIC HEADSET INPUT MIC HANDSET INPUT CELL-PHONE INPUT

BIT

AGC enable D0 01H D0 1EH D0 24H Target gain D7−D5 01H D7−D5 1EH D7−D5 24H Time constants (attack and decay time) D4−D1 01H D4−D1 1EH D4−D1 24H Noise threshold D13−D11 24H D13−D11 24H D13−D11 24H Noise threshold flag D11 04H D11 04H D14 24H Hysteresis D10−D9 1DH D10−D9 1DH D10−D9 24H Debounce time (normal to silence mode) D8−D6 26H D8−D6 26H D8−D6 27H Debounce time (silence to normal mode) D5−D3 26H D5−D3 26H D5−D3 27H Max PGA applicable D15−D9 26H D15−D9 26H D15−D9 27H Gain applied by AGC D15−D8 01H D15−D8 1EH D14−D8 1FH Saturation flag D0 04H D0 04H D7 1FH Clip stepping disable D3 06H D3 06H D8 24H

NOTE:All settings shown in Table 1 are located in Page 2 of control registers.

CONTROL

BIT

Stereo Audio DAC

CONTROL REGISTER

BIT

CONTROL

Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sample rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 x Fsref and changing the oversampling ratio as the input sample rate is changed. For Fsref of 48 kHz, the digital delta−sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within the delta-sigma modulator stays within the frequency band below 20 kHz at all sample rates. Similarly, for Fsref rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.

Digital Audio Processing

The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, or speaker equalization. The de-emphasis function is only available for sample rates of 32 kHz, 44.1 kHz, and 48 kHz. The transfer function consists of a pole with time constant of 50ms and a zero with time constant of 15ms. Frequency response plots are given in the Audio Codec Filter Frequency Responses section of this data sheet.

The DAC digital effects processing block consists of a fourth order digital IIR filter with programmable coefficients (one set per channel). The filter is implemented as cascade of two biquad sections with frequency response given by:

N0 ) 2 N1 z*1) N2 z

32768 * 2 D1 z*1* D2 z

N3 ) 2 N4 z*1) N5 z

Ǔǒ

32768 * 2 D4 z*1* D5 z

The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications. The default N and D coefficients in the part are given by:

N0 = N3 = 27619 N1 = N4 = −27034 N2 = N5 = 26461 D1 = D4 = 32131 D2 = D5 = −31506

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TEXAS INSTRUMENTS TLV320AIC28 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual