TEXAS INSTRUMENTS TLV320AIC26 Technical data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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        



FEATURES

D Low Power High Quality Audio Codec D Stereo Audio DAC and Mono Audio ADC

Support Rates up to 48 ksps

D High Quality 97-dBA Stereo Audio Playback

Performance

D Low Power: 11-mW Stereo Audio Playback at

48 ksps

D On-Chip 325-mW, 8- Speaker Driver D Stereo Headphone Amplifier With Capless

Output Option

D Microphone Preamp and Hardware Automatic

Gain Control

D Integrated PLL for Flexible Audio Clock

Generation

D Programmable Digital Audio

Bass/Treble/EQ/De-Emphasis

D Direct Battery Measurement Accepts up to

6-V Input

D On-Chip Temperature Measurement D SPI and I

S Serial Interface

D Full Power-Down Control D 32-Pin 5y5 mm QFN Package

DESCRIPTION

The TLV320AIC26 is a high-performance audio codec with 16/20/24/32-bit 97-dBA stereo playback, mono record functionality at up to 4 8 k s p s . A microphone input includes built-in preamp and hardware automatic gain control, with single-ended or fully-differential input capability.

The audio output drivers on the ’AIC26 are highly flexible, having software-programmable low or high-power drive modes to optimize system power dissipation. The outputs can be configured to supply up to 325 mW into a bridge terminated 8-Ω load, can support stereo 16-Ω headphone amplifiers in ac-coupled or capless output configurations, and can supply a stereo line-level output

A programmable digital audio effects processor enables bass, treble, midrange, or equalization playback processing. The digital audio data format is programmable to work with popular audio standard protocols (I Left/Right Justified) in master or slave mode, and also includes an on-chip programmable PLL for flexible clock generation capability. Highly configurable software power control is provided, enabling stereo audio playback at 48 ksps at 11 mW with a 3.3-V analog supply level.

S, DSP,

APPLICATIONS

D Cellular and Smart Phones D MP3 Players D Digital Still Cameras D Digital Video Camcorders

semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI is a trademark of Motorola. I2S is a trademark of Phillips Electronics.

  !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/ #".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&' '&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/

The ’AIC26 offers a 12-bit measurement ADC and internal reference voltage, as well as two battery measurement inputs capable of reading battery voltages up to 6 V, while operating at an analog supply as low as 2.7 V. It includes an on-chip temperature sensor capable of reading 0.3°C resolution. The ’AIC26 is available in a 32 lead QFN.



TLV320AIC26

QFN-32

RHB

−40°C to 85°C

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PRODUCT PACKAGE

PIN ASSIGNMENTS

PACKAGE

DESIGNATOR

DVSS

IOVDD

MCLK

SCLK

MISO MOSI

DAV

DVDD

32 26

1 2 3 4 5 6 7 8

910

OPERATING

TEMPERATURE RANGE

BCLK

DOUT

DIN

PWD/ADWS

LRCK

RESET16HPR

31 30 29 28 27

AIC26

11 12 13 14 15

ORDERING NUMBER

TLV320AIC26IRHB Tubes, 74

TLV320AIC26IRHBR Tape and Reel, 3000

QFN(TOP VIEW)

DRVDD

VGND

DRVSS

HPL

AVDD

TRANSPORT MEDIA,

QUANTITY

AUX

MICIN

VBAT2

VBAT1

AVSS

VREF

MICBIAS

Terminal Functions

QFN

NAME DESCRIPTION

29 DIN Audio data input 13 VBAT1 Battery monitor input 30 DOUT Audio data output 14 VREF Reference voltage I/O 31 BCLK Audio bit−clock 15 AVSS Analog ground 32 DVDD Digital core supply 16 NC No connect

1 DVSS Digital core and IO ground 17 NC No connect 2 IOVDD IO supply 18 NC No connect 3 MCLK Master clock 19 NC No connect 4 SCLK SPI serial clock input 20 AVDD Analog power supply 5 MISO SPI serial data output 21 HPL Left channel audio output 6 MOSI SPI serial data input 22 DRVSS Speaker ground 7 SS SPI slave select input 23 VGND V irtual ground for audio output 8 DAV Auxiliary data available output 24 DRVDD Speaker /PLL supply

9 MICBIAS Microphone bias voltage 25 HPR Right channel audio output 10 MICIN Microphone input 26 RESET Device reset 11 AUX Auxiliary input 27 LRCK Audio DAC word-clock 12 VBAT2 Battery monitor input 28 PWD/ADWS Hardware powerdown/ADC word clock

QFN

NAME DESCRIPTION

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QFN package

Lead temperature

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SLAS412− DECEMBER 2003

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

AVDD to AVSS −0.3 V to 3.9 V DRVDD to DRVSS −0.3 V to 3.9 V IOVDD to DVSS −0.3 V to 3.9 V DVDD to DVSS −0.3 V to 2.5 V AVDD to DRVDD −0.1 V to 0.1 V AVSS to DR VSS to DVSS −0.1 V to 0.1 V Analog inputs (except VBAT1 and VBAT2) to AVSS −0.3 V to AVDD + 0.3 V VBAT1 / VBAT2 to AVSS −0.3 V to 6 V Digital input voltage to DVSS −0.3 V to IOVDD + 0.3 V Operating temperature range −40°C to 85°C Storage temperature range −65°C to 105°C Junction temperature (TJ Max) 105°C

Power dissipation (TJ Max − TA)/θ

Thermal impedance 123°C/W

Soldering vapor phase (60 sec) 215°C Infrared (15 sec) 220°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

If the ’AIC26 is used to drive high power levels to an 8-Ω load for extended intervals at ambient temperatures above 70°C, multiple vias should be used to electrically and thermally connect the thermal pad on the QFN package to an internal heat-dissipating ground plane on the user’s PCB.

(1)(2)

UNITS



Voltage

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ELECTRICAL CHARACTERISTICS

At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. V

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BATTERY MONITOR INPUTS

Input voltage range 0.5 6.0 V Input leakage current Battery conversion not selected ±1 µA

AUXILIARY A/D CONVERTER

Resolution Programmable: 8-, 10-,12-bits 12 Bits No missing codes 12-bit resolution 11 Bits Integral nonlinearity −5 5 LSB Offset error −6 6 LSB

Gain error Noise 53 µVrms

AUDIO CODEC ADC DECIMATION FILTER Sample rate of 48 ksps

Filter gain from 0 to 0.39Fs ±0.1 dB Filter gain at 0.4125Fs −0.25 dB Filter gain at 0.45Fs −3 dB Filter gain at 0.5Fs −17.5 dB Filter gain from 0.55Fs to 64Fs −75 dB Filter group delay 17/Fs sec MICROPHONE INPUT TO ADC 1 kHz sine wave input, Fs = 48 ksps Full scale input voltage (0 dB) By design, not tested in production 0.707 Vrms Input common mode By design, not tested in production 1.35 V

SNR THD 0.63-Vrms input, 0-dB gain −89 −72 dB

PSRR 1 kHz, 100 mVpp on AVDD. Mute attenuation Output code with 0.63-Vrms sine wave input at

Input resistance 20 kΩ Input capacitance 10 pF

MICROPHONE BIAS

Voltage D4 = 0 control register 05H/Page2 2.5 V

Sourcing current 4.7 mA

(1)

ADC PSRR measurement is calculated as:

VSIG

PSRR + 20 log

ADCOUT

sup

Calculated with effect of internal reference variation removed.

Measured as idle channel noise, 0-dB gain, A-weighted

1 kHz

D4 = 1 control register 05H/Page2 2.0 V

= 2.5 V , Fs (Audio) = 48 kHz, unless otherwise noted

ref

−6 6 LSB

80 92 dBA

(1)

57 dB

0000H



THD

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ELECTRICAL CHARACTERISTICS

At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. V

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DAC INTERPOLATION FILTER

Pass band 20 0.45 Fs Hz Pass band ripple ±0.06 dB Transition band 0.45 Fs 0.5501 Fs Hz Stop band 0.5501 Fs 7.455 Fs Hz Stop band attenuation 65 dB Filter group delay 21/Fs sec De−emphasis error ±0.1 dB

DAC LINE OUTPUT

Full scale output voltage (0 dB) By design, D10−D9 = 00 in control register

Output common mode By design, D10−D9 = 00 in control register

SNR Measured as idle channel noise, A-weighted 85 97 dBA THD 0-dB FS input, 0-dB gain −95 dB PSRR 1 kHz, 100 mVpp on AVDD

Interchannel isolation Coupling from ADC to DAC 84 dB DAC HEADPHONE OUTPUT 1-kHz sine wave input, 48 ksps, output drivers

Full scale output voltage (0 dB) By design, D10−D9 = 00 in control register

SNR Measured as idle channel noise, A-weighted 85 97 dBA THD −1 dB FS input, 0-dB gain −91 −55 dB PSRR 1 kHz, 100 mVpp on AVDD

Interchannel isolation Coupling from ADC to DAC 85 dB Mute attenuation 121 dB Maximum output power D10−D9 = 00 in control register 06H/Page2 30 mW Digital volume control gain −63.5 0 dB Digital volume control step size 0.5 dB Channel separation Between HPL and HPR 80 dB DAC SPEAKER OUTPUT Output driver in high power mode,

Output power 0 dB input to DAC 325 mW SNR Measured as idle channel noise, A-weighted 102 dBA THD −1 dB FS input, 0-dB gain −86 dB

(1)

DAC PSRR measurement is calculated as:

1-kHz sine wave input, 48 ksps, output drivers in low power mode, load = 10 kΩ, 10 pF

06H/Page2 corresponding to 2-VPP output swing

down

in high power mode, load = 16 Ω, 10 pF

06H/Page2 corresponding to 2-VPP output swing

down

load = 8 Ω,, connected between HPR and HPL pins. D10−D9 = 10 in control register 06H/Page2 corresponding to 2.402-VPP output swing

−6 dB FS input, 0-dB gain −88 dB

= 2.5 V , Fs (Audio) = 48 kHz, unless otherwise noted (continued)

ref

0.707 Vrms

1.35 V

(2)

VGND powered

(1)

VGND powered

56 dB

0.707 Vrms

54 dB

PSRR + 20 log

VSIG V

HPRńL

sup



Voltage range

48 ksps, output drivers in low

Stereo audio playback

power mode, VGND off, PLL

Microphone record

48 ksps, no playback, PLL off

PLL

when PLL is enabled.

VGND

when VGND is powered.

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ELECTRICAL CHARACTERISTICS

At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. V

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VOLTAGE REFERENCE

VREF output programmed as 2.5 V 2.3 2.5 2.7 VREF output programmed as 1.25 V 1.15 1.25 1.35

Voltage range External VREF. By design, not tested in

production.

Reference drift Internal VREF = 1.25 V 29 ppm/°C Current drain

DIGITAL INPUT / OUTPUT

Internal clock frequency 8.8 MHz Logic family

Logic level: V

Capacitive load 10 pF

POWER SUPPLY REQUIREMENTS

Power supply voltage

(2)

AVDD DRVDD IOVDD 1.1 3.6 V DVDD 1.525 1.95 V

Stereo audio playback

Microphone record

PLL

VGND

Hardware power down All currents 2 µA

(1)

Internal oscillator is designed to give nominally 8-MHz clock frequency. However, due to process variations, this frequency can vary from device

to device. All calculations for delays and wait times in the data sheet assume an 8-MHz oscillator clock.

(2)

It is recommended that AVDD and DRVDD be set to the same voltage for the best performance. It is also recommended that these supplies be

separated on the user’s PCB.

(2)

(1)

Extra current drawn when the internal reference is turned on.

IIH = +5 µA 0.7xIOVDD V IIL = +5 µA −0.3 0.3xIOVDD V IOH = 2 TTL loads 0.8xIOVDD V IOL = 2 TTL loads 0.1xIOVDD V

IAVDD IDRVDD IDVDD IAVDD 2.9 IDRVDD IDVDD IAVDD IDRVDD IDVDD IAVDD IDRVDD IDVDD

= 2.5 V , Fs (Audio) = 48 kHz, unless otherwise noted (continued)

ref

1.2 2.55 V

650 µA

CMOS

2.7 3.6 V

2.2

power mode, VGND off, PLL off

48 ksps, no playback, PLL off

Additional power consumed

2.4

1.4

0.1

1.3

0.9

0.3

0.9 0

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FUNCTIONAL BLOCK DIAGRAM

DRVDD DRVSS AVDD AVSS DVDD DVSS IOVDD

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HPR

HPL

VGND

MICBIAS

MICIN

AUX

VBAT1

VBAT2

Headphone Driver

Battery

Monitor

Battery

Monitor

Temperature

Measurement

DAC CM

2.5 V/2 V

Σ Σ

Analog Volume

Control −34.5 to

(0.5 dB Steps)

∑−∆

DAC

∑−∆

DAC

12 dB

0 to 59.5 dB

∑−∆

ADC

AGC

SAR ADC

0 to −63.5 dB

(0.5 dB Steps)

Vol Ctl

Sidetone

−48 to 0 dB

1.5 dB Steps

PLL

Digital

Audio

Processing

and

Serial

Interface

SPI

Interface

MCLK

PWD DOUT LRCK DIN BCLK

RESET

SCLKSSSCLK

MOSI MISO DAV

/ADWS

VREF

Internal 2.5 V/

1.25 V

Reference

OSC

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PARAMETER

UNITS

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SPI TIMING DIAGRAM

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sck

wsck

MSB OUT BIT . . . 1 LSB OUT

wsck

MSB OUT BIT . . . 1 LSB OUT

SCLK

MISO

MOSI

Lead

TYPICAL TIMING REQUIREMENTS

All specifications at 25°C, DVDD = 1.8 V

wsck

Lead

Lag

dis

(1)

These parameters are based on characterization and are not tested in production.

SCLK pulse width 27 18 ns Enable lead time 18 15 ns Enable lag time 18 15 ns Sequential transfer delay 18 15 ns Slave MISO access time 18 15 ns Slave MISO disable time 18 15 ns MOSI data setup time 6 6 ns MOSI data hold time 6 6 ns MISO data hold time 4 4 ns MISO data valid time 22 13 ns Rise time 6 4 ns Fall time 6 4 ns

(1)

Lag

dis

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

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PARAMETER

UNITS

PARAMETER

UNITS

AUDIO INTERFACE TIMING DIAGRAMS

LRCK/ADWS

td (WS)

BCLK

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td (DO−WS)

DOUT

DIN

td (DO−BCLK)

ts (DI) th (DI)

Figure 1. I2S/LJF/RJF Timing in Master Mode

TYPICAL TIMING REQUIREMENTS (FIGURE 1)

All specifications at 25°C, DVDD = 1.8 V

td (WS) ADWS/LRCK delay 25 15 ns td (DO−WS) ADWS to DOUT delay (for LJF mode) 25 15 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

LRCK/ADWS

BCLK

Rise time 10 6 ns Fall time 10 6 ns

(1)

td (WS)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

td (WS)

td (DO−BCLK)

DOUT

ts (DI)

DIN

th (DI)

Figure 2. DSP Timing in Master Mode

TYPICAL TIMING REQUIREMENTS (FIGURE 2)

All specifications at 25°C, DVDD = 1.8 V

td (WS) ADWS/LRCK delay 25 15 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

Rise time 10 6 ns Fall time 10 6 ns

(1)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

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PARAMETER

UNITS

SLAS412− DECEMBER 2003

LRCK/ADWS

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BCLK

DOUT

DIN

tL(BCLK)

th (WS)

tH(BCLK)

td(DO−WS)

tP(BCLK)

tS (WS)

td(DO−BCLK)

ts (DI)

th (DI)

Figure 3. I2S/LJF/RJF Timing in Slave Mode

TYPICAL TIMING REQUIREMENTS (FIGURE 3)

All specifications at 25°C, DVDD = 1.8 V

tH (BCLK) BCLK high period 35 35 ns tL (BCLK) BCLK low period 35 35 ns ts(WS) ADWS/LRCK setup 6 6 ns th(WS) ADWS/LRCK hold 6 6 ns td (DO−WS) ADWS to DOUT delay (for LJF mode) 25 18 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

Rise time 5 4 ns Fall time 5 4 ns

(1)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

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PARAMETER

UNITS

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LRCK/ADWS

BCLK

DOUT

DIN

tH(BCLK)

th(WS)

tL(BCLK)

tP(BCLK)

tS (WS)

th(WS)

td(DO−BCLK)

ts (DI)

tS (WS)

th (DI)

Figure 4. DSP Timing in Slave Mode

TYPICAL TIMING REQUIREMENTS (FIGURE 4)

All specifications at 25°C, DVDD = 1.8 V

tH (BCLK) BCLK high period 35 35 ns tL (BCLK) BCLK low period 35 35 ns ts(WS) ADWS/LRCK setup 6 6 ns th(WS) ADWS/LRCK hold 6 6 ns td (DO−BCLK) BCLK to DOUT delay 25 15 ns ts(DI) DIN setup 6 6 ns th(DI) DIN hold 6 6 ns t

(1)

These parameters are based on characterization and are not tested in production.

Rise time 5 4 ns Fall time 5 4 ns

(1)

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

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1.5 1

0.5

LSB

−0.5

−1

−1.5

Figure 5. SAR INL (TA = 25°C, Internal Ref = 2.5 V, 12 bit, AVDD = 3.3 V)

0.5

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TYPICAL CHARACTERISTICS

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

LSB

−0.5

−1 0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 6. SAR DNL (TA = 25°C, Internal Ref = 2.5 V, AVDD = 3.3 V)

−20

−40

−60

−80

−100

−120

−140

−160 0 500 1000 1500 2000 2500 3000 3500 4000

Figure 7. ADC FFT Plot at 8 ksps (TA = 25°C, −1 dB, 1 kHz Input, AVDD = 3.3 V)

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−20

−40

−60

−80

−100

−120

−140

−160 0 5000 10000 15000 20000

Figure 8. ADC FFT Plot at 48 ksps (TA = 25°C, −1 dB, 1 kHz Input, AVDD = 3.3 V)

89.5

88.5

87.5

Dynamic Range − dB

86.5

818283848

Sampling Rate − ksps

Figure 9. ADC Dynamic Range vs Sampling Speed (TA = 25°C, AVDD = 3.3 V)

−20

−40

−60

−80

−100

−120

−140

−160 0 5000 10000 15000 20000

Figure 10. DAC FFT Plot (TA = 25°C, 48 ksps, 0 dB, 1 kHz Input, AVDD = 3.3 V, RL = 10 kΩ)

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SLAS412− DECEMBER 2003

−10

−30

−50

−70

−90

−110

−130

−150

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0 5000 10000 15000 20000

Figure 11. DAC FFT Plot (TA = 25°C, 48 ksps, −1 dB, 1 kHz Input, AVDD = DRVDD = 3.3 V, DVDD = 1.8 V,

RL = 16 Ω)

−88

−90

−92

THD − Total Harmonic Distortion − dB

−94 515 2535

Output Power − mW

Figure 12. High Power Output Driver THD vs Output Power

=25°C, AVDD, DRVDD = 3.3 V, RL = 16 )



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OVERVIEW

The ’AIC26 is a highly integrated stereo audio codec for portable computing, communication, and entertainment applications. The ’AIC26 has a register-based architecture where all functions are controlled through the registers and onboard state machines.

The ’AIC26 consists of the following blocks (refer to the block diagram):

D Audio Codec D Battery Monitors D Auxiliary Inputs D Temperature Monitor

Audio data is transferred between the host DSP/µP via a standard 4-wire interface and supports a variety of modes (i.e.,

S, DSP, etc).

Control of the ’AIC26 and its functions is accomplished by writing to different registers in the ’AIC26. A simple command protocol is used to address the 16-bit registers. Registers control the operation of the A/D converter and audio codec. The control and auxiliary functions are accessed via a SPI bus.

A typical application of the ’AIC26 is shown in Figure 13.

8 

Speaker

V1: Main Battery V2: Secondary Battery C1: 1 µF − 10 µF (Optional) C2, C3, C4: 0.1 F R1, R2: 200 − 300 

V1 V2

Auxiliary Input

Audio

2.2 k

AUX

MICBIAS MICIN

HPR HPL

VGND

VBAT1

VBAT2 VREF

MCLK

ADWS/

PWDZ DOUT

LRCK

DIN

BCLK

DAV

MISO MOSI

SCLK

Figure 13. Typical Circuit Configuration

12S Interface

Master Clock Input ADC Word Select Serial Output to CPU/DSP DAC Word Select Serial Input From CPU/DSP

Serial Clock Input

SPI Interface

Auxiliary Data Interrupt Request to CPU

Serial Output to SPI Master Serial Input From SPI Master

SPI Slave Select Input SPI Serial Clock Input



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OPERATION−AUDIO CODEC

Audio Analog I/O

The ’AIC26 has one mono audio input (MICIN) typically used for microphone recording, and an auxiliary input (AUX) that can be used as a second microphone or line input. The dual audio output drivers have programmable power level and can be configured to drive up to 325 mW into an 8-Ω speaker, or to drive 16-Ω stereo headphones at over 30-mW per channel, or to provide a stereo line-level output. The power level of the output drivers is controlled using bit D12 in control register REG−05H/Page2. The ’AIC26 also has a virtual ground (VGND) output driver, which can optionally be used to connect the return terminal of headphones, to eliminate the ac-coupling capacitors needed at the headphone output. The VGND amplifier is controlled by bit D8 of REG−05H/Page2. A special circuit has also been included in the ’AIC26 to insert a short keyclick sound into the stereo audio output, even when the audio DAC is powered down. The keyclick sound is used to provide feedback to the user when a particular button is pressed or item is selected. The specific sound of the keyclick can be adjusted by varying several register bits that control its frequency, duration, and amplitude.

Audio Digital Interface

Digital audio data samples are transmitted between the ’AIC26 and the audio processor via the serial bus (BCLK, ADWS, DOUT, LRCK, DIN) that can be configured to transfer digital data in four different formats: right justified, left justified, I and DSP. The four modes are MSB-first and operate with variable word length of 16, 20, 24, or 32 bits. The digital audio serial bus of the ’AIC26 can operate in master or slave mode, depending on its register settings. The word-select signals (ADWS, LRCK) and bit clock signal (BCLK) are configured as outputs when the bus is in master mode. They are configured as inputs when the bus is in slave mode. The ADWS is representative of the sampling rate of the audio ADC and is synchronized with DOUT. The LRCK is representative of the audio DAC sampling rate and is synchronized with DIN. Although the DOUT signal can contain two channels of information (a left and right channel), the ’AIC26 sends the same ADC data in both channels.

D ADC/DAC SAMPLING RATE

The Audio Control 1 register (Register 00H, Page2) determines the sampling rates of the audio DAC and ADC, which are scaled down from a reference rate (Fsref). The ADC and DAC can operate with either a common LRCK (equal sampling rates) or separate ADWS and LRCK (unequal sampling rates). When the audio codec is powered up, it is configured by default as an I

S slave with both the DAC and ADC operating at Fsref.

D WORD SELECT SIGNALS

The word select signal (LRCK, ADWS) indicates the channel being transmitted:

− LRCK/ADWS = 0: left channel for I

− LRCK/ADWS = 1: right channel for I

For other modes see the timing diagrams below.

Bitclock (BCLK) Signal

In addition to flexibility as master or slave mode, the BCLK can also be configured in two transfer modes—256−S and Continuous Transfer Modes. These modes are set using bit D12/REG−06h/Page2.

S mode

D 256−S TRANSFER MODE

In the 256−S mode, the BCLK rate always equals 256 times the maximum of the LRCK and ADWS frequencies. In the 256−S mode, the combination of ADC/DAC sampling rate equal to Fsref (as selected by bit D5−D0/REG−00h/Page2) and left−justified mode is not supported.

D CONTINUOUS TRANSFER MODE

In the continuous transfer mode, the BCLK rate always equals two times the word length of the maximum of the LRCK and ADWS frequencies.

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D RIGHT-JUSTIFIED MODE

In right-justified mode, the LSB of the left channel is valid on the rising edge of the BCLK preceding the falling edge of ADWS or LRCK. Similarly, the LSB of the right channel is valid on the rising edge of the BCLK preceding the rising edge of ADWS or LRCK.

1/fs

ADWS/

LRCK

BCLK

Left Channel Right Channel

DIN/

DOUT

n n−1 1 00 n n−1 1 0

n−2 2 2n−2

LSBMSB

Figure 14. Timing Diagram for Right-Justified Mode

D LEFT-JUSTIFIED MODE

In left−justified mode, the MSB of the right channel is valid on the rising edge of the BCLK, following the falling edge of ADWS or LRCK. Similarly the MSB of the left channel is valid on the rising edge of the BCLK following the rising edge of ADWS or LRCK.

1/fs

ADWS/

LRCK

BCLK

Left Channel Right Channel

DIN/

DOUT

n n−1 1 0 n n−1 1 0

LSBMSB

Figure 15. Timing Diagram for Left-Justified Mode

n n−1n−2 2 n−2 2

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D I

S MODE

In I2S mode, the MSB of the left channel is valid on the second rising edge of the BCLK after the falling edge of ADWS or LRCK. Similarly the MSB of the right channel is valid on the second rising edge of the BCLK after the rising edge of ADWS or LRCK.

1/fs

ADWS/

LRCK

BCLK

1 clock before MSB

Left Channel Right Channel

DIN/

DOUT

n n−1 1 0 n n−1 1 0

n−2 2 n−2 2

LSBMSB

Figure 16. Timing Diagram for I2S Mode

D DSP MODE

In DSP mode, the falling edge of ADWS or LRCK starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of BCLK.

1/fs

ADWS/

LRCK

BCLK

Left Channel Right Channel

DIN/

DOUT

n n−1 1 0 n n−1 1 0

n−2 2 n−2 2 n−2

LSBMSB

MSB LSB

Figure 17. Timing Diagram for DSP Mode

n n−11 0

MSBLSB

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AUDIO DATA CONVERTERS

The ’AIC26 has a stereo audio DAC and a mono audio ADC. Both ADC and DAC can operate with a maximum sampling rate of 53 kHz and support all audio standard rates of 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz,

44.1 kHz, and 48 kHz. By utilizing the flexible clock generation capability and internal programmable interpolation, a wide variety of sampling rates up to 53 kHz can be obtained from many possible MCLK inputs. In addition, the DAC and ADC can independently operate at different sampling rates as indicated in control register REG−00H/Page2.

When the ADC or DAC is operating, the ’AIC26 requires an applied audio MCLK input. The user should also set bit D13/REG−06H/Page2 to indicate which Fsref rate is being used. If the codec ADC or DAC is powered up, then the auxiliary

Typical audio DACs can suffer from poor out-of-band noise performance when operated at low sampling rates, such as 8 kHz or 11.025 kHz. The ’AIC26 includes programmable interpolation circuitry to provide improved audio performance at such low sampling rates, by first upsampling low-rate data to a higher rate, filtering to reduce audible images, and then passing the data to the internal DAC, which is actually operating at the Fsref rate. This programmable interpolation is determined using bit D5−D3/REG−00H/Page2.

For example, if playback of 11.025-kHz data is required, the ’AIC26 can be configured such that Fsref = 44.1 kHz. Then using bit D5−D3/REG−00H/Page2, the DAC sampling rate (Fs) can be set to Fsref/4, or Fs = 1 1.025 kHz. In operation, the

11.025-kHz digital input data is received by the ’AIC26, upsampled to 44.1 kHz, and filtered for images. It is then provided to the audio DAC operating at 44.1 kHz for playback. In reality, the audio DAC further upsamples the 44.1 kHz data by a ratio of 128x and performs extensive interpolation filtering and processing on this data before conversion to a stereo analog output signal.

ADC uses MCLK and BCLK for its internal clocking, and the internal oscillator is powered down to save power.

PLL

The ’AIC26 has an on-chip PLL to generate the needed internal ADC and DAC operational clocks from a wide variety of clocks available in the system. The PLL supports an MCLK varying from 2 MHz to 50 MHz and is register programmable to enable generation of required sampling rates with fine precision.

ADC and DAC sampling rates are given by DAC_FS = Fsref/N1 and ADC_FS = Fsref/N2

where, Fsref must fall between 39 kHz and 53 kHz, and N1, N2 =1, 1.5, 2, 3, 4, 5, 5.5, 6 are register programmable.

The PLL can be enabled or disabled using register programming.

D When PLL is disabled

Fsref +

Q = 2, 3…17

− Note: For ADC, with N2 = 1.5 or 5.5, odd values of Q are not allowed.

− In this mode, the MCLK can operate up to 50 MHz, and Fsref should fall within 39 kHz to 53 kHz.

MCLK

128 Q

D When PLL is enabled

Fsref +

P = 1, 2, 3, …, 8 K = J.D J = 1, 2, 3, ….,64 D = 0, 1, 2, …, 9999 P, J, and D are register programmable, where J is an integer part of K before the decimal point, and D is a four-digit fractional

part of K after the decimal point, including lagging zeros. Examples: If K = 8.5, Then J = 8, D = 5000

If K = 7.12, Then J = 7, D = 1200 If K = 7.012, Then J = 7, D = 120

The PLL is programmed through Registers 1BH and 1CH of Page2.

MCLK K

2048 P

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D When PLL is enabled and D = 0, the following condition must be satisfied

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2MHzv

80 MHz v

4 v J v 55

MCLK

v 20 MHz

MCLK K

v 110 MHz

D When PLL is enabled and D ≠ 0, the following condition must be satisfied

10 MHz v

80 MHz v

4 v J v 11

Example 1:

For MCLK = 12 MHz and Fsref = 44.1 kHz P = 1, K = 7.5264 ⇒ J = 7, D = 5264

Example 2:

For MCLK = 12 MHz and Fsref = 48.0 kHz P = 1, K = 8.192 ⇒ J = 8, D = 1920

MONO AUDIO ADC

MCLK

v 20 MHz

MCLK K

v 110 MHz

Analog Front End

The analog front end of the audio ADC consists of an analog MUX and a programmable gain amplifier (PGA). The MUX can connect either the MICIN or AUX signal through the PGA to the ADC for audio recording. The ’AIC26 also has an option of choosing both MICIN and AUX as a differential input pair. The ’AIC26 also includes a microphone bias circuit, which can source up to 4.7-mA current and is programmable to a 2-V or 2.5-V level. The bias block is powered down when both the ADC and analog mixer blocks are powered down.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog antialiasing filtering are very relaxed. The ’AIC26 integrates a second order analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient antialiasing filtering without requiring any external components.

The PGA allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming. This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag (D0 control register 04H/Page2) is set whenever the gain applied by PGA equals the desired value set by the register. The soft−stepping control can be disabled by programming D15=1 in register 1DH of Page02. When soft-stepping is enabled, the MCLK signal to the device should not be changed until the ADC power-down flag is set. When the flag is set, the internal soft-stepping process and power-down sequence is complete, and the MCLK can be stopped if desired.

Delta-Sigma ADC

The analog-to-digital converter is a delta-sigma modulator with 128 times oversampling ratio. The ADC can support a maximum output rate of 53 kHz.

Decimation Filter

The audio ADC includes an integrated digital decimation filter that removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 times Fs to the final output sampling rate of Fs. The decimation filter provides a linear phase output response with a group delay of 17/Fs. The −3-dB bandwidth of the decimation filter extends to 0.45 Fs and scales with the sample rate (Fs)

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Automatic Gain Control (AGC)

Automatic gain control (AGC) can be used to maintain nominally constant output signal amplitude when recording speech signals. This circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The ’AIC26 allows programming of eight different target gains, which can be programmed from −5.5 dB to −24 dB relative to a full-scale signal. Since the ’AIC26 reacts to the signal absolute average and not to peak levels, it is recommended that the larger gain be set with enough margin to avoid clipping at the occurrence of loud sounds.

Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 8 ms to 20 ms.

Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied in the range from 100 ms to 500 ms.

Noise threshold is the minimum amplitude for the input signal that the AGC considers as a valid signal. If the average amplitude of the incoming signal falls below this value, the AGC considers it as silence and brings down the gain to 0 dB in steps of 0.5 dB for every FS. It also sets the noise threshold flag. The gain stays at 0 dB until the average amplitude of the input signal rises above the noise threshold value. This ensures that noise does not get amplified in the absence of a valid input speech signal. The noise threshold level is programmable between −60 dB and −90 dB relative to full scale. This operation includes debounce and hysteresis to avoid having the AGC gain cycle from high gain to 0 dB when the signal amplitude is close to the noise threshold level. When the noise threshold flag is set, the status of the gain applied by the AGC and the saturation flag should be ignored.

Maximum input gain applicable allows the user to restrict the maximum gain applied by the AGC. This can be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold. Depending on the noise threshold setting, the value of the maximum input gain applicable can be programmed between 0 dB and 59.5 dB in steps of 0.5 dB as shown in Table 1.

Table 1. Input Gain Settings

NOISE THRESHOLD ALLOWED RANGE FOR THE MAXIMUM INPUT GAIN

−60 dB 0 dB to 59.5 dB

−70 dB 11.5 dB to 59.5 dB

−80 dB 21.5 dB to 59.5 dB

−90 dB 31.5 dB to 59.5 dB

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TEXAS INSTRUMENTS TLV320AIC26 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual