TLV320AIC20K/24KEVM
User’s Guide
April 2005 Data Acquisition Products
SLAU088A
IMPORTANT NOTICE
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Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright © 2005, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright © 2005, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM with a maximum input supply voltage not exceeding 4 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI field
representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification, please
contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
30°C. The EVM is designed to operate properly with certain components above 40°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware that
these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright © 2005, Texas Instruments Incorporated
-4
About This Manual
How to Use This Manual
Preface
Read This First
This users guide describes the operation and use of the TLV320AIC20K codec
family. A complete circuit descriptiion, schematic diagram, and bill of materials
are also included.
How to Use This Manual
This document contains the following chapters:
- Chapter 1—EVM Overview
- Chapter 2—Digital Interface
- Chapter 3—Analog Interface
- Chapter 4—EVM Operation
- Chapter 5—TLV320AIC20K/24K Bill of Materials
- Appendix A—TLV320AIC20K/24K Schematic
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
iii
Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477-8924 or the Product
Information Center (PIC) at (972) 644-5580. When ordering, identify this
booklet by its title and literature number. Updated documents can also be
obtained through our website at www.ti.com.
Data Sheet: Literature Number:
TLV320AIC20K/24K SLAS363
iv
Contents
Contents
1 EVM Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Digital Interface 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Codec-to-Platform 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Jumper Options 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Stand-Alone Slave 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Single Master Only 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Master/Slave Cascade 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Analog Interface 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 EVM Operation 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 TLV320AIC20K/24K Bill of Materials 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A TLV320AIC20K/24K EVM Schematic A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
Contents
Figures
1−1 EVM 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 EVM Captured Signals 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
2−1 Pinout for 40-Pin Connector 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Jumper Options 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 Stand-Alone Slave Jumper Settings 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 Single Master Only Jumper Settings 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Master/Slave Cascade Jumper Settings 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 Analog Interface Connectors 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
Figure 1−1. EVM
Chapter 1
EVM Overview
This user’s guide provides support for the following EVMs:
- TLV320AIC20KEVM
- TLV320AIC24KEVM
The EVM is split into two complementary halves as shown in Figure 1−1.
SLAVE CODEC
MASTER CODEC
EVM Overview
1-1
1-2
Chapter 2
Digital Interface
The digital signals required to operate this codec originate from the 40-pin
connector—J21. There are two methods to drive the digital interface:
- Create a custom interface between the codec EVM and the host system.
- Alternatively, if a TI DSK (DSP starter kit) is the host system, a develop-
ment platform (AICDEVPLAT EVM) is available from TI. This platform provides the additional functions that the codec requires in a convenient form
factor.
Topic Page
2.1 Codec-to-Platform 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Jumper Options 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 System Level Considerations 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Interface
2-1
Codec-to-Platform
2.1 Codec-to-Platform
The TLV320AIC20K and 24K mate with the development platform via a 40-pin
Samtec connector. The mating connector (Samtec part number,
TSM-120-01-T-DV-P) is used on the development platform to provide the
electrical connections necessary. Consult Samtec at www.samtec.com
1−800−SAMTEC−9 for more information.
The pinout for the 40-pin connector is listed in Table 2−1.
Table 2−1. Pinout for 40-Pin Connector
Pin Number Signal Description
J21.1 MCLK Master clock
J21.2 DGND Digital ground
J21.3 SCLK Serial data clock
J21.4 DGND Digital ground
J21.5 DIN Data in
J21.6 DGND Digital ground
J21.7 DOUT Data out
J21.8 Reserved Reserved for future use
J21.9 FS Frame sync
J21.10 Reserved Reserved for future use
J21.11 CLKX Transmit clock
J21.12 Reserved Reserved for future use
J21.13 FSX Frame sync transmit
J21.14 Reserved Reserved for future use
J21.15 DX Data transmit
J21.16 DR Data receive
J21.17 RESET Global reset for all devices
J21.18 FSR Frame sync receive
J21.19 PWDN Global powerdown for all devices
J21.20 CLKR Receive clock
J21.21 CNTLb GPIO pin
J21.22 CNTLa GPIO pin
J21.23 STATb Status pin
J21.24 STATa Status pin
J21.25 3.3V_D Digital 3.3 V
J21.26 Reserved Reserved for future use
J21.27 3.3V_D Digital 3.3 V
J21.28 DGND Digital ground
J21.29 1.8V_D Digital 1.8 V
J21.30 DGND Digital ground
J21.31 1.8V_D Digital 1.8 V
J21.32 DGND Digital ground
or
2-2
Table 2−1. Pinout for 40-Pin Connector (Continued)
Pin Number Signal Description
J21.33 3.3V_A_DRV Output driver supply 3.3 V
J21.34 AGND Analog ground
J21.35 3.3V_A_DRV Output driver supply 3.3 V
J21.36 AGND Analog ground
J21.37 3.3V_A Analog 3.3 V
J21.38 AGND Analog ground
J21.39 3.3V_A Analog 3.3 V
J21.40 AGND Analog ground
The development platform supports a number of functions that the codecs
require. These are:
- MCLK generation
- Manual reset generation
- Power options
Refer to the DSP − Codec Development Platform User’s Guide (TI Literature
Number SLAU090) for details regarding the development platform.
Codec-to-Platform
Further descriptions regarding the operation of this EVM assumes that the
development platform is being used for all additional signals and power.
Digital Interface
2-3
Jumper Options
2.2 Jumper Options
There are eight jumpers on the board that can be configured in various ways,
depending upon the user’s requirements. Their functions are briefly presented
in Table 2−2:
Table 2−2. Jumper Options
Jumper Function
W1 Gives users the option of disconnecting the 3.3-V driver ground
W2 Manages FSD from the master. Either connecting FSD to the next
W3 Used along with W2 for correct polarity for FSD
W4 Selects whether U1 is either a master or a slave codec.
W5 Connects analog and digital ground together
P1.9–P1.10 Last FSD in the chain must be high
P1.11–P1.12 SCL must be high
P1.13–P1.14 SDA must be high
from the regular analog ground
codec or providing relevant polarity
Since the EVM contains two codecs, there a variety of options available to the
user:
- Stand-alone slave codec
- Single master codec
- Master/slave cascade
Note that the terms master and slave refer to the codec device itself. Keep in
mind that each of these codecs contains two independent channels connected
together internally. Thus any codec configuration described in this guide
actually comprises two individual codecs chained together and performing as
one unit.
Each of these options are discussed in the following sections.
2.2.1 Stand-Alone Slave
This configuration applies to EVM1 only. When a single codec is to be used
in slave mode, U1 is always the slave codec. Follow the jumper settings
detailed in Table 2−3 for this condition.
Table 2−3. Stand-Alone Slave Jumper Settings
2-4
Jumper 1−2 2−3
W2 Inserted Not inserted
W3 Not inserted Inserted
W4 Not inserted Inserted
P1.9–P1.10 N/A N/A
2.2.2 Single Master Only
This configuration applies to EVM1 only. When a single codec is to be used
in master mode, U1 is always the master codec. Follow the jumper settings
detailed in Table 2−4 for this condition.
Table 2−4. Single Master Only Jumper Settings
Jumper 1−2 2−3
W2 Inserted Not inserted
W3 Inserted Not inserted
W4 Inserted Not inserted
P1.9–P1.10 N/A N/A
2.2.3 Master/Slave Cascade
This configuration applies to EVM1 only and is the factory-set shipping
condition. When both codecs are used, both U1 and U2 are active. In this
condition U1 is always the master codec, and U2 is always the slave codec.
Follow the jumper settings detailed in Table 2−5.
Jumper Options
Table 2−5. Master/Slave Cascade Jumper Settings
Jumper 1−2 2−3
W2 Not inserted Inserted
W3 N/A N/A
W4 Inserted Not inserted
P1.9–P1.10 Inserted Inserted
Digital Interface
2-5
Chapter 3
Analog Interface
Table 3−1 indicates the applicable connectors for each codec. In order to
enable a wide range of sources and loads to be connected to the codecs,
screw terminals have been used wherever possible.
Table 3−1. Analog Interface Connectors
TLV320AIC20K TLV320AIC24K
Master Slave Master Slave
Input Sources
8-Ω Speaker output J2 J11 Not available
600-Ω Line output J5 J4 J5 J4
150-Ω Handset output J1 J9 J1 J9
150-Ω Headset output J8 J3 J8 J3
Output Loads
Handset input/INP2 J12 J19 J12 J19
Headset input/INP3 J10 J13 J10 J13
Microphone input J16 J20 J16 J20
Line input/INP1 J14 J15 J14 J15
Caller ID input/INP4 J17 J8 J17 J8
Analog Interface
3-1
3-2
Chapter 4
EVM Operation
The EVM is shipped from the factory in master/slave cascade mode. To check
if the EVM is working properly, simply install the EVM onto the development
platform and apply power to the DSK. The EVM should begin working
immediately.
In the default mode, the codecs recognize that there are four discrete
channels, consequently the resultant SCLK and FS signals transmitted by the
master codec adjust automatically based on the available MCLK.
It is now possible to calculate what should be observed after power up by
calculating what FS and SCLK should be observed:
- FS
J In this example, MCLK is generated by the development platform and
is equal to 100 MHz.
J FS = MCLK/16 × m × n × p
J Default values for m, n, and p are 16, 6, and 8 respectively
J FS = 100×10
J FS = 8138 kHz
- SCLK
J SCLK = 16 × FS × (number of devices) × 2
J SCLK = 16 × 8138 × 4 × 2
J SCLK = 1.04 MHz
FS can be observed either directly at the FS pin of U1 or U2 (pin 19) or on the
development platform at TP9. SCLK can be observed easily at P1 pin 3 of the
EVM or on the development platform at TP8.
6
/16 ×16 × 6 × 8
EVM Operation
4-1
The captured signals are shown in Figure 4−1.
Figure 4−1. EVM Captured Signals
FS
SCLK
4-2
µ
pp
12
0.1 µF
C14 C16
Capacitor 0.1 µF 25 V
Panasonic
ECJ 1VF1E104Z
C17 C18
C21 C23
CC5
16
0.1 µF
C1 C2 C3
Capacitor 0.1 µF 50 V
Panasonic
ECJ 2YB1H104K
C4 C5 C6
C7 C8 C9
C0C
µ
p µ
7
10 kΩ
R3 R4 R5
Resistor 10 kΩ 1/16 W 5%
Panasonic
ERJ 3GEYJ103V
R6 R7 R8
Chapter 5
TLV320AIC20K/24K Bill of Materials
The following table contains a complete bill of materials for the
TLV320AIC20K/24K codec EVM. The schematic diagram is also provided for
reference. Contact the Product Information Center or e-mail
dataconvapps@list.ti.com
Used Value Ref Des Description Vendor Part number
4 0.01 µF C20 C29 Capacitor 10000-pF 50-V
C32 C34
12 0.1 µF C14 C16 Capacitor 0.1-µF 25-V Panasonic ECJ-1VF1E104Z
C17 C18
C21 C23
C24 C25
C26 C28
C33 C35
16 0.1 µF C1 C2 C3 Capacitor 0.1-µF 50-V Panasonic ECJ-2YB1H104K
C4 C5 C6
C7 C8 C9
C10 C11
C12 C13
C15 C19
C27
4 1 µF C22 C30 Capacitor 1-µF 10-V ceramic
C31 C36
1 10 µF C37 Capacitor 10-µF 16-V VS
7 10 kΩ R3 R4 R5 Resistor 10-kΩ 1/16-W 5% Panasonic ERJ-3GEYJ103V
R6 R7 R8
R9
2 10 kΩ R1 R2 Resistor 10.0-kΩ 1/10-W
2
* Alternate IC CODEC dual-channel
1 TLV320AIC20 PWB Advanced Circuit Design 6442569
0 TLV320AIC20 DDB Texas Instruments 6442568
1 J21 40-Pin SMT socket Samtec SSW-120-22-F-D-VS-K
1 P1 40-Pin SMT plug Samtec TSM-120-01-T-DV-P
U1 U2 * IC CODEC dual-channel
ceramic Y5V 0603
ceramic Y5V 0603
ceramic X7R 0805
Y5V 0603
elect SMD
0603 SMD
1% 0805 SMD
PROG LP 48-TQFP
PROG LP 48-TQFP
for questions regarding this EVM.
Panasonic ECJ-1VF1H103Z
Panasonic ECJ-1VF1A105Z
Panasonic ECE-V1CA100SR
Panasonic ERJ-6ENF1002V
Texas Instruments TLV320AIC20KIPFB
Texas Instruments TLV320AIC24KIPFB
TLV320AIC20K/24K Bill of Materials
5-1
Used Part numberVendorDescriptionRef DesValue
14
J1 J2 J3
2 Terminal screw connector
Lumberg
KRMZ2
J4 J5 J8
J9 J10 J11
JJ3
jp
14 J1 J2 J3 2 Terminal screw connector Lumberg KRMZ2
J4 J5 J8
J9 J10 J11
J12 J13
J14 J15
J19
2 J16 J20 161−3504 Mouser 161-3504
2 J17 J18 4-Pin plug Samtec TSW-102-07-L-D
4 J6 J7 W1 2 Position jumper Samtec TSW-102-07-L-S
W5
3 W2 W3 W4 3 Position jumper Samtec TSW-103-07-L-S
2 See Assy
Dwg
2 See Assy
Dwg
2 See Assy
Dwg
1.000/4−40 Nylon hex threadSPKeystone Electronics 1902E
0.500/4−40 Nylon hex threadSPKeystone Electronics 1902C
4−40 X 1/4 Machine screw
PH SS
Building Fasteners PMSSS 440 0025 PH
5-2
Appendix A
TLV320AIC20K/24K EVM Schematic
The TLV320AIC20K/24KEVM schematics are provided on the following
pages.
TLV320AIC20K/24K EVM Schematic
A-1
54321
REV ECN Number Approved
6
Revision History
D
Analog_IO
Analog_IO
C
2xAIC20
2xAIC20
D
C
B
A
B
A
ti
12500 TI Boulevard. Dallas, Texas 75243
Title:
Engineer:
Drawn By:
FILE: SIZE:
1 2 3 4 56
Joe Purvis
Joe Purvis
AIC20 CODEC
System Block
DOCUMENTCONTROL #
DATE:
10-Feb-2005
REV:
SHEET: OF:
13
A6442568
54321
3.3V_D
3.3V_A
AGND
CIDI-_b
MICI-_b
MICI+_b
MICBIASb
35
34
36
D
LCDAC_b
HNSO-_b
HNSO+_b
HNSI-_b
HNSI+_b
3.3V_A
AGND
LINEI+_b
LINEI-_b
LINEO-_b
LINEO+_b
37
LCDAC
38
HNSO-
39
HNSO+
40
HNSI-
41
HNSI+
42
AVDD
43
AVSS
44
LINEI+
45
LINEI-
46
LINEO-
47
LINEO+
48
NC
C
MICI-
MICI+
MICBIAS
HDSI-1HDSI+2HDSO-3HDSO+4AVDD25AVSS26TESTP7NC8PWRDN*
CIDI+_b
32
33
31
30
CIDI-
CIDI+
AVSS1
AVDD1
DRV_AGND
29
DRVSS2
SPKO-_b
28
SPKO-
9
3.3V_A_DRV
SPKO+_b
27
26
SPKO+
DRVDD
SCL11IOVDD
SDA
10
DRV_AGND
25
DRVSS1
RESET*
MCLK
SCLK
DOUT
DVSS
DVDD
IOVSS
12
VSS
M/S
FS
DIN
FSD
U2
24
23
22
21
20
19
18
17
16
15
14
13
AGND
GBL_SYNC_RESET*
GBL_MCLK
DGND
GBL_SCLK
FS_2
GBL_DIN
GBL_DOUT
DGND
1.8V_D
FSD_2
DGND
TLV320AIC20K / 24K
Slave
GBL_MCLK
GBL_SCLK
GBL_DIN
GBL_DOUT
FSD_2
GBL_SCL
GBL_SDA
C30
1uF
C22
1uF
P1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
C28
0.1uF
C21
0.1uF
DGND
DGND
DGND
C29
0.01uF
C20
0.01uF
DGND
1.8V_D
DGND
R7
10K
C36
1uF
C31
1uF
3.3V_D
R6
10K
R5
10K
C35
0.1uF
C33
0.1uF
C34
0.01uF
C32
0.01uF
3.3V_D
DGND
1.8V_D
DGND
GBL_MCLK
GBL_SCLK
GBL_DIN
GBL_DOUT
FS_1
GBL_SCL
GBL_SDA
15 16
GBL_SYNC_RESET*
GBL_SYNC_PWDN*
HDSI-_b
HDSI+_b
GBL_SYNC_RESET*
DGND
3.3V_A
HDSO-_b
AGND
HDSO+_b
GBL_SYNC_PWDN*
GBL_SDA
3.3V_D
GBL_SCL
GBL_SYNC_PWDN*
17 18
19 20
21 22
23 24
3.3V_D
3.3V_D
3.3V_A
AGND
CIDI-_a
MICI-_a
MICI+_a
MICBIASa
34
36
35
MICI-
B
LCDAC_a
HNSO-_a
HNSO+_a
HNSI-_a
HNSI+_a
3.3V_A
AGND
LINEI+_a
LINEI-_a
LINEO-_a
LINEO+_a
37
LCDAC
38
HNSO-
39
HNSO+
40
HNSI-
41
HNSI+
42
AVDD
43
AVSS
44
LINEI+
45
LINEI-
46
LINEO-
47
LINEO+
48
NC
MICI+
MICBIAS
CIDI+_a
32
33
31
30
CIDI-
CIDI+
AVSS1
AVDD1
HDSI-1HDSI+2HDSO-3HDSO+4AVDD25AVSS26TESTP7NC8PWRDN*
A
DRV_AGND
29
DRVSS2
SPKO-_a
28
SPKO-
9
3.3V_A_DRV
SPKO+_a
27
26
SPKO+
DRVDD
SCL11IOVDD
SDA
10
DRV_AGND
25
DRVSS1
RESET*
MCLK
SCLK
DOUT
DVSS
DVDD
IOVSS
12
VSS
M/S
FS
DIN
FSD
U1
24
23
22
21
20
19
18
17
16
15
14
13
AGND
GBL_SYNC_RESET*
GBL_MCLK
M/S
GBL_SCLK
FS_1
GBL_DIN
GBL_DOUT
DGND
1.8V_D
FSD_1
DGND
TLV320AIC20K / 24K
Master / Slave
3.3V_D
R4
10K
W4
DGND
3.3V_D
R3
10K
W3
W2
FS_2
1.8V_D
1.8V_D
3.3V_A_DRV
3.3V_A_DRV
3.3V_A
3.3V_A
DGND
W5
DGND
3.3V_A
HDSI-_a
HDSI+_a
HDSO-_a
AGND
HDSO+_a
GBL_SYNC_PWDN*
GBL_SDA
GBL_SCL
3.3V_D
DGNDAGND
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
40-PIN PLUG
C17
0.1uF
C18
0.1uF
C23
0.1uF
DGND
AGND
C24
0.1uF
C25
0.1uF
C16
0.1uF
C26
0.1uF
C14
0.1uF
3.3V_A
AGND
3.3V_A_DRV
DRV_AGND
Engineer:
Drawn By:
FILE: SIZE:
3.3V_D
3.3V_D
1.8V_D
1.8V_D
3.3V_A_DRV
3.3V_A_DRV
3.3V_A
3.3V_A
W1
Joe Purvis
Joe Purvis
2xAIC20
REV ECN Number Approved
J21
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
40-PIN SOCKET
ti
12500 TI Boulevard. Dallas, Texas 75243
Title:
AIC20K / 24K
DOCUMENTCONTROL #
DATE:
10-Feb-2005
6
Revision History
DGND
DGND
DGND
SHEET: OF:
DGND
AGND
REV:
A6442568
23
D
C
B
A
1 2 3 4 56
54321
MICBIASa
J13
2
1
D
J3
2
HDSO-_b
1
HDSO+_b
J4
2
LINEO-_b
1
LINEO+_b
J15
2
1
C4
0.1uF
C8
0.1uF
C2
0.1uF
C6
HDSI-_b
HDSI+_b
LINEI-_b
LINEI+_b
CIDI+_b
CIDI-_b
LCDAC_b
C37
+
10uF
C7
0.1uF
AGND
HNSI+_a
HNSI-_a
C1
J10
2
J18
1
2 3
J7
LINEO-_b CIDI-_a
4
LINEO+_b
AGND
1
J14
2
1
R8
0.1uF
10K
AGND AGND
C9
0.1uF
C11
C3
0.1uF
HDSI+_a
HDSI-_a
LINEI-_a
LINEI+_a
J12
2
1
R9
10K
C5
0.1uF
0.1uF
REV ECN Number Approved
CIDI+_a
LCDAC_a
J17
J6
1
2 3
4
6
Revision History
LINEO-_a
LINEO+_a
AGND
D
0.1uF
J9
2
HNSO-_b
1
C
HNSO+_b
J8
2
HDSO-_a
1
HDSO+_a
C
J11
2
SPKO-_b
1
SPKO+_b
J19
2
1
C12
0.1uF
C10
HNSI-_b
HNSI+_b
J5
2
LINEO-_a
1
LINEO+_a
J1
2
HNSO-_a
1
HNSO+_a
0.1uF
J2
2
SPKO-_a
1
SPKO+_a
B
MICBIASb
C19
MICI+_b
0.1uF
R2
10K
J20
3
B
A
2
1
C15
0.1uF
MICI-_b
J16
3
B
A
2
1
R1
10K
C27
0.1uF
C13
0.1uF
MICBIASa
MICI+_a
MICI-_a
B
AGND
AGND
A
A
ti
12500 TI Boulevard. Dallas, Texas 75243
Title:
Engineer:
Joe Purvis
Drawn By:
Joe Purvis
FILE: SIZE:
Analog_IO
1 2 3 4 56
Analog I/O
DOCUMENTCONTROL #
DATE:
10-Feb-2005
REV:
SHEET: OF:
33
A6442568
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