TEXAS INSTRUMENTS TLV320AIC12, TLV320AIC13, TLV320AIC14, TLV320AIC15, TLV320AIC20 Technical data
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Texas Instruments (TI) has recently identified a problem in the product models listed above related to DLL
clock-generation. When a clock-generation mode is used that powers up the delay-locked-loop (DLL), the DLL
may not startup properly when initiated, resulting in the audio master clock not functioning. This results in the
codec in the products not functioning. This issue does not affect applications that do not enable the product’s
DLL.
TLV320AIC14, TLV320AIC15, TLV320AIC20
TLV320AIC21, TLV320AIC24, TLV320AIC25
PRODUCT NOTIFICATION
DEVICE LITERATURE NO.
TLV320AIC12 SLWS115
TLV320AIC13 SLWS139
TLV320AIC14 SLWS140
TLV320AIC15 SLWS141
TLV320AIC20 SLAS363
TLV320AIC21 SLAS365
TLV320AIC24 SLAS366
TLV320AIC25 SLAS367
TLV320AIC12, TLV320AIC13
OCTOBER 2003
Since this issue does not af fect operation if the DLL is not enabled, customers are recommended to ensure their
system does not enable the product’s DLL. The DLL is enabled anytime the P value in control register #4
(pertaining to clock generation) is NOT set equal to 8. The DLL is used whenever the part is in fine sampling
mode, as described in Section 3.1 of the data manual, so the recommended mode to use is the coarse sampling
mode, which requires P=8.
At present, TI does not have a screening procedure in place to detect product with the DLL issue, but the
company also realizes that many customers do not use the DLL in their systems and will be unaffected by this
issue.
TI is not confident of the operation of the DLL in this product at this time. To ensure customers have been made
aware of this issue, orders for these parts will only be filled upon return of a signed waiver until this issue is
resolved. The company has initiated an investigation to fully understand the root cause of this problem and
determine what appropriate long-term corrective action should be taken. TI recommends that all customers
presently using these parts contact the company immediately, so they can receive updates on this investigation
and plans for its resolution.
We apologize for the inconvenience placed upon customers in ordering this product. However, we wish to
ensure that our customers are aware of the device shortcomings from the specification. We are working in
earnest to remove this waiver requirement.
For further information, please contact
Neeraj Magotra
WW Strategic Marketing Manager for Voice/Audio Systems
Office: (214) 480-7486
nmagotra@ti.com
Copyright 2003, Texas Instruments Incorporated
Data Manual
May 2002 HPA Data Acquisition
SLWS140A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI pro d u cts or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Ordering Information 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Terminal Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Definitions and Terminology 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Functional Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Operating Frequencies 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Internal Architecture 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Antialiasing Filter 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Sigma-Delta ADC 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Decimation Filter 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Sigma-Delta DAC 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 Interpolation Filter 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 Analog/Digital/Side-Tone Loopback 3–2. . . . . . . . . . . . . . . . . . .
3.2.7 ADC PGA 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 DAC PGA 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Analog Input/Output 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 MIC Input 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 INP and INM Input 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Single-Ended Analog Input 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Analog Output 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 IIR/FIR Control 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Overflow Flags 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 IIR/FIR Bypass Mode 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 System Reset and Power Management 3–4. . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Software and Hardware Reset 3–4. . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Power Management 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Digital Interface 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Clock Source (MCLK, SCLK) 3–5. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Serial Data Out (DOUT) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Serial Data In (DIN) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4 Frame-Sync FS 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.5 Cascade Mode and Frame-Sync Delayed (FSD) 3–6. . . . . . . .
3.6.6 Stand-Alone Slave 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.7 Asynchronous Sampling (Codecs in cascade
are sampled at different sampling frequency) 3–6. . . . . . . . . . .
v
3.7 Host Port Interface 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 S
3.7.2 I
2
C (Start-Stop Communication) 3–9. . . . . . . . . . . . . . . . . . . . .
2
C3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Smart Time Division Multiplexed Serial Port (SMARTDM) 3–11. . . . . . . . .
3.8.1 Programming Mode 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Continuous Data Transfer Mode 3–12. . . . . . . . . . . . . . . . . . . . . .
3.8.3 Turbo Mode (SCLK) 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Control Register Programming 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1 Data Frame Format 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Control Frame Format (Programming Mode) 3–15. . . . . . . . . . .
3.9.3 Broadcast Register Write 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.4 Register Map 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Control Register Content Description 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Control Register 1 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Control Register 2 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Control Register 3 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Control Register 4 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Control Register 5A 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Control Register 5B 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Control Register 5C 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Control Register 5D 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Control Register 6 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Electrical Characteristics 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Free-Air
Temperature Range 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 5–1. . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Operating
Free-Air Temperature Range, AV
= 1.8 V, IOVDD = 3.3 V 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DV
DD
5.3.1 Digital Inputs and Outputs, f
= 3.3 V,
DD
= 8 kHz,
s
Outputs Not Loaded 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ADC Path Digital Filter, f
= 8 kHz 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
s
5.4.1 FIR Filter 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 IIR Filter 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 ADC Dynamic Performance, f
= 8 kHz 5–3. . . . . . . . . . . . . . . . . . . . . . . . .
s
5.5.1 ADC Signal-to-Noise 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2 ADC Signal-to-Distortion 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3 ADC Signal-to-Distortion + Noise 5–3. . . . . . . . . . . . . . . . . . . . .
5.5.4 ADC Channel Characteristics 5–3. . . . . . . . . . . . . . . . . . . . . . . .
5.6 DAC Path Digital Filter, fs = 8 kHz 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1 FIR Filter 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2 IIR Filter 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 DAC Dynamic Performance 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 OUTP/OUTM Signal-to-Noise When Load Is 600 Ω 5–4. . . . .
5.7.2 OUTP/OUTM Signal-to-Distortion When Load Is 600 Ω 5–4. .
vi
5.7.3 OUTP/OUTM Signal-to-Distortion + Noise When Load
Is 600 Ω 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.4 DAC Channel Characteristics 5–5. . . . . . . . . . . . . . . . . . . . . . . .
5.8 BIAS Amplifier Characteristics 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Power-Supply Rejection 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Power Supply 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Timing Requirements 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Layout and Grounding Guidelines for TLV320AIC14 5–13. . . . . . . . . . . . .
List of Illustrations
Figure Title Page
3–1 Microphone Interface 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 INP and INM Internal Self-Biased Circuit 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Single-Ended Input 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 OUTP1/OUTM1 Output 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Timing Diagram of FS 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Timing Diagram for FSD Output 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Cascade Connection (To DSP Interface) 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Master-Slave Frame-Sync Timing in Continuous Data
Transfer Mode 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9S
3–10 I
3–11 I
3–12 Index Register Addresses 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Standard Operation/Programming Mode: Stand-Alone Timing 3–12. . . . . . . . .
3–14 Standard Operation/Programming Mode: Master-Slave Cascade Timing 3–12
3–15 Standard Operation/Continuous Data Transfer Mode:
3–16 Standard Operation/Continuous Data Transfer Mode:
3–17 Timing Diagram for Turbo Operation 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Data Frame Format 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 Control Frame Data Format 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 Broadcast Register Write Example 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Hardware Reset Timing 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Serial Communication Timing 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 FFT—ADC Channel (–3 dB Input) 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 FFT—ADC Channel (–1 dB Input) 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 FFT—ADC Channel (–3 dB Input) 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Programming 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Write Sequence 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Read Sequence 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand-Alone Timing 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master-Slave Cascade Timing 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
5–6 FFT—DAC Channel (–3 dB Input) 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 FFT—DAC Channel (0 dB Input) 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 FFT—DAC Channel (–3 dB Input) 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 FFT—DAC Channel (0 dB Input) 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10. FFT—ADC Channel (–1 dB Input) 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 ADC FIR Frequency Response 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 ADC IIR Frequency Response 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 DAC IIR Frequency Response (OSR = 512) 5–10. . . . . . . . . . . . . . . . . . . . . . . . .
5–14 DAC IIR Frequency Response (OSR = 256) 5–10. . . . . . . . . . . . . . . . . . . . . . . . .
5–15 DAC IIR Frequency Response (OSR = 128) 5–11. . . . . . . . . . . . . . . . . . . . . . . . .
5–16 DAC FIR Frequency Response (OSR = 512) 5–11. . . . . . . . . . . . . . . . . . . . . . . .
5–17 DAC FIR Frequency Response (OSR = 256) 5–11. . . . . . . . . . . . . . . . . . . . . . . .
5–18 DAC FIR Frequency Response (OSR = 128) 5–11. . . . . . . . . . . . . . . . . . . . . . . .
5–19 Single-Ended Microphone Input (Internal Common Mode) 5–12. . . . . . . . . . . . .
5–20 Pseudo-Differential Microphone Input (External Common Mode) 5–13. . . . . . .
List of Tables
Table Title Page
3–1 SMARTDM Device Addresses 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Serial Interface Configurations 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Register Map 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Register Addresses 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Control Register 1 Bit Summary 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Control Register 2 Bit Summary 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Control Register 3 Bit Summary 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Control Register 4 Bit Summary 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Control Register 5A Bit Summary 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 A/D PGA Gain 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 Control Register 5B Bit Summary 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 D/A PGA Gain 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Digital Sidetone Gain 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–10 Input Buffer Gain 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–11 Control Register 6 Bit Summary 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
1 Introduction
The TLV320AIC14 is a true low-cost, low-power, high-performance, highly-integrated voiceband codec designed with
new technological advances. The TLV320AIC14 provides high resolution signal conversion from digital-to-analog
(D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology with programmable sampling rate.
1.1 Description
The TLV320AIC14 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design
innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free
interface to popular DSPs (i.e., C5x, C6x) and microcontrollers. The SMARTDM supports both continuous data
transfer mode and on-the-fly reconfiguration programming mode. SMARTDM maximizes the bandwidth of data
transfer between the TLV320AIC14 DSP codec and the DSP. In normal operation, it automatically detects the number
of codecs in the serial interface and adjusts the number of time slots to match the number of codecs so that no time
slot in the TDM frame is wasted. In the turbo mode, it maintains the same number of time slots but maximizes the
bit transferred rate to 25 MHz to give the DSP more bandwidth to process other tasks in the same sampling period.
The SMARTDM technology allows up to 16 codecs to share a single 4-wire serial bus.
The TL V320AIC14 also provides a flexible host port. The host port interface is a two-wire serial interface that can be
programmed to be either an industrial standard I
The TLV320AIC14 also integrates all of the critical functions needed for most voice-band applications including MIC
preamp, handset/headset preamps, antialiasing filter (AAF), input/output programmable gain amplifier (PGA), and
selectable low-pass IIR/FIR filters.
The TLV320AIC14 implements an extensive power management; including device power-down, independent
software control for turning off ADC, DAC, op-amps, and IIR/FIR filter (bypassable) to maximize system power
conservation. The TLV320AIC14 consumes only 10 mW at 3 V.
The TLV320AIC14’s low power operation from 2.7 V to 3.6 V for analog and I/O and 1.65 V to 1.95 V for digital core
power supplies, along with extensive power management, make it ideal for portable applications including wireless
accessories, hands free car kits, VOIP, cable modem, and speech processing. Its low group delay characteristic
makes it suitable for single or multichannel active control applications.
The TLV320AIC14 is characterized for commercial operation from 0°C to 70°C and industrial operation from –40°C
to 85°C.
2
C or a simple S2C (start-stop communication protocol).
1.2 Features
• C54x Software Driver Available
• 16-Bit Oversampling Sigma-Delta A/D Converter
• 16-Bit Oversampling Sigma-Delta D/A Converter
• Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to Be Used as Master Clock
• Selectable FIR/IIR Filter With Bypassing Option
• Programmable Sampling Rate up to:
– Max 26 KSPS With On-Chip IIR/FIR Filter
– Max 104 KSPS With IIR/FIR Bypassed
• On-Chip FIR Produced 84-dB SNR for ADC and 91-dB SNR for DAC Over 13-kHz BW
• External DSPs IIR/FIR for a Final Sampling Rate of 8 Ksps (IIR/FIR Bypassed) Produced 87-dB SNR for
ADC and 92-dB SNR for DAC.
SMARTDM is a trademark of Texas Instruments.
1–1
• Smart Time Division Multiplexed Serial Port (SMARTDM)
– Glueless 4-Wire Interface to DSP
– Automatic Cascade Detection (ACD) Self-Generates Master/Slave Device Addresses
– Programming Mode to Allow On-the-Fly Reconfiguration
– Continuous Data Transfer Mode to Support DSP’s DMA/Autobuffering Mode
– Turbo Mode to Maximize Bit Clock for Faster Data Transfer and Higher Data Bandwidth
– Total Number of Time Slots Dynamically Proportional to Number of Codecs in the Cascade to Eliminate
Unused Time Slots and Optimize DSP Memory Allocation
– Allows up to 16 Codecs to Be Connected to a Single Serial Port
• Host Port
– 2-Wire Interface
2
– Selectable I
C or S2C
• Differential and Single-Ended Analog Input/Output
• Built-In Functions:
– Sidetone
– Antialiasing Filter (AAF)
– Programmable Input and Output Gain Control (PGA)
– Microphone Amplifiers
– Power Management With Hardware/Software Power-Down Modes 30 µW
• Separate Software Control for ADC and DAC Power Down
• Fully Compatible With TI C54x DSP Power Supplies
– 1.65 V–1.95 V Digital Core Power
– 2.7 V–3.6 V Digital I/O
– 2.7 V–3.6 V Analog
• Power Dissipation (P
• Internal Reference Voltage (V
) 10 mW at 3 V in Standard Operation
D
)
ref
• 2s Complement Data Format
• Test Mode Which Includes Digital Loopback and Analog Loopback
1–2
1.3 Functional Block Diagram
MICIN
INP2
INM2
INP1
INM1
Analog
Loopback
OUTP1
(600 ΩDriver)
OUTM1
BIAS
1.35 V/2.35 V @ 5 mA max
s2d
MUX
– 42 dB to 20 dB
Step Size = 1 dB
Preamplifier
24, 12, 6, 0 dB
PGA
Anti-
Aliasing
Filter
– 42 dB to 20 dB
Step Size = 1 dB
Low-Pass
Filter
PGA
Sigma-
Delta
ADC
Sigma-
Delta
DAC
V
ref
Decimation Filter
Sinc
Filter
Interpolation Filter
Sinc
Filter
FIR Filter
IIR Filter
Digital Loopback
w/ Sidetone Control
and Mute
–3 dB to –21 dB
FIR Filter
IIR Filter
SMARTDM
Serial
Port
Host Port
M/S
DOUT
DIN
FS
SCLK
FSD
SCL
SDA
Internal Clock Circuit MCLK
Div
16xMxNxP
1–3
1–4
2 Terminal Descriptions
DBT PACKAGE
(TOP VIEW)
IOVSS
IOVDD
FSD
FS
DOUT
DIN
M/S
PWRDN
OUTM1
OUTP1
DRVDD
DRVSS
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DVSS
DVDD
SCLK
SDA
SCL
MCLK
RESET
INP1
INM1
BIAS
INM2
INP2
MICIN
AVDD
AVSS
2.1 Ordering Information
T
A
0°C to 70°C TLV320AIC14C
–40°C to 85°C TLV320AIC14I
30-TSSOP DBT PACKAGE
2.2 Terminal Functions
TERMINAL
NAME NO.
AVDD 17 I Analog power supply
AVSS 16 I Analog ground
BIAS 21 O Bias output voltage is software selectable between 1.35 V and 2.35 V. Its output current is 5 mA.
DIN 6 I Data input. DIN receives the DAC input data and register data from the external DSP (digital signal processor) and is
DOUT 5 O Data output. DOUT transmits the ADC output bits and registers data, and is synchronized to SCLK and FS. Data is
DRVDD 11 I Analog power supply for the 600-Ω driver
DRVSS 12 I Analog ground for the 600-Ω driver
DVDD 29 I Digital power supply
DVSS 30 I Digital ground
FS 4 I/O Frame sync. When FS goes low, DIN begins receiving data bits and DOUT begins transmitting data bits. In master
FSD 3 O Frame sync delayed output. The FSD output synchronizes a slave device to the frame sync of the master device. FSD
INM1 22 I Inverting analog input 1. It must be connected to AVSS if not used.
INM2 20 I Inverting analog input 2. It must be connected to AVSS if not used.
INP1 23 I Noninverting analog input 1. It must be connected to AVSS if not used.
INP2 19 I Noninverting analog input 2. It must be connected to AVSS if not used.
I/O
synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low.
sent out at the rising edge of SCLK when FS is low. Outside data/control frame, DOUT is put in 3-state.
mode, FS is internally generated and is low during the data transmission to DIN and from DOUT. In slave mode, FS is
externally generated.
is applied to the slave FS input and is the same duration as the master FS signal. This pin must be pulled low if AIC14 is
a stand-alone slave. It may be pulled high if the AIC14 is a stand-alone master or the last slave in the cascade.
DESCRIPTION
2–1
2.2 Terminal Functions (Continued)
TERMINAL
NAME NO.
IOVDD 2 I Digital I/O power supply
IOVSS 1 I Digital I/O ground
MCLK 25 I Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.
MICIN 18 I MIC preamplifier input. It must be connected to AVSS if not used.
M/S 7 I Master/slave select input. When M/S is high, the device is the master, and when low it is a slave.
OUTM1 9 O Inverting output of the DAC. OUTM1 is functionally identical with and complementary to OUTP1. This differential
NC 13, 14,
OUTP1 10 O Noninverting output of the DAC. This differential output can drive a minimum load of 600 Ω. This output can also be
PWRDN 8 I Power down. When PWRDN is pulled low, the device goes into a power-down mode, the serial interface is disabled,
RESET 24 I Hardware reset. The reset function is provided to initialize all of the internal registers to their default values. The
SCL 26 I Programmable host port (I2C or S2C) clock input.
SCLK 28 I/O Shift clock. SCLK signal clocks serial data into DIN and out of DOUT during the frame-sync interval. When
SDA 27 I/O Programmable host port (I2C or S2C) data line.
I/O
output can drive a minimum load of 600 Ω. This output can also be used alone for single-ended operation.
15
used alone for single-ended operation.
and most of the high-speed clocks are disabled. However, all the register values are sustained and the device
resumes full-power operation without reinitialization when PWRDN
counters only and preserves the programmed register contents.
serial port is configured to the default state accordingly.
configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync signal frequency b y
16 and the number of codecs in cascade in standard and continuous mode. When configured as an input (M/S low),
SCLK is generated externally and must be synchronous with the master clock and frame sync.
DESCRIPTION
is pulled high again. PWRDN resets the
2.3 Definitions and Terminology
Data Transfer
Interval
Signal Data This refers to the input signal and all of the converted representations through the ADC channel and the
Frame Sync Frame sync refers only to the falling edge of the signal FS that initiates the data transfer interval
Frame Sync and
Sampling Period
f
s
ADC Channel ADC channel refers to all signal processing circuits between the analog input and the digital
DAC channel DAC channel refers to all signal processing circuits between the digital data word applied to DIN and the
Dxx Bit position in the primary data word (xx is the bit number)
DSxx Bit position in the secondary data word (xx is the bit number)
PGA Programmable gain amplifier
IIR Infinite impulse response
FIR Finite impulse response
The time during which data is transferred from DOUT and to DIN. The interval is 16 shift clocks and the data
transfer is initiated by the falling edge of the FS signal in standard and continuous mode.
signal through the DAC channel to the analog output. This is contrasted with the purely digital software
control data.
Frame sync and sampling period is the time between falling edges of successive FS signals.
The sampling frequency
conversion result at DOUT.
differential output analog signal available at OUTP1 and OUTM1.
2–2
3 Functional Description
3.1 Operating Frequencies (see Notes)
The sampling frequency is the frequency of the frame sync (FS) signal whose falling edge starts digital-data transfer
for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by the following
equations:
• Coarse sampling frequency (default):
The coarse sampling is selected by programming P = 8 in the control register 4, which is the default
configuration of AIC14 on power-up or reset.
FS = Sampling (conversion) frequency = MCLK / (16 × M × N x 8)
• Fine sampling frequency (see Note 5):
FS = Sampling (conversion) frequency = MCLK/ (16 × M × N × P)
NOTES: 1. Use control register 4 to set the following values of M, N, and P
2. M = 1,2, . . . ,128
3. N = 1,2, . . . ,16
4. P = 1,2, . . . ,8
5. The fine sampling rate needs an on-chip DLL to generate internal clocks. The DLL requires the relationship
between MCLK and P to meet the following condition: 10 MHz ≤ (MCLK/P) ≤ 25 MHz
6. Both equations of FS require that the following conditions should be met:
S (M × N × P) ≥ (devnum × mode) if the FIR/IIR filter is not bypassed.
S [Integer(M/4) × N × P] ≥ (devnum × mode) if the FIR/IIR filter is bypassed.
where
devnum is the number of devices connecting in cascade
mode is equal to 1 for continuous data transfer mode and 2 for programming mode
EXAMPLE:
The MCLK comes from the DSP C5402’s CLKOUT and equals to 20.48 MHz and the conversion rate of 8 kHz is
desired. First, set P = 1 to satisfy the condition 5 so that (MCLK/P) = 20.48 MHz/1 = 20.48 MHz. Next, pick
M = 10 and N = 16 to satisfy condition 6 and derive 8 kHz for FS. That is,
FS = 20.48 MHz/ (16 × 10 × 16 × 1) = 8 kHz
3.2 Internal Architecture
3.2.1 Antialiasing Filter
The built-in antialiasing filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.
3.2.2 Sigma-Delta ADC
The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128-x oversampling. The ADC provides
high-resolution, low-noise performance using oversampling techniques. Due to the oversampling employed, only
single pole R-C filters are required on the analog inputs.
3.2.3 Decimation Filter
The decimation filters are either FIR filters or IIR filters, selected by bit D5 of the control register 1. The FIR filter
provides linear-phase output with 17/f group delay, whereas the IIR filter generates nonlinear phase output with
negligible group delay. The decimation filters reduce the digital data rate to the sampling rate. This is accomplished
by decimating with a ratio of 1:128. The output of the decimation filter is a 16-bit 2s-complement data word clocking
at the sample rate selected for that particular data channel. The BW of the filter is (0.45 × FS) and scales linearly with
the sample rate.
3–1
3.2.4 Sigma-Delta DAC
The sigma-delta digital-to-analog converter is a sigma-delta modulator with 128/256/512 x oversampling. The DAC
provides high-resolution, low-noise performance using oversampling techniques. The oversampling ratio in DAC is
programmable to 256/512 using bits D4–D3 of control register 3, the default being 128. Oversampling ratio of 512
can be used when FS is a maximum of 8 Ksps and an oversampling ratio of 256 can be used when FS is a maximum
of 16 Ksps. M should be a multiple of 2 for an oversampling ratio of 256 and 4 for oversampling ratio of 512.
3.2.5 Interpolation Filter
The interpolation filters are either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter
provides linear-phase output with 16/f group delay, whereas the IIR filter generates nonlinear phase output with
negligible group delay . The interpolation filter resamples the digital data at a rate of 128/256/512 times the incoming
sample rate, based on the oversampling rate of DAC. The high-speed data output from the interpolation filter is then
used in the sigma-delta DAC. The BW of the filter is (0.45 × FS) and scales linearly with the sample rate.
3.2.6 Analog/Digital/Side-Tone Loopback
The analog and digital loopbacks provide a means of testing the data ADC/DAC channels and can be used for
in-circuit system level tests. The analog loopback always has the priority to route the DAC low pass filter output into
the analog input where it is then converted by the ADC to a digital word. The digital loopback routes the ADC output
to the DAC input on the device. Analog loopback is enabled by writing a 1 to bit D2 in the control register 1. Digital
loopback is enabled by writing a 1 to bit D1 in control register 1. The side-tone digital loopback attenuates the ADC
output and mixes it with the input of the DAC. The level of the side tone is set by DSTG, bits D5–D3 of the control
register 5C.
3.2.7 ADC PGA
TLV320AIC14 has a built-in PGA for controlling the signal levels at ADC outputs. ADC PGA gain setting can be
selected by writing into bits D5–D0 of register 5A. The PGA range of the ADC channel is 20 dB to –42 dB in steps
of 1 dB and mute. To avoid sudden jumps in signal levels with PGA changes, the gains are applied internally with
zero-crossovers.
3.2.8 DAC PGA
TLV320AIC14 has a built-in PGA for controlling the analog output signal levels in DAC channel. DAC PGA gain setting
can selected by writing into bits D5–D0 of register 5B. The PGA range of the DAC channel is 20 dB to –42 dB in steps
of 1 dB, and mute. T o avoid sudden pop-sounds with power-up/down and gain changes the power-up/down and gain
changes for DAC channel are applied internally with zero-crossovers.
3.3 Analog Input/Output
The TLV320AIC14 has three programmable analog inputs and three programmable analog outputs. Bits D2–D1 of
control register 6 select the analog input source from MICIN, INP1/M1, or INP2/M2. All analog I/O is either
single-ended or d i fferentia l. Al l analog input signals are self-biased to 1.35 V. The three analog outputs are configured
by bits D7, D6, D5, and D4–D3 of control register 6.
3.3.1 MIC Input
TLV320AIC14 supports single ended microphone input. This can be used by connecting the external single ended
source through ac coupling to the MICIN pin. This channel is selected by writing 01 or 10 into bits D2–D1 in control
register 6. The single ended input is supported in two modes.
Writing 01 into bits D2–D1 chooses self biased MICIN mode. In this mode the device internally self-biases the input
at 1.35V. For best noise performance the user should bias the microphone circuit using the BIAS voltage generated
by the device as shown in Figure 5–19.
3–2
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