TEXAS INSTRUMENTS TLV320AIC12, TLV320AIC13, TLV320AIC14, TLV320AIC15, TLV320AIC20 Technical data
...
查询TLV320AIC12供应商
www.ti.com
Texas Instruments (TI) has recently identified a problem in the product models listed above related to DLL
clock-generation. When a clock-generation mode is used that powers up the delay-locked-loop (DLL), the DLL
may not startup properly when initiated, resulting in the audio master clock not functioning. This results in the
codec in the products not functioning. This issue does not affect applications that do not enable the product’s
DLL.
TLV320AIC14, TLV320AIC15, TLV320AIC20
TLV320AIC21, TLV320AIC24, TLV320AIC25
PRODUCT NOTIFICATION
DEVICE LITERATURE NO.
TLV320AIC12 SLWS115
TLV320AIC13 SLWS139
TLV320AIC14 SLWS140
TLV320AIC15 SLWS141
TLV320AIC20 SLAS363
TLV320AIC21 SLAS365
TLV320AIC24 SLAS366
TLV320AIC25 SLAS367
TLV320AIC12, TLV320AIC13
OCTOBER 2003
Since this issue does not af fect operation if the DLL is not enabled, customers are recommended to ensure their
system does not enable the product’s DLL. The DLL is enabled anytime the P value in control register #4
(pertaining to clock generation) is NOT set equal to 8. The DLL is used whenever the part is in fine sampling
mode, as described in Section 3.1 of the data manual, so the recommended mode to use is the coarse sampling
mode, which requires P=8.
At present, TI does not have a screening procedure in place to detect product with the DLL issue, but the
company also realizes that many customers do not use the DLL in their systems and will be unaffected by this
issue.
TI is not confident of the operation of the DLL in this product at this time. To ensure customers have been made
aware of this issue, orders for these parts will only be filled upon return of a signed waiver until this issue is
resolved. The company has initiated an investigation to fully understand the root cause of this problem and
determine what appropriate long-term corrective action should be taken. TI recommends that all customers
presently using these parts contact the company immediately, so they can receive updates on this investigation
and plans for its resolution.
We apologize for the inconvenience placed upon customers in ordering this product. However, we wish to
ensure that our customers are aware of the device shortcomings from the specification. We are working in
earnest to remove this waiver requirement.
For further information, please contact
Neeraj Magotra
WW Strategic Marketing Manager for Voice/Audio Systems
Office: (214) 480-7486
nmagotra@ti.com
Copyright 2003, Texas Instruments Incorporated
Data Manual
May 2002 HPA Data Acquisition
SLWS140A
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI pro d u cts or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Ordering Information 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Terminal Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Definitions and Terminology 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Functional Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Operating Frequencies 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Internal Architecture 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Antialiasing Filter 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Sigma-Delta ADC 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Decimation Filter 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Sigma-Delta DAC 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5 Interpolation Filter 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6 Analog/Digital/Side-Tone Loopback 3–2. . . . . . . . . . . . . . . . . . .
3.2.7 ADC PGA 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.8 DAC PGA 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Analog Input/Output 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 MIC Input 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 INP and INM Input 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Single-Ended Analog Input 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Analog Output 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 IIR/FIR Control 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Overflow Flags 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 IIR/FIR Bypass Mode 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 System Reset and Power Management 3–4. . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Software and Hardware Reset 3–4. . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Power Management 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Digital Interface 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Clock Source (MCLK, SCLK) 3–5. . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Serial Data Out (DOUT) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Serial Data In (DIN) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4 Frame-Sync FS 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.5 Cascade Mode and Frame-Sync Delayed (FSD) 3–6. . . . . . . .
3.6.6 Stand-Alone Slave 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.7 Asynchronous Sampling (Codecs in cascade
are sampled at different sampling frequency) 3–6. . . . . . . . . . .
v
3.7 Host Port Interface 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 S
3.7.2 I
2
C (Start-Stop Communication) 3–9. . . . . . . . . . . . . . . . . . . . .
2
C3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Smart Time Division Multiplexed Serial Port (SMARTDM) 3–11. . . . . . . . .
3.8.1 Programming Mode 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Continuous Data Transfer Mode 3–12. . . . . . . . . . . . . . . . . . . . . .
3.8.3 Turbo Mode (SCLK) 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Control Register Programming 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.1 Data Frame Format 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Control Frame Format (Programming Mode) 3–15. . . . . . . . . . .
3.9.3 Broadcast Register Write 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.4 Register Map 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Control Register Content Description 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Control Register 1 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Control Register 2 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Control Register 3 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Control Register 4 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Control Register 5A 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Control Register 5B 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Control Register 5C 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Control Register 5D 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Control Register 6 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Electrical Characteristics 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Free-Air
Temperature Range 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 5–1. . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Operating
Free-Air Temperature Range, AV
= 1.8 V, IOVDD = 3.3 V 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DV
DD
5.3.1 Digital Inputs and Outputs, f
= 3.3 V,
DD
= 8 kHz,
s
Outputs Not Loaded 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ADC Path Digital Filter, f
= 8 kHz 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
s
5.4.1 FIR Filter 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 IIR Filter 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 ADC Dynamic Performance, f
= 8 kHz 5–3. . . . . . . . . . . . . . . . . . . . . . . . .
s
5.5.1 ADC Signal-to-Noise 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2 ADC Signal-to-Distortion 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3 ADC Signal-to-Distortion + Noise 5–3. . . . . . . . . . . . . . . . . . . . .
5.5.4 ADC Channel Characteristics 5–3. . . . . . . . . . . . . . . . . . . . . . . .
5.6 DAC Path Digital Filter, fs = 8 kHz 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1 FIR Filter 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2 IIR Filter 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 DAC Dynamic Performance 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 OUTP/OUTM Signal-to-Noise When Load Is 600 Ω 5–4. . . . .
5.7.2 OUTP/OUTM Signal-to-Distortion When Load Is 600 Ω 5–4. .
vi
5.7.3 OUTP/OUTM Signal-to-Distortion + Noise When Load
Is 600 Ω 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.4 DAC Channel Characteristics 5–5. . . . . . . . . . . . . . . . . . . . . . . .
5.8 BIAS Amplifier Characteristics 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Power-Supply Rejection 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Power Supply 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Timing Requirements 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Layout and Grounding Guidelines for TLV320AIC14 5–13. . . . . . . . . . . . .
List of Illustrations
Figure Title Page
3–1 Microphone Interface 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 INP and INM Internal Self-Biased Circuit 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Single-Ended Input 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 OUTP1/OUTM1 Output 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Timing Diagram of FS 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Timing Diagram for FSD Output 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Cascade Connection (To DSP Interface) 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–8 Master-Slave Frame-Sync Timing in Continuous Data
Transfer Mode 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9S
3–10 I
3–11 I
3–12 Index Register Addresses 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Standard Operation/Programming Mode: Stand-Alone Timing 3–12. . . . . . . . .
3–14 Standard Operation/Programming Mode: Master-Slave Cascade Timing 3–12
3–15 Standard Operation/Continuous Data Transfer Mode:
3–16 Standard Operation/Continuous Data Transfer Mode:
3–17 Timing Diagram for Turbo Operation 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Data Frame Format 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 Control Frame Data Format 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 Broadcast Register Write Example 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Hardware Reset Timing 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Serial Communication Timing 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 FFT—ADC Channel (–3 dB Input) 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 FFT—ADC Channel (–1 dB Input) 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 FFT—ADC Channel (–3 dB Input) 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Programming 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Write Sequence 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Read Sequence 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stand-Alone Timing 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master-Slave Cascade Timing 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
5–6 FFT—DAC Channel (–3 dB Input) 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 FFT—DAC Channel (0 dB Input) 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 FFT—DAC Channel (–3 dB Input) 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 FFT—DAC Channel (0 dB Input) 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10. FFT—ADC Channel (–1 dB Input) 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 ADC FIR Frequency Response 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–12 ADC IIR Frequency Response 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 DAC IIR Frequency Response (OSR = 512) 5–10. . . . . . . . . . . . . . . . . . . . . . . . .
5–14 DAC IIR Frequency Response (OSR = 256) 5–10. . . . . . . . . . . . . . . . . . . . . . . . .
5–15 DAC IIR Frequency Response (OSR = 128) 5–11. . . . . . . . . . . . . . . . . . . . . . . . .
5–16 DAC FIR Frequency Response (OSR = 512) 5–11. . . . . . . . . . . . . . . . . . . . . . . .
5–17 DAC FIR Frequency Response (OSR = 256) 5–11. . . . . . . . . . . . . . . . . . . . . . . .
5–18 DAC FIR Frequency Response (OSR = 128) 5–11. . . . . . . . . . . . . . . . . . . . . . . .
5–19 Single-Ended Microphone Input (Internal Common Mode) 5–12. . . . . . . . . . . . .
5–20 Pseudo-Differential Microphone Input (External Common Mode) 5–13. . . . . . .
List of Tables
Table Title Page
3–1 SMARTDM Device Addresses 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Serial Interface Configurations 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Register Map 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Register Addresses 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Control Register 1 Bit Summary 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Control Register 2 Bit Summary 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Control Register 3 Bit Summary 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Control Register 4 Bit Summary 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Control Register 5A Bit Summary 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 A/D PGA Gain 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 Control Register 5B Bit Summary 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 D/A PGA Gain 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Digital Sidetone Gain 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–10 Input Buffer Gain 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–11 Control Register 6 Bit Summary 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
1 Introduction
The TLV320AIC14 is a true low-cost, low-power, high-performance, highly-integrated voiceband codec designed with
new technological advances. The TLV320AIC14 provides high resolution signal conversion from digital-to-analog
(D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology with programmable sampling rate.
1.1 Description
The TLV320AIC14 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design
innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free
interface to popular DSPs (i.e., C5x, C6x) and microcontrollers. The SMARTDM supports both continuous data
transfer mode and on-the-fly reconfiguration programming mode. SMARTDM maximizes the bandwidth of data
transfer between the TLV320AIC14 DSP codec and the DSP. In normal operation, it automatically detects the number
of codecs in the serial interface and adjusts the number of time slots to match the number of codecs so that no time
slot in the TDM frame is wasted. In the turbo mode, it maintains the same number of time slots but maximizes the
bit transferred rate to 25 MHz to give the DSP more bandwidth to process other tasks in the same sampling period.
The SMARTDM technology allows up to 16 codecs to share a single 4-wire serial bus.
The TL V320AIC14 also provides a flexible host port. The host port interface is a two-wire serial interface that can be
programmed to be either an industrial standard I
The TLV320AIC14 also integrates all of the critical functions needed for most voice-band applications including MIC
preamp, handset/headset preamps, antialiasing filter (AAF), input/output programmable gain amplifier (PGA), and
selectable low-pass IIR/FIR filters.
The TLV320AIC14 implements an extensive power management; including device power-down, independent
software control for turning off ADC, DAC, op-amps, and IIR/FIR filter (bypassable) to maximize system power
conservation. The TLV320AIC14 consumes only 10 mW at 3 V.
The TLV320AIC14’s low power operation from 2.7 V to 3.6 V for analog and I/O and 1.65 V to 1.95 V for digital core
power supplies, along with extensive power management, make it ideal for portable applications including wireless
accessories, hands free car kits, VOIP, cable modem, and speech processing. Its low group delay characteristic
makes it suitable for single or multichannel active control applications.
The TLV320AIC14 is characterized for commercial operation from 0°C to 70°C and industrial operation from –40°C
to 85°C.
2
C or a simple S2C (start-stop communication protocol).
1.2 Features
• C54x Software Driver Available
• 16-Bit Oversampling Sigma-Delta A/D Converter
• 16-Bit Oversampling Sigma-Delta D/A Converter
• Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to Be Used as Master Clock
• Selectable FIR/IIR Filter With Bypassing Option
• Programmable Sampling Rate up to:
– Max 26 KSPS With On-Chip IIR/FIR Filter
– Max 104 KSPS With IIR/FIR Bypassed
• On-Chip FIR Produced 84-dB SNR for ADC and 91-dB SNR for DAC Over 13-kHz BW
• External DSPs IIR/FIR for a Final Sampling Rate of 8 Ksps (IIR/FIR Bypassed) Produced 87-dB SNR for
ADC and 92-dB SNR for DAC.
SMARTDM is a trademark of Texas Instruments.
1–1
• Smart Time Division Multiplexed Serial Port (SMARTDM)
– Glueless 4-Wire Interface to DSP
– Automatic Cascade Detection (ACD) Self-Generates Master/Slave Device Addresses
– Programming Mode to Allow On-the-Fly Reconfiguration
– Continuous Data Transfer Mode to Support DSP’s DMA/Autobuffering Mode
– Turbo Mode to Maximize Bit Clock for Faster Data Transfer and Higher Data Bandwidth
– Total Number of Time Slots Dynamically Proportional to Number of Codecs in the Cascade to Eliminate
Unused Time Slots and Optimize DSP Memory Allocation
– Allows up to 16 Codecs to Be Connected to a Single Serial Port
• Host Port
– 2-Wire Interface
2
– Selectable I
C or S2C
• Differential and Single-Ended Analog Input/Output
• Built-In Functions:
– Sidetone
– Antialiasing Filter (AAF)
– Programmable Input and Output Gain Control (PGA)
– Microphone Amplifiers
– Power Management With Hardware/Software Power-Down Modes 30 µW
• Separate Software Control for ADC and DAC Power Down
• Fully Compatible With TI C54x DSP Power Supplies
– 1.65 V–1.95 V Digital Core Power
– 2.7 V–3.6 V Digital I/O
– 2.7 V–3.6 V Analog
• Power Dissipation (P
• Internal Reference Voltage (V
) 10 mW at 3 V in Standard Operation
D
)
ref
• 2s Complement Data Format
• Test Mode Which Includes Digital Loopback and Analog Loopback
1–2
1.3 Functional Block Diagram
MICIN
INP2
INM2
INP1
INM1
Analog
Loopback
OUTP1
(600 ΩDriver)
OUTM1
BIAS
1.35 V/2.35 V @ 5 mA max
s2d
MUX
– 42 dB to 20 dB
Step Size = 1 dB
Preamplifier
24, 12, 6, 0 dB
PGA
Anti-
Aliasing
Filter
– 42 dB to 20 dB
Step Size = 1 dB
Low-Pass
Filter
PGA
Sigma-
Delta
ADC
Sigma-
Delta
DAC
V
ref
Decimation Filter
Sinc
Filter
Interpolation Filter
Sinc
Filter
FIR Filter
IIR Filter
Digital Loopback
w/ Sidetone Control
and Mute
–3 dB to –21 dB
FIR Filter
IIR Filter
SMARTDM
Serial
Port
Host Port
M/S
DOUT
DIN
FS
SCLK
FSD
SCL
SDA
Internal Clock Circuit MCLK
Div
16xMxNxP
1–3
1–4
2 Terminal Descriptions
DBT PACKAGE
(TOP VIEW)
IOVSS
IOVDD
FSD
FS
DOUT
DIN
M/S
PWRDN
OUTM1
OUTP1
DRVDD
DRVSS
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DVSS
DVDD
SCLK
SDA
SCL
MCLK
RESET
INP1
INM1
BIAS
INM2
INP2
MICIN
AVDD
AVSS
2.1 Ordering Information
T
A
0°C to 70°C TLV320AIC14C
–40°C to 85°C TLV320AIC14I
30-TSSOP DBT PACKAGE
2.2 Terminal Functions
TERMINAL
NAME NO.
AVDD 17 I Analog power supply
AVSS 16 I Analog ground
BIAS 21 O Bias output voltage is software selectable between 1.35 V and 2.35 V. Its output current is 5 mA.
DIN 6 I Data input. DIN receives the DAC input data and register data from the external DSP (digital signal processor) and is
DOUT 5 O Data output. DOUT transmits the ADC output bits and registers data, and is synchronized to SCLK and FS. Data is
DRVDD 11 I Analog power supply for the 600-Ω driver
DRVSS 12 I Analog ground for the 600-Ω driver
DVDD 29 I Digital power supply
DVSS 30 I Digital ground
FS 4 I/O Frame sync. When FS goes low, DIN begins receiving data bits and DOUT begins transmitting data bits. In master
FSD 3 O Frame sync delayed output. The FSD output synchronizes a slave device to the frame sync of the master device. FSD
INM1 22 I Inverting analog input 1. It must be connected to AVSS if not used.
INM2 20 I Inverting analog input 2. It must be connected to AVSS if not used.
INP1 23 I Noninverting analog input 1. It must be connected to AVSS if not used.
INP2 19 I Noninverting analog input 2. It must be connected to AVSS if not used.
I/O
synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low.
sent out at the rising edge of SCLK when FS is low. Outside data/control frame, DOUT is put in 3-state.
mode, FS is internally generated and is low during the data transmission to DIN and from DOUT. In slave mode, FS is
externally generated.
is applied to the slave FS input and is the same duration as the master FS signal. This pin must be pulled low if AIC14 is
a stand-alone slave. It may be pulled high if the AIC14 is a stand-alone master or the last slave in the cascade.
DESCRIPTION
2–1
2.2 Terminal Functions (Continued)
TERMINAL
NAME NO.
IOVDD 2 I Digital I/O power supply
IOVSS 1 I Digital I/O ground
MCLK 25 I Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.
MICIN 18 I MIC preamplifier input. It must be connected to AVSS if not used.
M/S 7 I Master/slave select input. When M/S is high, the device is the master, and when low it is a slave.
OUTM1 9 O Inverting output of the DAC. OUTM1 is functionally identical with and complementary to OUTP1. This differential
NC 13, 14,
OUTP1 10 O Noninverting output of the DAC. This differential output can drive a minimum load of 600 Ω. This output can also be
PWRDN 8 I Power down. When PWRDN is pulled low, the device goes into a power-down mode, the serial interface is disabled,
RESET 24 I Hardware reset. The reset function is provided to initialize all of the internal registers to their default values. The
SCL 26 I Programmable host port (I2C or S2C) clock input.
SCLK 28 I/O Shift clock. SCLK signal clocks serial data into DIN and out of DOUT during the frame-sync interval. When
SDA 27 I/O Programmable host port (I2C or S2C) data line.
I/O
output can drive a minimum load of 600 Ω. This output can also be used alone for single-ended operation.
15
used alone for single-ended operation.
and most of the high-speed clocks are disabled. However, all the register values are sustained and the device
resumes full-power operation without reinitialization when PWRDN
counters only and preserves the programmed register contents.
serial port is configured to the default state accordingly.
configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync signal frequency b y
16 and the number of codecs in cascade in standard and continuous mode. When configured as an input (M/S low),
SCLK is generated externally and must be synchronous with the master clock and frame sync.
DESCRIPTION
is pulled high again. PWRDN resets the
2.3 Definitions and Terminology
Data Transfer
Interval
Signal Data This refers to the input signal and all of the converted representations through the ADC channel and the
Frame Sync Frame sync refers only to the falling edge of the signal FS that initiates the data transfer interval
Frame Sync and
Sampling Period
f
s
ADC Channel ADC channel refers to all signal processing circuits between the analog input and the digital
DAC channel DAC channel refers to all signal processing circuits between the digital data word applied to DIN and the
Dxx Bit position in the primary data word (xx is the bit number)
DSxx Bit position in the secondary data word (xx is the bit number)
PGA Programmable gain amplifier
IIR Infinite impulse response
FIR Finite impulse response
The time during which data is transferred from DOUT and to DIN. The interval is 16 shift clocks and the data
transfer is initiated by the falling edge of the FS signal in standard and continuous mode.
signal through the DAC channel to the analog output. This is contrasted with the purely digital software
control data.
Frame sync and sampling period is the time between falling edges of successive FS signals.
The sampling frequency
conversion result at DOUT.
differential output analog signal available at OUTP1 and OUTM1.
2–2
3 Functional Description
3.1 Operating Frequencies (see Notes)
The sampling frequency is the frequency of the frame sync (FS) signal whose falling edge starts digital-data transfer
for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by the following
equations:
• Coarse sampling frequency (default):
The coarse sampling is selected by programming P = 8 in the control register 4, which is the default
configuration of AIC14 on power-up or reset.
FS = Sampling (conversion) frequency = MCLK / (16 × M × N x 8)
• Fine sampling frequency (see Note 5):
FS = Sampling (conversion) frequency = MCLK/ (16 × M × N × P)
NOTES: 1. Use control register 4 to set the following values of M, N, and P
2. M = 1,2, . . . ,128
3. N = 1,2, . . . ,16
4. P = 1,2, . . . ,8
5. The fine sampling rate needs an on-chip DLL to generate internal clocks. The DLL requires the relationship
between MCLK and P to meet the following condition: 10 MHz ≤ (MCLK/P) ≤ 25 MHz
6. Both equations of FS require that the following conditions should be met:
S (M × N × P) ≥ (devnum × mode) if the FIR/IIR filter is not bypassed.
S [Integer(M/4) × N × P] ≥ (devnum × mode) if the FIR/IIR filter is bypassed.
where
devnum is the number of devices connecting in cascade
mode is equal to 1 for continuous data transfer mode and 2 for programming mode
EXAMPLE:
The MCLK comes from the DSP C5402’s CLKOUT and equals to 20.48 MHz and the conversion rate of 8 kHz is
desired. First, set P = 1 to satisfy the condition 5 so that (MCLK/P) = 20.48 MHz/1 = 20.48 MHz. Next, pick
M = 10 and N = 16 to satisfy condition 6 and derive 8 kHz for FS. That is,
FS = 20.48 MHz/ (16 × 10 × 16 × 1) = 8 kHz
3.2 Internal Architecture
3.2.1 Antialiasing Filter
The built-in antialiasing filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.
3.2.2 Sigma-Delta ADC
The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128-x oversampling. The ADC provides
high-resolution, low-noise performance using oversampling techniques. Due to the oversampling employed, only
single pole R-C filters are required on the analog inputs.
3.2.3 Decimation Filter
The decimation filters are either FIR filters or IIR filters, selected by bit D5 of the control register 1. The FIR filter
provides linear-phase output with 17/f group delay, whereas the IIR filter generates nonlinear phase output with
negligible group delay. The decimation filters reduce the digital data rate to the sampling rate. This is accomplished
by decimating with a ratio of 1:128. The output of the decimation filter is a 16-bit 2s-complement data word clocking
at the sample rate selected for that particular data channel. The BW of the filter is (0.45 × FS) and scales linearly with
the sample rate.
3–1
3.2.4 Sigma-Delta DAC
The sigma-delta digital-to-analog converter is a sigma-delta modulator with 128/256/512 x oversampling. The DAC
provides high-resolution, low-noise performance using oversampling techniques. The oversampling ratio in DAC is
programmable to 256/512 using bits D4–D3 of control register 3, the default being 128. Oversampling ratio of 512
can be used when FS is a maximum of 8 Ksps and an oversampling ratio of 256 can be used when FS is a maximum
of 16 Ksps. M should be a multiple of 2 for an oversampling ratio of 256 and 4 for oversampling ratio of 512.
3.2.5 Interpolation Filter
The interpolation filters are either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter
provides linear-phase output with 16/f group delay, whereas the IIR filter generates nonlinear phase output with
negligible group delay . The interpolation filter resamples the digital data at a rate of 128/256/512 times the incoming
sample rate, based on the oversampling rate of DAC. The high-speed data output from the interpolation filter is then
used in the sigma-delta DAC. The BW of the filter is (0.45 × FS) and scales linearly with the sample rate.
3.2.6 Analog/Digital/Side-Tone Loopback
The analog and digital loopbacks provide a means of testing the data ADC/DAC channels and can be used for
in-circuit system level tests. The analog loopback always has the priority to route the DAC low pass filter output into
the analog input where it is then converted by the ADC to a digital word. The digital loopback routes the ADC output
to the DAC input on the device. Analog loopback is enabled by writing a 1 to bit D2 in the control register 1. Digital
loopback is enabled by writing a 1 to bit D1 in control register 1. The side-tone digital loopback attenuates the ADC
output and mixes it with the input of the DAC. The level of the side tone is set by DSTG, bits D5–D3 of the control
register 5C.
3.2.7 ADC PGA
TLV320AIC14 has a built-in PGA for controlling the signal levels at ADC outputs. ADC PGA gain setting can be
selected by writing into bits D5–D0 of register 5A. The PGA range of the ADC channel is 20 dB to –42 dB in steps
of 1 dB and mute. To avoid sudden jumps in signal levels with PGA changes, the gains are applied internally with
zero-crossovers.
3.2.8 DAC PGA
TLV320AIC14 has a built-in PGA for controlling the analog output signal levels in DAC channel. DAC PGA gain setting
can selected by writing into bits D5–D0 of register 5B. The PGA range of the DAC channel is 20 dB to –42 dB in steps
of 1 dB, and mute. T o avoid sudden pop-sounds with power-up/down and gain changes the power-up/down and gain
changes for DAC channel are applied internally with zero-crossovers.
3.3 Analog Input/Output
The TLV320AIC14 has three programmable analog inputs and three programmable analog outputs. Bits D2–D1 of
control register 6 select the analog input source from MICIN, INP1/M1, or INP2/M2. All analog I/O is either
single-ended or d i fferentia l. Al l analog input signals are self-biased to 1.35 V. The three analog outputs are configured
by bits D7, D6, D5, and D4–D3 of control register 6.
3.3.1 MIC Input
TLV320AIC14 supports single ended microphone input. This can be used by connecting the external single ended
source through ac coupling to the MICIN pin. This channel is selected by writing 01 or 10 into bits D2–D1 in control
register 6. The single ended input is supported in two modes.
Writing 01 into bits D2–D1 chooses self biased MICIN mode. In this mode the device internally self-biases the input
at 1.35V. For best noise performance the user should bias the microphone circuit using the BIAS voltage generated
by the device as shown in Figure 5–19.
3–2
Writing 10 into bits D2–D1 chooses pseudo-differential MICIN mode. In this mode the single ended input is connected
through ac-coupling to MICIN and the bias voltage used to generate the signal is also ac coupled to INM1 as shown
in Figure 5–20. For best noise performance the MICIN and INM1 lines must be routed in similar fashion from the
microphone to the device for noise cancellation.
For high quality performance the single ended signal is converted internally into differential signal before being
converted. To improve the dynamic range with different types of microphones the device supports a pre-amp with
gain settings of 0/6/12/24 dB. This can be chosen by writing into bits D1–D0 of control register 5C.
0.1 µF
INM1
BIAS
MICIN
Electret
Microphone
10 kΩ
0.1 µF
BIAS
MICIN
TLV320AIC14 TLV320AIC14
(a) Single Ended (b) Pseudo -Differential (High Quality)
Electret
Microphone
10 kΩ
0.1 µF
Figure 3–1. Microphone Interface
3.3.2 INP and INM Input
To produce common-mode rejection of unwanted signal performance, the analog signal is processed differentially
until it is converted to digital data. The signal applied to the terminals INM1/2 and INP1/2 are differential to preserve
device specifications (see Figure 3–2). The signal source driving analog inputs (INP1/2 and INM1/2) should have low
source impedance for lowest noise performance and accuracy . T o obtain maximum dynamic range, the signal should
be ac-coupled to the input terminal.
INP1 or INP2
V
(INP)
1.35 V
INM1 or INM2
V
(INM)
TLV320AIC14
Figure 3–2. INP and INM Internal Self-Biased Circuit
3.3.3 Single-Ended Analog Input
The two differential inputs of (INP1/M1 and INP2/M2) can be configured to work as single-ended inputs by connecting
INP to the analog input and INM to ground (see Figure 3–3).
C
Analog Input
Figure 3–3. Single-Ended Input
INP1 or INP2
C
INM1 or INM2
3–3
3.3.4 Analog Output
The OUTP1 and OUTM1 are differential output from the DAC channel. The OUTP1 and OUTM1 can drive a load of
600-Ω directly and be either differential or single-ended (see Figure 3–4).
C
OUTP1
OUTP1
RL
OUTM1
Differential Output OUTP/OUTM
RL
OUTM1
Single-Ended Output OUTP/OUTM
Figure 3–4. OUTP1/OUTM1 Output
3.4 IIR/FIR Control
3.4.1 Overflow Flags
The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog signal
has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an overflow flag
(bit D4) of control register 1 indicating that the digital input has exceeded the range of internal interpolation filter
calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user reads the register.
Reading this value resets the overflow flag. These flags need to be reset after power-up by reading the register. If
FIR/IIR overflow occurs, the input signal is attenuated by either the PGA or some other method.
3.4.2 IIR/FIR Bypass Mode
An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This mode
is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to four times
normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS = 8 kHz) with IIR/FIR,
if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4×8 kHz = 32 kHz. The sinc filters of the two paths
can not be bypassed. A maximum of eight devices in cascade can be supported in the IIR/FIR bypassed mode.
In this mode , the ADC channel outputs data which has been decimated only till 4Fs. Similarly DAC channel input
needs to be pre-interpolated to 4Fs before being given to the device. This mode allows users the flexibility to
implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR Bypass
mode.
3.5 System Reset and Power Management
3.5.1 Software and Hardware Reset
The TLV320AIC14 resets internal counters and registers in response to either of two events:
• A low-going reset pulse is applied to terminal RESET
• A 1 is written to the programmable software reset bits (D3 of control register 3)
NOTE:The TLV320AIC14 requires a power-up reset applied to the RESET pin.
Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active low)
signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC14 enters the
3–4
initialization cycle that lasts for 132 MCLKs, during which the DSPs serial port is put in 3-state. For a cascaded system
the rise time of H/W RESET needs to be less than the MCLK period and should satisfy setup time requirement of 2 ns
with respect to MCLK rise-edge. In stand-alone-slave mode SCLK must be running during RESET. RESET must be
synchronized with MCLK in all cases.
3.5.2 Power Management
Most of the device (except the digital interface) enters the power-down mode when D7 and D6, in control register 3,
are set to 1. When the PWRDN
preserved and the output of the amplifier is held at midpoint voltage to minimize pops and clicks.
The amount of power drawn during software power down is higher than during a hardware power down because of
the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs.
pin is low, the entire device is powered down. In either case, register contents are
3.5.2.1 Software Power-Down
Data bits D7 and D6 of control register 3 are used by TLV320AIC14 to turn on or off the software power-down mode,
which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In the software
power-down, the digital interface circuit is still active while the internal ADC and DAC channel and differential output
OUTP1 and OUTM1 are disabled, and DOUT is put in 3-state in the data frame only. Register data in the control frame
is still accepted via DIN, but data in the data frame is ignored. The device returns to normal operation when D7 and
D6 of control register 3 are reset.
3.5.2.2 Hardware Power-Down
The TLV320AIC14 requires the PWRDN signal to be synchronized with MCLK. When PWRDN is held low, the device
enters hardware power-down mode. In this state, the internal clock control circuit and the differential outputs are
disabled. All other digital I/Os are disabled and DIN can not accept any data input. The device can only be returned
to normal operation by holding PWRDN
PWRDN
must be tied high.
high. When not holding the device in the hardware power-down mode,
3.6 Digital Interface
3.6.1 Clock Source (MCLK, SCLK)
MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout the
device. SCLK is the bit clock used to receive and transmit data synchronously. When the device is in the master mode,
SCLK and FS are output and derived from MCLK in order to provide clocking the serial communications between the
device and a digital signal processor (DSP). When in the slave mode, SCLK and FS are inputs. In the non-turbo mode
(TURBO = 0), SCLK frequency is defined by:
SCLK = (16 × FS × #Devices × mode)
Where:
FS is the frame-sync frequency.
#Device is the number of the device in cascade.
Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
In turbo mode, see Section 3.8.3.
3.6.2 Serial Data Out (DOUT)
DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data word
is the ADC conversion result. In the control frame, the data is the register read results when requested by the
read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all zeroes. Valid
data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The first bit transmitted
on the falling edge of FS is the MSB of valid data.
3–5
3.6.3 Serial Data In (DIN)
The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of FS. In a data
frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is used, the LSB (D0) is
set to 1 to switch from the continuous data transfer mode to the programming mode. In a control frame, the data is
the control and configuration data that sets the device for a particular function as described in Section 3.9, Control
Register Programming.
3.6.4 Frame-Sync FS
The frame-sync signal (FS) indicates the device is ready to send and receive data. FS is an output if the M/S pin is
connected to HI (master mode) and an input if the M/S pin is connected to LO (slave mode).
Data is valid on the falling edge of the FS signal.
The frequency of FS is defined as the sampling rate of the TLV320AIC14 and derived from the master clock MCLK
as followed (see Section 3.1 Operating Frequencies for details):
FS = MCLK / (16× P × N × M)
0 1 15 1614
SCLK
16 SCLKs
FS
DIN/DOUT
(16 Bit)
D15 D14
MSB LSB
D2 D1
D0
Figure 3–5. Timing Diagram of FS
3.6.5 Cascade Mode and Frame-Sync Delayed (FSD)
In cascade mode, the DSP receives all frame-sync pulses from the master though the master’s FS. The master’s FSD
is output to the first slave and the first slave’s FSD is output to the second slave device and so on. Figure 3–7 shows
the cascade of 4 TLV320AIC14s in which the closest one to DSP is the master and the rest are slaves. The FSD output
of each device is input to the FS terminal of the succeeding device. Figure 3–8 shows the FSD timing sequence in
the cascade.
3.6.6 Stand-Alone Slave
In the stand-alone slave connection, the FS and SCLK are input in which they need to be synchronized to each other
and programmed according to Section 3.1 (Operating Frequencies). The FS and SCLK input are not required to
synchronize to the MCLK input but must remain active at all times to assure continuous sampling in the data converter .
FS is output for initial 132 MCLK and it must be kept low. DSP needs to keep FS low-or high-impedance state for this
period to avoid contention on FS.
3.6.7 Asynchronous Sampling
(Codecs in cascade are sampled at different sampling frequency)
The AIC14’s SMARTDM support different sampling frequency between the different codecs in cascade connecting
to a single serial port. In this case, all codecs are required to sample at the same fdrequency that is the frequency
of FS signal. Then the desired sampling frequency of each codec is calculated by D2–D0 of control register 3. For
example: fs1 and fs2 are desired sampling rates for CODEC1 and CODEC2 respectively:
3–6
1. FS = MCLK/(16xMxNxP)
2. FS = n1 x fs1 (n1 = 1,2, 0, 8 defined in the control register 3 of CODEC1)
3. FS = n2 x fs2 (n2 = 1,2, 0, 8 defined in the control register 3 of CODEC2)
For validating the conversion data from this operation:
For DAC: DSP need to give same data for n1 samples. CODEC1 picks one of n1 samples.
For ADC: CODEC1 gives same data for n1 samples. DSP should pick one of n1 samples.
0 1 14 1513
SCLK
FS
16 SCLKs
FSD
(Output)
CLKOUT
FSX
FSR
CLKX
CLKR
TMS320C5x
DIN/DOUT
(16 Bit)
DX
DR
100 MHz Max
MCLK
FS
SCLK
DOUT
Figure 3–7. Cascade Connection (To DSP Interface)
D15 D14
MSB LSB
D1 D0
D15
Figure 3–6. Timing Diagram for FSD Output
Slave 2 Slave 1 Slave 0Master
MCLK
DIN
FSD
IOVDD
M/S M/S M/S M/S
DIN
DOUT
FS
SCLK
FSD FSD
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
FSD
IOVDD
1 kΩ
3–7
Master FS
DIN/DOUT
Master FSD,
Slave 2 FS
Slave 2 FSD,
Slave 1 FS
Slave 1 FSD,
Slave 0 FS
Slave 0 FSD,
(see Note)
NOTE: Slave 0 FSD should be pulled high for stand-alone-master or cascade configuration. FSD must be pulled low for stand-alone-slave
configuration.
Master Slave2 Slave1 Slave0 Slave2Master
Figure 3–8. Master-Slave Frame-Sync Timing in Continuous Data Transfer Mode
3.7 Host Port Interface
The host port uses a 2-wire serial interface (SCL, SDA) to program the AIC14s six control registers and selectable
protocol between S2C mode and I2C mode. The S2C is a write-only mode and the I
by setting the MSB (I2CSEL bit) of control register 4 to 1. If the host interface is not needed, the two pins of SCL and
SDA can be programmed to become general-purpose I/Os by setting the MSB of the control register 4 to 0. If selected
to be used as I/O pins, the SDA and SCL pins become output and input pins respectively, determined by D1 and D0.
Both S2C and I2C require a SMARTDM device address to communicate with the AIC14. One of SMARTDMs
advanced features is the automatic cascade detection (ACD) that enables SMARTDM to automatically detect the total
number of codecs in the serial connection and use this information to assign each codec a distinct SMARTDM device
address. Table 3–1 lists device addresses assigned to each codec in the cascade by the SMARTDM. The master
always has the highest position in the cascade. For example, if there is a total of 8 codecs in the cascade (i.e., one
master and 7 slaves), then the device addresses in row 8 are used in which the master is codec 7 with a device
address of 0111.
Table 3–1. SMARTDM Device Addresses
TOTAL
CODECS
1 0000
2 0001 0000
3 0010 0001 0000
4 0011 0010 0001 0000
5 0100 0011 0010 0001 0000
6 0101 0100 0011 0010 0001 0000
7 0110 0101 0100 0011 0010 0001 0000
8 0111 0110 0101 0100 0011 0010 0001 0000
9 1000 0111 0110 0101 0100 0011 0010 0001 0000
10 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
11 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
12 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
13 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
14 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
15 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
16 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CODECs POSITION IN CASCADE
2
C is a read-write mode selected
3–8
3.7.1 S2C (Start-Stop Communication)
The S2C is a write-only interface selected by programming bits D1-D0 of control register 2 to 01. The SDA input is
normally in a high state, pulled low (START bit) to start the communication, and pulled high (STOP bit) after the
transmission of the LSB. Figure 3–9 shows the timing diagram of S2C. The S2C also supports a broadcast mode in
which the same register of all devices in cascade is programmed in a single write. To use S2Cs broadcast mode,
execute the following steps:
1. Write 111 1000 1111 1111 after the start bit to enable the broadcast mode.
2. Write data to program control register as specified in with bits D14–D11 = XXXX (don’t care).
3. Write 111 1000 0000 0000 after the start bit to disable the broadcast mode.
SCL
SDA
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Start Bit = 0 Stop Bit = 1
SMARTDM Device
Address
(see Table 3–1)
Register
Address
Register Content
Figure 3–9. S2C Programming
3.7.2 I2C
• Each I2C read-from or write-to AIC14s control register is given by index register address.
• Read/write sequence always starts with the first byte as I2C address followed by 0. During the second byte,
default/broadcast mode is set and the index register address is initialized. For write operation control
register, data to be written is given from the third byte onwards. For read operation, stop-start is performed
after the second byte. Now the first byte is I
register data appears.
• Each time read/write is performed, the index register address is incremented so that next read/write is
performed on the next control register.
• During the first write cycle and all write cycles in the broadcast, only the device with address 0000 issues
ACK to the I
2
C.
2
C address followed by 1. From the second byte onwards, control
I2C Write Sequence
SCL
SDA
Start Bit = 0
Programmable I2C Device Address
A5 A4 A3 A2A1A0 0
I2C5I2C4I2C
6
Set by Control Register 2
SMARTDM Device
Address
(see Table 3-1)
B7 B6 B5 B4 B3 R2 R1 R0A6 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
ACK
00000 = Default
11111 = Broadcast Mode
Index Register Address
ACK ACK ACK
(Index)
Control Register Data for Write
(Index)
Control Register Data for Write
(Index+1)
Figure 3–10. I2C Write Sequence
3–9
I2C Read Sequence
SCL
SDA
Start Bit = 0
SCL
SDA
Start Bit = 0
Programmable I2C Device Address
A6 ACK
6
Programmable I2C Device Address
Set by Control Register 2
A5 A4 A3 A2
I2CI2CI2C
654
Set by Control Register 2
A5 A4 A3 A2
I2CI2CI2C
54
SMARTDM Device Address
SMARTDM Device Address
(see Table 3-1)
A0 0
A1
(see Table 3-1)
A0 0
A1
ACK
B7 B6 B5 B4 B3 R2 R1 R0
xxxxx = Don’t Care
ACK
D7 D6 D5 D4 D3 D2 D1 D0A6
Control Register Data
(Index)
Index Register Address
(Index)
ACK ACK
Stop Bit = 1
D7 D6 D5 D4 D3 D2 D1 D0
Control Register Data
(Index+1)
Figure 3–11. I2C Read Sequence
Each AIC has an index register address. To perform a write operation, make the LSB of the first byte as 0 (write) (see
Figure 3–12). During the second byte, the index register address is initialized and mode (broadcast/default) is set.
From the third byte onwards, write data to the control register (given by index register) and increment the index
register until stop or repeated start occurs. For operation, make the LSB of the first byte as 1 (read). From the second
byte onwards, AIC starts transmitting data from the control register (given by the index register) and increments the
index register. For setting the index register perform operation the same as write case for 2 bytes, and then give a
stop or repeated start.
S/Sr –> Start/Repeated Start.
Write Mode
7 Bit 1 Bit 8 Bit 8 Bit 8 Bit
S/Sr I2C Device Address (3 Bit)+
Dtdmsp Device Address (+)
Read Mode
7 Bit 1 Bit 8 Bit 8 Bit
S/Sr I2C Device Address (3 Bit)+
Dtdmsp Device Address (+)
For Initializing Index Reg Address
7 Bit 1 Bit 8 Bit
S/Sr I2C Device Address (3 Bit)+
Dtdmsp Device Address (+)
Default/Broadcast
(00000/11111)
R/W
= 0
R/W
= 1
Mode (5 Bit) + Index Reg
Ack
Control Reg. Data
Ack
(Read)
Address
(3 Bit)
Ack Control Reg. Data
Ack Control Reg. Data
From The Address Given
by Index Reg. Address
R/W
= 0
Mode (5 Bit) + Index Reg.
Ack
Address
(3 Bit)
Ack
Figure 3–12. Index Register Addresses
(Write)
To The Address Given
by Index Reg. Address
Increment Index Reg. AddressIncrement Index Reg. Address
(Read)
From The Address Given
by Index Reg. Address
Stop
Increment Index Reg. Address
Ack Control Reg. Data
(Write)
To The Address Given
by Index Reg. Address
Ack
3–10
3.8 Smart Time Division Multiplexed Serial Port (SMARTDM)
TLV320AIC14
The SMART time division multiplexed serial port (SMARTDM) uses the 4 wires of DOUT, DIN, SCLK, and FS to
transfer data into and out of the AIC14. The TLV320AIC14s SMARTDM supports three serial interface configurations
(see Table 3–2): stand-alone master, stand-alone slave, and master-slave cascade, employing a time division
multiplexed (TDM) scheme (a cascade of only-slaves is not supported). The SMARTDM allows for a serial connection
of up to 16 codecs to a single serial port. Data communication in these three serial interface configurations can be
carried out in either standard operation (default) or turbo operation. Each operation has two modes; programming
mode (default mode) and continuous data transfer mode. To switch from the programming mode to the continuous
data transfer mode, set bit D6 of control register 1 to 1, which resets after switching back to programming mode. The
TLV320AIC14 can be switched back from the continuous data transfer mode to the programming mode by setting
the LSB of the data on DIN to 1, only if the data format is (15+1), as selected by bit 0 of control register 1. The
SMARTDM automatically adjusts the number of time slots per frame sync (FS) to match the number of codecs in the
serial interface so that no time slot is wasted. Both the programming mode and the continuous data transfer mode
of the TLV320AIC14 are compatible with the TLV320AIC10. The TLV320AIC14 provides primary/secondary
communication and continuous data transfer with improvements and eliminates the requirements for hardware and
software requests for secondary communication as seen in the TLV320AIC10. The TLV320AIC14 continuous data
transfer mode now supports both master/slave stand-alone and cascade.
Table 3–2. Serial Interface Configurations
TLV320AIC14
CONNECTIONS
Stand-alone master High NA Pull high NA
Stand-alone slave NA Low NA Pull-low
Master-slave cascade High Low
Slave-slave cascade NA NA NA NA Not supported
M/S PIN FSD PIN
MASTER SLAVE MASTER SLAVE
Connect to the next slave’s FS
(see Figure 3–7)
COMMENTS
Last slave’s FSD pin is pulled high
3.8.1 Programming Mode
In the programming mode, the FS signal starts the input/output data stream. Each period of FS contains two frames
as shown in Figures 3–13 and 3–14: data frame and control frame. The data frame contains data transmitted from
the ADC or to the DAC. The control frame contains data to program the AIC14s control registers. The SMARTDM
automatically sets the number of time slots per frame equal to 2 times the number of AIC14 codecs in the interface.
Each time slot contains 16-bit data. The SCLK is used to perform data transfer for the serial interface between the
AIC14 codecs and the DSP. The frequency of SCLK varies depending on the selected mode of serial interface. In
the stand-alone mode, there are 32 SCLKs (or two time slots) per sampling period. In the master-slave cascade
mode, the number of SLCKs equals 32x(Number of codecs in the cascade). The digital output data from the ADC
is taken from DOUT. The digital input data for the DAC is applied to DIN. The synchronization clock for the serial
communication data and the frame-sync is taken from SCLK. The frame-sync signal that starts the ADC and DAC
data transfer interval is taken from FS. The SMARTDM also provides a turbo mode, in which the FS’s frequency is
always the device’s sampling frequency, but SCLK is running at a much higher speed. Thus, there are more than 32
SCLKs per sampling period, in which the data frame and control frame occupy only the first 32 SCLKs from the falling
edge of the frame-sync FS (also see Section 3.6 for more details).
3–11
SCLK
FS
Slot Number 0
Slot Number 1
DIN
DOUT
16–Bit DAC Data Register Data Write
16–Bit ADC Data Register Data Read
Figure 3–13. Standard Operation/Programming Mode: Stand-Alone Timing
Slot
Number
SCLK
FS
DIN/
DOUT
NOTE: n is the total number of AIC14s in the cascade
0 12 2n–12n–22n–3
Master Slave
n–2
Slave
n–3
Data Frame Control Frame
Figure 3–14. Standard Operation/Programming Mode: Master-Slave Cascade Timing
3.8.2 Continuous Data Transfer Mode
16 SCLKs Per Slot
Slave2Slave1Slave0Master Slave
n–2
Slave
n–3
(Register R/W)
Slave2Slave1Slave
0
The continuous data transfer mode, selected by setting bit D6 of the control register 1 to 1, contains conversion data
only . In continuous data transfer mode, the control frame is eliminated and the period of FS signal contains only the
data frame in which the 16-bit data is transferred contiguously , with no inactivity between bits. The control frame c a n
be reactivated by setting the LSB of DIN data to 1 if the data is in the 15+1 format. To return the programming mode
in the 16-bit DAC data format mode, write 0 in bit D6 of control register 1 using I
2
C or S2C, or do a hardware reset
to come out of continuous data transfer mode. The continuous data transfer mode can support the TI DSP McBSPs
autobuffering unit (ABU) operation in which the serial port interrupts are not generated with each word transferred
to prevent CPU’s ISR overheads.
3–12
SCLK
FS
Slot Number 0
Data Frame Data Frame
Slot Number 0
DIN
DOUT
16-Bit DAC Data (Sample 1)
16-Bit ADC Data (Sample 1)
16-Bit DAC Data (Sample 2)
16-Bit ADC Data (Sample 2)
(Sample 3)
(Sample 3)
Figure 3–15. Standard Operation/Continuous Data Transfer Mode: Stand-Alone Timing
Slot
Number
SCLK
FS
DIN/
DOUT
NOTE: n is the total number of AIC14s in the cascade
0 12 n–1n–2n–3 01 2 n–1n–2n–3
16 SCLKs Per Time Slot
Master Slave
n–2
Slave
n–3
Data Frame / Sample 1
Slave2Slave1Slave0Master Slave
Slave
n–2
n–3
Data Frame / Sample 2
Slave
2
Slave1Slave
Figure 3–16. Standard Operation/Continuous Data Transfer Mode: Master-Slave Cascade Timing
0
3.8.3 Turbo Mode (SCLK)
Setting TURBO = 1 (bit D7) in control register 2 enables the turbo mode that requires the following condition to be
met:
• For master with SCLK as output, M × N > #Devices × mode
Where:
M, N, and P are clock divider values defined in the control register 4.
#Device is the number of the device in cascade.
Mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
• For slave, SCLK is the input with max allowable speed of 25 MHz (no condition is required)
The turbo mode is useful for applications that require more bandwidth for multitasking processing per sampling
period. In the turbo mode (see Figure 3–17), the FSs frequency is always the device’s sampling frequency but the
SCLK is running at much higher speed than that described in Section 3.6.1. The output SCLK frequency is equal to
(MCLK/P) in master mode and up to a maximum speed of 25 MHz for both master and slave AIC14. The data/control
frame is still 16-SCLK long and the FS is one-SCLK pulse. Therefore, the DSP can maximize its data processing
bandwidth by taking advantage of time available between the end of AIC14s control frame and the next frame-sync
FS to process other tasks.
3–13
TURBO PROGRAMMING MODE
Stand-Alone Case:
Turbo SCLK
FS
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
One SCLK
Sampling Period
DIN / DOUT
Data Frame
15 14 1 0 1415 1 0 1415 1 0
...
Control Frame
...
Cascade Case (Master + 4 Slaves):
Turbo SCLK
FS
DIN / DOUT
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Sampling Period
Data Frame Control Frame Data Frame
TURBO CONTINUOUS DATA TRANSFER MODE
Stand-Alone Case:
Turbo SCLK
FS
DIN / DOUT
•••••••••••••••••••••••••••••••••••••••••••••••••••••
One SCLK
Data Frame
... ...
15 14
10 1415 1 0
Cascade Case (Master + 4 Slaves):
Sampling Period
Hi-Z
Hi-Z
Hi-Z
Data Frame Control Frame
...
Data Frame
...
1415 1 0
Hi-Z
Control Frame
Turbo SCLK
FS
DIN / DOUT
•••••••••••••••••••••••••••••••••••••••••••••••••
Sampling Period
Data Frame
Hi-Z
Data Frame
Hi-Z
NOTE: SCLK is not drawn to scale.
Figure 3–17. Timing Diagram for Turbo Operation
3.9 Control Register Programming
The TLV320AIC14 contains six control registers that are used to program available modes of operation. All register
programming occurs during the control frame through DIN. New configuration takes effect after a delay of one frame
sync FS except the software reset, which happens after 6 MCLKs from the falling edge of the next frame sync FS.
The TLV320AIC14 is defaulted to the programming mode upon power up. Set bit 6 in control register 1 to switch to
continuous data transfer mode. If the 15+1 data format of DIN has been selected, the LSB of the DIN to 1 to switch
from continuous data transfer mode to programming set mode. Otherwise, either the device needs to be reset or the
host port writes 0 to bit D6 of control register 1 during the continuous data transfer mode to switch back to the
programming mode.
3–14
3.9.1 Data Frame Format
(15+1) Bit Mode
DIN
(Continuous Data Transfer Mode Only)
DOUT
(16 Bit A/D Data)
DIN
16 Bit Mode
DOUT
16 Bit Mode
D15 – D1
A/D and D/A Data
D15 – D0
D15 – D0
A/D and D/A Data
D15 – D0
D0
Control Frame
Request
Figure 3–18. Data Frame Format
3.9.2 Control Frame Format (Programming Mode)
During the control frame, the DSP sends 16-bit words to the SMARTDM(TM) through DIN to read or write control
registers shown in Table 3–3. The upper byte (Bits D15–D8) of the 16-bit control-frame word defines the read/write
command. Bits D15–D13 define the control register address with register content occupied the lower byte D7–D0.
Bit D12 is set to 0 for a write or to 1 for a read. Bit D11 in the write command is used to perform the broadcast mode.
During a register write, the register content is located in the lower byte of DIN. During a register read, the register
content is output in the lower byte of DOUT in the same control frame, whereas the lower byte of DIN is ignored.
3.9.3 Broadcast Register Write
Broadcast operation is very useful for a cascading system of SMARTDM DSP codecs in which all register
programming can be completed in one control frame. During the control frame and in any register-write time slot, if
the broadcast bit (D11) is set to 1, the register content of that time slot is written into the specified register of all devices
in cascade (see Figure 3–20). This reduces the DSP’s overhead of doing multiple writes to program same data into
cascaded devices.
Data to be Written Into Register
DIN (Write)
D15
D15 D13D14
SMARTDM Device
Register
Address
Address
D13D14
R/W Broadcast
1DIN (Read)
0
Register
Address
Figure 3–19. Control Frame Data Format
111D110
111
0D9D10D11DOUT (Read) D15 D13D14 D12
D7 – D0
Don’t care
D7 – D0
Register Content
D7 – D0
3–15
Master FS
Data Frame Control Frame
DIN
Time Slot
Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0Slave0
Write
Command
Reg Addr (D15–D13)
R/W (D12)
Broadcast (D11)
D10–D8
001(1)
0
1
111
010(2)
0
1
111
100(4)
0
1
111
110(6)
0
1
111
NOTE: In this example, the broadcast operation (D11 = 1) is used to program the four control registers of Reg.1, Reg.2, Reg.4, and Reg.6 in all
4 DSP codecs (Master, Slave2, Slave1, and Slave0) shown in Figure 3–8. These registers are programmed during the same frame.
Figure 3–20. Broadcast Register Write Example
3.9.4 Register Map
Bits D15 through D13 represent the control register address that is written with data carried in D7 through D0. Bit D12
determines a read or a write cycle to the addressed register. When D12 = 0, a write cycle is selected. When
D12 = 1, a read cycle is selected. Bit D11 controls the broadcast mode as described above, in which the broadcast
mode is enabled if D11 is set to 1. Always write 1s to bits D10 through D8.
Table 3–3 shows the register map.
Table 3–3. Register Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Address RW BC 1 1 1 Control Register Content
Table 3–4. Register Addresses
REGISTER NO. D15 D14 D13 REGISTER NAME
0 0 0 0 No operation
1 0 0 1 control 1
2 0 1 0 control 2
3 0 1 1 control 3
4 1 0 0 control 4
5 1 0 1 control 5
6 1 1 0 control 6
3–16
4 Control Register Content Description
4.1 Control Register 1
D7 D6 D5 D4 D3 D2 D1 D0
ADOVF CX IIR DAOVF BIASV ALB DLB DAC16
R R/W R/W R R/W R/W R/W R/W
NOTE: R = Read, W = Write
Table 4–1. Control Register 1 Bit Summary
BIT NAME
D7 ADOVF 0 ADC over flow. This bit indicates whether the ADC is overflow.
D6 CX 0 Continuous data transfer mode. This bit selects between programming mode and continuous data transfer
D5 IIR 0 IIR Filter. This bit selects between FIR and IIR for decimation/interpolation low-pass filter.
D4 DAOVF 0 DAC over flow. This bit indicates whether the DAC is overflow
D3 BIASV 0 Bias voltage. This bit selects the output voltage for BIAS pin
D2 ALB 0 Analog loop back
D1 DLB 0 Digital loop back
D0 DAC16 0 DAC 16-bit data format. This bit applies to the continuous data transfer mode only to enable the 16-bit data
RESET
VALUE
FUNCTION
ADOVF = 0 No overflow.
ADOVF = 1 A/D is overflow.
mode.
CX = 0 Programming mode.
CX = 1 Continuous data transfer mode.
IIR = 0 FIR filter is selected.
IIR = 1 IIR filter is selected.
DAOVF = 0 No overflow.
DAOVF = 1 DAC is overflow
BIASV = 0 BIAS pin = 2.35V
BIASV = 1 BIAS pin = 1.35V
DLB = 0 Analog loopback disabled
DLB = 1 Analog loopback enabled
DLB = 0 Digital loopback disabled
DLB = 1 Digital loopback enabled
format for DAC input.
DAC16 = 0 DAC input data length is 15 bits. Writing a 1 to the LSB of the DAC input to switch from continuous
data transfer mode to programming mode.
DAC16 = 1 DAC input data length is 16 bit.
4–1
4.2 Control Register 2
D7 D6 D5 D4 D3 D2 D1 D0
TURBO
R/W R/W R/W R/W R/W R/W R/W R/W
NOTE: R = Read, W = Write
BIT NAME
D7 TURBO 0 Turbo mode. This bit is used to set the SCLK rate.
D6 DIFBP 0 Decimation/interpolation filter bypass. This bit is used to bypass both decimation and interpolation filters.
D5–D3 I2Cx 100 I2C device address. These three bits are programmable to define three MSBs of the I2C device address (reset
D2 GPO 0 General-purpose output
D1–D0 HPC 00 Host port control bits.
DIFBP I2C6 I2C5 I2C4 GPO HPC
Table 4–2. Control Register 2 Bit Summary
RESET
VALUE
TURBO = 0 SCLK = (16 × FS × #Device × mode)
TURBO = 1 SCLK = MCLK/P (P is determined in register 4)
DIFBP = 0 Decimation/interpolation filters are operated.
DIFBP = 1 Decimation/interpolation filters are bypassed.
value is 100). These three bits are combined with the 4-bit SMARTDM device address to form 7-bit I2C device
address.
Write the following values into D1–D0 to select the appropriate configuration for two pins SDA and SCL. SDA pin
is set to be equal to D2 if D1–D0 = 10.
D1–D0
0 0 SDA and SCL pins are used for I2C interface
1 1 SDA and SCL pins are used for S2C interface
0 0 SDA pin = D2, input going into SCL pin is output to DOUT
1 1 SDA pin = Control frame flag.
FUNCTION
4.3 Control Register 3
D7 D6 D5 D4 D3 D2 D1 D0
PWDN SWRS OSR-option ASRF
R/W R/W R/W R/W R/W
NOTE: R = Read, W = Write
Table 4–3. Control Register 3 Bit Summary
BIT NAME
D7–D6 PWDN 00 Power down
D5 SWRS 0 Software reset. Set this bit to 1 to reset the device.
D4-D3 OSR op-
tion
D2-D0 ASRF 001 Asynchronous sampling rate factor. These three bits define the ratio n between FS frequency and the
RESET
VALUE
PWDN = 00 No power down
PWDN = 01 Power-down A/D
PWDN = 10 Power-down D/A
PWDN = 11 Software power down the entire device
00 OSR option.
D4–D3=X1 OSR for DAC Channel is 512( Max Fs=8Ksps)
D4–D3=10 OSR for DAC Channel is 256( Max Fs=16Ksps)
D4–D3=00 OSR for DAC Channel is 128(Max Fs=26Ksps)
desired sampling frequency fs (Applied only if different sampling rate between CODEC1 and CODEC2 is
desired)
ASRF = 001 n = FS/fs = 1
ASRF = 010 n = FS/fs = 2
ASRF = 011 n = FS/fs = 3
ASRF = 100 n = FS/fs = 4
ASRF = 101 n = FS/fs = 5
ASRF = 110 n = FS/fs = 6
ASRF = 111 n = FS/fs = 7
ASRF = 000 n = FS/fs = 8
FUNCTION
4–2
4.4 Control Register 4
D7 D6 D5 D4 D3 D2 D1 D0
FSDIV
R/W R/W R/W R/W R/W R/W R/W R/W
NOTE: R = Read, W = Write
Table 4–4. Control Register 4 Bit Summary
BIT NAME
D7 FSDIV 0 Frame sync division factor
D6–D0 MNP — Divider values of M,N, and P to be used in junction with the FSDIV bit for calculation of FS frequency according
RESET
VALUE
FSDIV = 0 To write value of P to bits D2-D0 and value of N to bits D6-D3
FSDIV = 1 To write value of M to bits D6-D0
to the formula FS = MCLK / (16xMxNxP)
• M = 1,2,…,128 Determined by D6-D0 with FSDIV = 1
D7-D0 = 10000000 M = 128
D7-D0 = 10000001 M = 1
•
•
D7-D0 = 11111111 M = 127
• N = 1,2,…,16 Determined by D6-D3 with FSDIV = 0
D7-D0 = 00000xxx N = 16
D7-D0 = 00001xxx N = 1
•
•
D7-D0 = 01111xxx N = 15
MNP
FUNCTION
• P = 1,2,…,8 Determined by D2-D0 with FSDIV = 0
D7-D0 = 0xxxx000 P = 8
D7-D0 = 0xxxx001 P = 1
•
•
D7-D0 = 0xxxx111 P = 7
NOTES: 1. It takes 2 sampling periods to update new values of M,N, and P.
2. In register read operation, first read receives N and P values and second read receives M value.
3. M(default) = 16, N(default) = 6, P(default) = 8
4. If P = 8, the device enters the coarse sampling mode as described in Section 3.1 Operating Frequencies
4.5 Control Register 5A
D7 D6 D5 D4 D3 D2 D1 D0
0
R/W R/W R/W R/W R/W R/W R/W R/W
NOTE: R = Read, W = Write
BIT NAME
D7-D6 Control
Register 5A
D5-D0 ADGAIN 101010 A/D converter gain (see T able 4–6)
NOTES: 5. In register read operation, first read receives ADC gain value, second read receives DAC gain value, third read receives register
5C contents, and fourth read receives register 5D contents.
6. PGA default value = 101010b (0dB) for both ADC and DAC.
0 ADGAIN
Table 4–5. Control Register 5A Bit Summary
RESET
VALUE
00 ADC programmable gain amplifier
FUNCTION
4–3
Table 4–6. A/D PGA Gain
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 0 1 1 1 1 1 1 ADC input PGA gain = MUTE
0 0 1 1 1 1 1 0 ADC input PGA gain = 20 dB
0 0 1 1 1 1 0 1 ADC input PGA gain = 19 dB
0 0 1 1 1 1 0 0 ADC input PGA gain = 18 dB
0 0 1 1 1 0 1 1 ADC input PGA gain = 17 dB
0 0 1 1 1 0 1 0 ADC input PGA gain = 16 dB
0 0 1 1 1 0 0 1 ADC input PGA gain = 15 dB
0 0 1 1 1 0 0 0 ADC input PGA gain = 14 dB
0 0 1 1 0 1 1 1 ADC input PGA gain = 13 dB
0 0 1 1 0 1 1 0 ADC input PGA gain = 12 dB
0 0 1 1 0 1 0 1 ADC input PGA gain = 11 dB
0 0 1 1 0 1 0 0 ADC input PGA gain = 10 dB
0 0 1 1 0 0 1 1 ADC input PGA gain = 9 dB
0 0 1 1 0 0 1 0 ADC input PGA gain = 8 dB
0 0 1 1 0 0 0 1 ADC input PGA gain = 7 dB
0 0 1 1 0 0 0 0 ADC input PGA gain = 6 dB
0 0 1 0 1 1 1 1 ADC input PGA gain = 5 dB
0 0 1 0 1 1 1 0 ADC input PGA gain = 4 dB
0 0 1 0 1 1 0 1 ADC input PGA gain = 3 dB
0 0 1 0 1 1 0 0 ADC input PGA gain = 2 dB
0 0 1 0 1 0 1 1 ADC input PGA gain = 1 dB
0 0 1 0 1 0 1 0 ADC input PGA gain = 0 dB
0 0 1 0 1 0 0 1 ADC input PGA gain = -1 dB
0 0 1 0 1 0 0 0 ADC input PGA gain = -2 dB
0 0 1 0 0 1 1 1 ADC input PGA gain = -3 dB
0 0 1 0 0 1 1 0 ADC input PGA gain = -4 dB
0 0 1 0 0 1 0 1 ADC input PGA gain = -5 dB
0 0 1 0 0 1 0 0 ADC input PGA gain = -6 dB
0 0 1 0 0 0 1 1 ADC input PGA gain = -7 dB
0 0 1 0 0 0 1 0 ADC input PGA gain = -8 dB
0 0 1 0 0 0 0 1 ADC input PGA gain = -9 dB
0 0 1 0 0 0 0 0 ADC input PGA gain = -10 dB
0 0 0 1 1 1 1 1 ADC input PGA gain = -11 dB
0 0 0 1 1 1 1 0 ADC input PGA gain = -12 dB
0 0 0 1 1 1 0 1 ADC input PGA gain = -13 dB
0 0 0 1 1 1 0 0 ADC input PGA gain = -14 dB
0 0 0 1 1 0 1 1 ADC input PGA gain = -15 dB
0 0 0 1 1 0 1 0 ADC input PGA gain = -16 dB
0 0 0 1 1 0 0 1 ADC input PGA gain = -17 dB
0 0 0 1 1 0 0 0 ADC input PGA gain = -18 dB
0 0 0 1 0 1 1 1 ADC input PGA gain = -19 dB
0 0 0 1 0 1 1 0 ADC input PGA gain = -20 dB
0 0 0 1 0 1 0 1 ADC input PGA gain = -21 dB
0 0 0 1 0 1 0 0 ADC input PGA gain = -22 dB
4–4
Table 4–6. A/D PGA Gain (Continued)
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 0 0 1 0 0 1 1 ADC input PGA gain = -23dB
0 0 0 1 0 0 1 0 ADC input PGA gain = -24 dB
0 0 0 1 0 0 0 1 ADC input PGA gain = -25 dB
0 0 0 1 0 0 0 0 ADC input PGA gain = -26 dB
0 0 0 0 1 1 1 1 ADC input PGA gain = -27 dB
0 0 0 0 1 1 1 0 ADC input PGA gain = -28 dB
0 0 0 0 1 1 0 1 ADC input PGA gain = -29 dB
0 0 0 0 1 1 0 0 ADC input PGA gain = -30 dB
0 0 0 0 1 0 1 1 ADC input PGA gain = -31 dB
0 0 0 0 1 0 1 0 ADC input PGA gain = -32 dB
0 0 0 0 1 0 0 1 ADC input PGA gain = -33 dB
0 0 0 0 1 0 0 0 ADC input PGA gain = -34 dB
0 0 0 0 0 1 1 1 ADC input PGA gain = -35 dB
0 0 0 0 0 1 1 0 ADC input PGA gain = -36 dB
0 0 0 0 0 1 0 1 ADC input PGA gain = -37 dB
0 0 0 0 0 1 0 0 ADC input PGA gain = -38 dB
0 0 0 0 0 0 1 1 ADC input PGA gain = -39 dB
0 0 0 0 0 0 1 0 ADC input PGA gain = -40 dB
0 0 0 0 0 0 0 1 ADC input PGA gain = -41 dB
0 0 0 0 0 0 0 0 ADC input PGA gain = -42 dB
4.6 Control Register 5B
D7 D6 D5 D4 D3 D2 D1 D0
0 1 DAGAIN
R/W R/W R/W R/W R/W R/W R/W R/W
NOTE: R = Read, W = Write
Table 4–7. Control Register 5B Bit Summary
BIT NAME
D7-D6 Control
Register 5B
D5-D0 DAGAIN 101010 D/A converter gain (see T able 4–8)
NOTES: 7. In register read operation, first read receives ADC gain value, second read receives DAC gain value, third receives register 5C, and
fourth receives register 5D.
8. PGA default value = 101010b (0dB) for both ADC and DAC.
RESET
VALUE
NA
FUNCTION
Table 4–8. D/A PGA Gain
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 1 1 1 1 1 1 1 DAC input PGA gain = MUTE
0 1 1 1 1 1 1 0 DAC input PGA gain = 20 dB
0 1 1 1 1 1 0 1 DAC input PGA gain = 19 dB
0 1 1 1 1 1 0 0 DAC input PGA gain = 18 dB
0 1 1 1 1 0 1 1 DAC input PGA gain = 17 dB
0 1 1 1 1 0 1 0 DAC input PGA gain = 16 dB
0 1 1 1 1 0 0 1 DAC input PGA gain = 15 dB
0 1 1 1 1 0 0 0 DAC input PGA gain = 14 dB
4–5
Table 4–8. D/A PGA Gain (Continued)
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 1 1 1 0 1 1 1 DAC input PGA gain = 13 dB
0 1 1 1 0 1 1 0 DAC input PGA gain = 12 dB
0 1 1 1 0 1 0 1 DAC input PGA gain = 11 dB
0 1 1 1 0 1 0 0 DAC input PGA gain = 10 dB
0 1 1 1 0 0 1 1 DAC input PGA gain = 9 dB
0 1 1 1 0 0 1 0 DAC input PGA gain = 8 dB
0 1 1 1 0 0 0 1 DAC input PGA gain = 7 dB
0 1 1 1 0 0 0 0 DAC input PGA gain = 6 dB
0 1 1 0 1 1 1 1 DAC input PGA gain = 5 dB
0 1 1 0 1 1 1 0 DAC input PGA gain = 4 dB
0 1 1 0 1 1 0 1 DAC input PGA gain = 3 dB
0 1 1 0 1 1 0 0 DAC input PGA gain = 2 dB
0 1 1 0 1 0 1 1 DAC input PGA gain = 1 dB
0 1 1 0 1 0 1 0 DAC input PGA gain = 0 dB
0 1 1 0 1 0 0 1 DAC input PGA gain = -1 dB
0 1 1 0 1 0 0 0 DAC input PGA gain = -2 dB
0 1 1 0 0 1 1 1 DAC input PGA gain = -3 dB
0 1 1 0 0 1 1 0 DAC input PGA gain = -4 dB
0 1 1 0 0 1 0 1 DAC input PGA gain = -5 dB
0 1 1 0 0 1 0 0 DAC input PGA gain = -6 dB
0 1 1 0 0 0 1 1 DAC input PGA gain = -7 dB
0 1 1 0 0 0 1 0 DAC input PGA gain = -8 dB
0 1 1 0 0 0 0 1 DAC input PGA gain = -9 dB
0 1 1 0 0 0 0 0 DAC input PGA gain = -10 dB
0 1 0 1 1 1 1 1 DAC input PGA gain = -11 dB
0 1 0 1 1 1 1 0 DAC input PGA gain = -12 dB
0 1 0 1 1 1 0 1 DAC input PGA gain = -13 dB
0 1 0 1 1 1 0 0 DAC input PGA gain = -14 dB
0 1 0 1 1 0 1 1 DAC input PGA gain = -15 dB
0 1 0 1 1 0 1 0 DAC input PGA gain = -16 dB
0 1 0 1 1 0 0 1 DAC input PGA gain = -17 dB
0 1 0 1 1 0 0 0 DAC input PGA gain = -18 dB
0 1 0 1 0 1 1 1 DAC input PGA gain = -19 dB
0 1 0 1 0 1 1 0 DAC input PGA gain = -20 dB
0 1 0 1 0 1 0 1 DAC input PGA gain = -21 dB
0 1 0 1 0 1 0 0 DAC input PGA gain = -22 dB
0 1 0 1 0 0 1 1 DAC input PGA gain = -23dB
0 1 0 1 0 0 1 0 DAC input PGA gain = -24 dB
0 1 0 1 0 0 0 1 DAC input PGA gain = -25 dB
0 1 0 1 0 0 0 0 DAC input PGA gain = -26 dB
0 1 0 0 1 1 1 1 DAC input PGA gain = -27 dB
0 1 0 0 1 1 1 0 DAC input PGA gain = -28 dB
0 1 0 0 1 1 0 1 DAC input PGA gain = -29 dB
0 1 0 0 1 1 0 0 DAC input PGA gain = -30 dB
4–6
Table 4–8. D/A PGA Gain (Continued)
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 1 0 0 1 0 1 1 DAC input PGA gain = -31 dB
0 1 0 0 1 0 1 0 DAC input PGA gain = -32 dB
0 1 0 0 1 0 0 1 DAC input PGA gain = -33 dB
0 1 0 0 1 0 0 0 DAC input PGA gain = -34 dB
0 1 0 0 0 1 1 1 DAC input PGA gain = -35 dB
0 1 0 0 0 1 1 0 DAC input PGA gain = -36 dB
0 1 0 0 0 1 0 1 DAC input PGA gain = -37 dB
0 1 0 0 0 1 0 0 DAC input PGA gain = -38 dB
0 1 0 0 0 0 1 1 DAC input PGA gain = -39 dB
0 1 0 0 0 0 1 0 DAC input PGA gain = -40 dB
0 1 0 0 0 0 0 1 DAC input PGA gain = -41 dB
0 1 0 0 0 0 0 0 DAC input PGA gain = -42 dB
4.7 Control Register 5C
D7 D6 D5 D4 D3 D2 D1 D0
1
R/W R/W R/W R/W R/W R R/W R/W
NOTE: R = Read, W = Write
0 DSTG Reserved INBG
Table 4–9. Digital Sidetone Gain
D5 D4 D3 DSTG
1 1 1 Digital sidetone gain = Mute (Default)
1 1 0 Digital sidetone gain = -21 dB
1 0 1 Digital sidetone gain = -18 dB
1 0 0 Digital sidetone gain = -15 dB
0 1 1 Digital sidetone gain = -12 dB
0 1 0 Digital sidetone gain = -9 dB
0 0 1 Digital sidetone gain = -6 dB
0 0 0 Digital sidetone gain = -3 dB
Table 4–10. Input Buffer Gain
D1 D0 INBG
1 1 Input buf fer gain = 24 dB
1 0 Input buffer gain = 12 dB
0 1 Input buffer gain = 6 dB
0 0 Input buffer gain = 0 dB (Default)
4.8 Control Register 5D
D7 D6 D5 D4 D3 D2 D1 D0
1
R/WR/WRRRRRR
NOTE: R = Read, W = Write
1 Reserved Chip Version-ID
4–7
4.9 Control Register 6
D7 D6 D5 D4 D3 D2 D1 D0
PSDO
R/W R/W R/W R/W R/W R/W R/W R/W
NOTE: R = Read, W = Write
BIT NAME
D7–D5 Reserved
D4–D3 Reserved
D2–D1 AINSEL 00 Analog input select. These bits select the analog input for the ADC
D0 Reserved
MUTE2 MUTE3 ODRCT AINSEL Reserved
Table 4–11. Control Register 6 Bit Summary
RESET
VALUE
FUNCTION
AINSEL = 00 The analog input is INP/M1
AINSEL = 01 The analog input is MICIN self-biased at 1.35 V
AINSEL =10 The analog input is MICIN with external common mode
AINSEL = 11 The analog input is INP/M2
NOTE: For AINSEL = 10, the external common mode is connected to INM1 via an ac-coupled capacitor.
4–8
5 Electrical Characteristics
5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Supply voltage range: DVDD, AVDD (see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRVDD (see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, all digital output signals –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, all digital input signals –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range, T
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Case temperature for 10 seconds: Package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
5.2 Recommended Operating Conditions
Supply voltage for analog, AVDD 2.7 3.3 3.6 V
Supply voltage for analog output driver, DRVDD 2.7 3.6
Supply voltage for digital core, DVDD 1.65 1.8 1.95 V
Supply voltage for digital I/O, IOVDD 2.7 3.3 3.6 V
Analog single-ended peak-to-peak input voltage, V
Output load resistance, R
Analog output load capacitance, C
Digital output capacitance 20 pF
Master clock 100 MHz
ADC or DAC conversion rate 26 kHz
Operating free-air temperature, T
Between OUTP1 and OUTM1 (differential) 600 Ω
L
L
A
–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
I(analog)
MIN NOM MAX UNIT
2 V
20 pF
–40 85 °C
5–1
5.3 Electrical Characteristics Over Recommended Operating Free-Air Temperature
Range, AV
5.3.1 Digital Inputs and Outputs, fs = 8 kHz, Outputs Not Loaded
V
High-level output voltage, any digital output
OH
V
Low-level output voltage, any digital output
OL
I
High-level input current, any digital input 0.5 µA
IH
I
Low-level input current, any digital input 0.5 µA
IL
C
Input capacitance 3 pF
i
C
Output capacitance 5 pF
o
= 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V (Unless Otherwise Noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.8
IOVDD
0.1
IOVDD
V
V
5.4 ADC Path Digital Filter, fs = 8 kHz (see Note 2)
5.4.1 FIR Filter
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0 to 300 Hz –0.5 0.2
300 Hz to 3 kHz –0.5 0.25
Filter gain relative to gain at 1020 Hz
NOTE 2: Filter gain outside the passband is measured with respect to gain at 1020 Hz. The analog input test signal is a sinewave with
0 dB = 4 V
scales linearly with the sample rate.
as the reference level for the analog input signal. The bandpass is 0 to 3600 Hz for an 8-kHz sample rate. This bandpass
I(PP)
3.3 kHz –0.5 0.3
3.6 kHz
4 kHz –35
≥4.4 kHz –74
–3
dB
5.4.2 IIR Filter
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0 to 300 Hz –0.5 0.2
300 Hz to 3 kHz –0.5 0.25
Filter gain relative to gain at 1020 Hz
NOTE 2: Filter gain outside the passband is measured with respect to gain at 1020 Hz. The analog input test signal is a sinewave with
0 dB = 4 V
scales linearly with the sample rate.
as the reference level for the analog input signal. The bandpass is 0 to 3600 Hz for an 8-kHz sample rate. This bandpass
I(PP)
3.3 kHz –0.5 0.3
3.6 kHz
4 kHz –20
≥4.4 kHz –60
–3
dB
5–2
5.5 ADC Dynamic Performance, fs = 8 kHz
SNR
Signal to noise ratio (SNR)
dB
THD
Total harmonic distortion
dB
Signal to total harmonic distortion + noise (THD + N)
dB
5.5.1 ADC Signal-to-Noise (see Note 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI = –1 dB 82 88
SNR Signal-to-noise ratio (SNR)
NOTE 3: Test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output common mode is 1.35 V.
VI = –9 dB
VI = –40 dB 43 46
5.5.2 ADC Signal-to-Distortion (see Note 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI = –1 dB 85 90
THD Total harmonic distortion
NOTE 3: Test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output common mode is 1.35 V.
VI = –9 dB
VI = –40 dB 67 67
5.5.3 ADC Signal-to-Distortion + Noise (see Note 3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI = –1 dB 79 87
Signal-to-total harmonic distortion + noise (THD + N)
NOTE 3: Test condition is a 1020-Hz input signal with an 8-kHz conversion rate. Input and output common mode is 1.35 V.
VI = –9 dB
VI = –40 dB 42 48
79 82
82 88
73 79
dB
dB
dB
5.5.4 ADC Channel Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I(PP)
V
IO
I
B
E
G
E
O(ADC)
CMRR Common-mode rejection ratio at INMx and INPx VI = –100 mVpp at 1020 Hz 50 dB
ri
C
i
Single–ended input level Preamp gain = 6 dB 2 V
Input offset voltage
Input bias current
Common-mode voltage 1.35 V
Dynamic range VI = –1 dB 85 dB
Mute attenuation PGA = MUTE 80 dB
Intrachannel isolation 87 dB
Gain error VI = –1 dB at 1020 Hz 0.6 dB
ADC converter offset error ±10 mV
Idle channel noise V
Input resistance
Input capacitance
Channel delay
MICIN, INPx, INMx
INP,INM,MICIN
MICIN, INPx, INMx, TA = 25°C
IIR 5/f
FIR 17/f
= 0 V 50 100 µVrns
±10 mV
34 µA
30 kΩ
2 pF
s
s
s
s
5–3
5.6 DAC Path Digital Filter, fs = 8 kHz (see Note 4)
SNR
Signal to noise ratio (SNR)
dB
THD
Total harmonic distortion
Signal to total harmonic distortion + noise (THD + N)
dB
5.6.1 FIR Filter
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0 to 300 Hz –0.5 0.2
300 Hz to 3 kHz –0.25 0.25
Filter gain relative to gain at 1020 Hz
5.6.2 IIR Filter
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Filter gain relative to gain at 1020 Hz
NOTE 4: Filter gain outside of the bandpass is measured with respect to gain at 1020 Hz. The input signal is the digital equivalent of a sine wave
(digital full scale = 0 dB). The nominal differential DAC channel output with this input condition is 4 V
Hz for an 8-kHz sample rate. This pass band scales linearly with the conversion rate.
3.3 kHz –0.35 0.3
3.6 kHz
4 kHz –40
≥4.4 kHz –74
0 to 300 Hz –0.5 0.2
300 Hz to 3 kHz –0.25 0.25
3.3 kHz –0.35 0.3
3.6 kHz
4 kHz –20
≥4.4 kHz –60
. The pass band is 0 Hz to 3600
I(PP)
–3
–3
dB
dB
5.7 DAC Dynamic Performance
5.7.1 OUTP/OUTM Signal-to-Noise When Load Is 600 Ω (see Note 5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI = 0 dB 80 92
SNR Signal-to-noise ratio (SNR)
NOTE 5: Test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at the output of
the application schematic low-pass filter. The test is conducted in 16-bit mode.
VI = –9 dB
VI = –40 dB 40 51
5.7.2 OUTP/OUTM Signal-to-Distortion When Load Is 600 Ω (see Note 5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI = –0 dB 78 85
THD Total harmonic distortion
NOTE 5: Test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at the output of
the application schematic low-pass filter. The test is conducted in 16-bit mode.
VI = –9 dB
VI = –40 dB 59 62
5.7.3 OUTP/OUTM Signal-to-Distortion + Noise When Load Is 600 Ω (see Note 5)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VI = –0 dB 75 82
Signal-to-total harmonic distortion + noise (THD + N)
NOTE 5: Test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at the output of
the application schematic low-pass filter. The test is conducted in 16-bit mode.
VI = –9 dB
VI = –40 dB 34 44
75 83
74 83
70 77
dB
dB
5–4
5.7.4 DAC Channel Characteristics
Analog
mA
DD
y
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dynamic range VI = 0 dB at 1020 Hz 92 dB
Interchannel isolation 120 dB
E
Gain error, 0 dB VO = 0 dB at 1020 Hz 0.5 dB
G
Common mode voltage 1.35 V
Idle channel narrow band noise 0 kHz–4 kHz, See Note 6 80 125 Vrms
V
Output offset voltage at OUT (differential) DIN = All zeros 10 mV
OO
V
Analog output voltage, (3.3 V) OUTP 0.35 2.35 V
O
P
Maximum output power 600 Ω load at 3.3 V between OUTP1 and OUTM1 6.7 mW
O
IIR
Channel delay
FIR
NOTE 6: The conversion rate is 8 kHz.
5.8 BIAS Amplifier Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage 2.2 2.35 2.4 V
Integrated noise 300 Hz–13 kHz 20 µV
Offset voltage 10 mV
Current drive 10 mA
Unity gain bandwidth 1 MHz
DC gain 140 dB
5/f
18/f
s
s
s
5.9 Power-Supply Rejection (see Note 7)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD Supply-voltage rejection ratio, analog supply (f
DVDD Supply-voltage rejection ratio
NOTE 7: Power supply rejection measurements are made with both the ADC and DAC channels idle and a 200 mV peak-to-peak signal applied
to the appropriate supply.
= 0 to fs/2) at 1 kHz
(j)
DAC channel
ADC channel
Differential 75
Single-ended
f
= 0 kHz to 30 kHz
(j)
50
95
86
dB
dB
5.10 Power Supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
P
I
(t)
I
DD
D
Power dissipation 11.2 16.5 mW
Total current Power down
ADC 2
Analog
Supply current
Digital
DAC 1
Ref 0.4
All sections on 1.8
Coarse sampling 1
3.4 5 mA
0.01 mA
mA
mA
5–5
5.11 Timing Requirements (see Parameter Measurement Information)
TEST CONDITIONS MIN TYP MAX UNIT
t
t
t
t
t
t
t
t
t
t
t
wH
wL
su1
h1
d1
d2
d3
en
dis
su2
h2
Pulse duration, MCLK high 5
Pulse duration, MCLK low 5
Setup time, RESET, before MCLK high (see Figure 5–1) 3
Hold time, RESET, after MCLK high (see Figure 5–1) 2
Delay time, SCLK↑ to FS/FSD↓ CL = 20 pF 5 ns
Delay time, SCLK↑ to FS/FSD↑ 5
Delay time, SCLK↑ to DOUT 15
Enable time, SCLK↑ to DOUT 15
Disable time, SCLK↑ to DOUT 15
Setup time, DIN, before SCLK↓ 10
Hold time, DIN, after SCLK↓ 10
t
wH
SCLK
FS
FSD
DOUT
t
d1
t
en
MCLK
RESET
2.4 V
t
wL
2.4 V
t
su1
t
h1
Figure 5–1. Hardware Reset Timing
t
d3
D15
t
d2
t
t
d1
dis
2.4 V
t
d2
5–6
t
su2
DIN
t
h2
D15
Figure 5–2. Serial Communication Timing
NOTE: Above Figures are meant to show timing delays only.
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
–100
–120
Amplitude – dB
–140
–160
–180
0 500 1000 1500 2000 2500 3000 3500 4000
f – Frequency – Hz
ADC = 8 KSPS
Figure 5–3. FFT—ADC Channel (–3 dB Input)
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
–100
–120
Amplitude – dB
–140
–160
–180
0 2000 4000 6000 8000
f – Frequency – Hz
ADC = 16 KSPS
Figure 5–4. FFT—ADC Channel (–1 dB Input)
AMPLITUDE
vs
FREQUENCY
0
ADC = 16 KSPS
–40
–80
Amplitude – dB
–120
–160
0 2000 4000 6000 8000
f – Frequency – Hz
Figure 5–5. FFT—ADC Channel (–3 dB Input)
5–7
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
–100
Amplitude – dB
–120
–140
–160
0 2000 4000 6000 8000
f – Frequency – Hz
ADC = 16 KSPS
Figure 5–6. FFT—DAC Channel (–3 dB Input)
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
–100
–120
Amplitude – dB
–140
–160
–180
0 2000 4000 6000 8000
f – Frequency – Hz
DAC = 16 KSPS
5–8
Figure 5–7. FFT—DAC Channel (0 dB Input)
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
–100
Amplitude – dB
–120
–140
–160
0 1000 2000 3000 4000
f – Frequency – Hz
DAC = 8 KSPS
Figure 5–8. FFT—DAC Channel (–3 dB Input)
AMPLITUDE
vs
FREQUENCY
0
–20
–40
–60
–80
–100
–120
Amplitude – dB
–140
–160
–180
0 1000 2000 3000 4000
f – Frequency – Hz
DAC = 8 KSPS
Figure 5–9. FFT—DAC Channel (0 dB Input)
AMPLITUDE
vs
FREQUENCY
0
–20
–40
ADC = 8 KSPS
–60
–80
–100
Amplitude – dB
–120
–140
0 1000 2000 3000 4000
f – Frequency – Hz
Figure 5–10. FFT—ADC Channel (–1 dB Input)
5–9
FILTER GAIN
vs
FREQUENCY
5
5
FILTER GAIN
vs
FREQUENCY
0
–5
–10
–15
–20
Filter Gain – dB
–25
–30
–35
–40
0 500 1000 1500 2000 2500 3000 3500 4000 4500
f – Frequency – Hz
Figure 5–11. ADC FIR Frequency Response
FILTER GAIN
vs
FREQUENCY
20
0
–5
–10
–15
Filter Gain – dB
–20
–25
–30
0 500 1000 1500 2000 2500 3000 3500 4000 4500
f – Frequency – Hz
Figure 5–12. ADC IIR Frequency Response
FILTER GAIN
vs
FREQUENCY
20
5–10
0
–20
–40
–60
Filter Gain – dB
–80
–100
–120
0 1000 2000 3000 4000 5000 6000 7000 8000
f – Frequency – Hz
Figure 5–13. DAC IIR Frequency Response
(OSR = 512)
0
–20
–40
–60
Filter Gain – dB
–80
–100
–120
0 1000 2000 3000 4000 5000 6000 7000 8000
f – Frequency – Hz
Figure 5–14. DAC IIR Frequency Response
(OSR = 256)
20
0
–20
–40
FILTER GAIN
vs
FREQUENCY
0
20
0
–20
–40
–60
FILTER GAIN
vs
FREQUENCY
–60
Filter Gain – dB
–80
–100
–120
0 1000 2000 3000 4000 5000 6000 7000 8000
f – Frequency – Hz
Figure 5–15. DAC IIR Frequency Response
(OSR = 128)
FILTER GAIN
vs
FREQUENCY
20
0
–20
–80
Filter Gain – dB
–100
–120
–140
0 1000 2000 3000 4000 5000 6000 7000 800
f – Frequency – Hz
Figure 5–16. DAC FIR Frequency Response
(OSR = 512)
FILTER GAIN
vs
FREQUENCY
20
0
–20
–40
–60
–80
Filter Gain – dB
–100
–120
–140
0 1000 2000 3000 4000 5000 6000 7000 8000
f – Frequency – Hz
Figure 5–17. DAC FIR Frequency Response
(OSR = 256)
–40
–60
–80
Filter Gain – dB
–100
–120
–140
0 1000 2000 3000 4000 5000 6000 7000 8000
f – Frequency – Hz
Figure 5–18. DAC FIR Frequency Response
(OSR = 128)
5–11
Microphone
600 Ω
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
TLV320AIC14
BIAS
MICIN
INP1
INM1
INP2
INM2
OUTP1
OUTM1
M/S
FSD
DIN
DOUT
SCLK
MCLK
RESET
PWRDN
FS
IOVDD
IOVDD
1 kΩ
1 kΩ
From DSP or
Other Clock Source
From DSP
From DSP
TLV320C5X
FSK
FSR
DX
DR
CLKR
CLKX
IOVDD
1 kΩ
SDA
SCL
3.3 V Analog Supply
Analog GND
3.3 V Analog Supply
Analog GND
0.1 µF
0.1 µF
AVDD
AVSS
DRVDD
DRVSS
DVDD
DVSS
IOVDD
IOVSS
0.01 µF 0.1 µF 1 µF
0.01 µF 0.1 µF 1 µF
Figure 5–19. Single-Ended Microphone Input (Internal Common Mode)
I2C Master
S2C
To 1.8 V Digital Supply
To Digital GND
To 3.3 V Digital Supply
To Digital GND
5–12
IOVDD
IOVDD
Microphone
600 Ω
3.3 V Analog Supply
Analog GND
3.3 V Analog Supply
Analog GND
600 Ω
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
1 µF
1 µF
0.1 µF
0.1 µF
TLV320AIC14
BIAS
MICIN
INP1
INM1
INP2
INM2
OUTP1
OUTM1
AVDD
AVSS
DRVDD
DRVSS
M/S
FSD
FS
DIN
DOUT
SCLK
MCLK
RESET
PWRDN
SDA
SCL
DVDD
DVSS
IOVDD
IOVSS
1 kΩ
1 kΩ
From DSP or
Other Clock Source
From DSP
From DSP
From DSP
0.01 µF 0.1 µF 1 µF
0.01 µF 0.1 µF 1 µF
TLV320C5X
FSK
FSR
DX
DR
CLKR
CLKX
IOVDD
1 kΩ
To 1.8 V Digital Supply
To Digital GND
To 3.3 V Digital Supply
To Digital GND
Figure 5–20. Pseudo-Differential Microphone Input (External Common Mode)
5.12 Layout and Grounding Guidelines for TLV320AIC14
TLV320AIC14 has a built-in analog antialias filter, which provides rejection to external noise at high frequencies that
may couple into the device. Digital filters with high out-of-band attenuation also reject the external noise. If the
differential inputs are used for the ADC channel, then the noise in the common-mode signal is also rejected by the
high CMRR of TLV320AIC14. Using external common-mode for microphone inputs also helps reject the external
noise. However to extract the best performance from TLV320AIC14, care must be taken in board design and layout
to avoid coupling of external noise into the device.
TL V320AIC14 supports clock frequencies as high as 100 MHz. To avoid coupling of fast switching digital signals to
analog signals, the digital and analog sections should be separated on the board. In TLV320AIC14 the digital and
analog pins are kept separated to aid such a board layout. A separate analog ground plane should be used for the
analog section of the board. The analog and digital ground planes should be shorted at only one place as close to
TL V320AIC14 a s possible. No digital trace should run under TLV320AIC14 to avoid coupling of external digital noise
into the device. It is suggested to have the analog ground plane running below the TLV320AIC14. The power supplies
should be decoupled close to the supply pins, preferably, with 0.1 µF ceramic capacitor and 10 µF tantalum capacitor
following it. The ground pin should be connected to the ground plane as close as possible to the TLV320AIC14, so
as to minimize any inductance in the path. Since the MCLK is expected to be a very high frequency signal, it is
advisable to shield it with digital ground. For best performance of ADC in dif ferential input mode, the differential signals
should be routed close to each other in similar fashion, so that the noise coupling on both the signals is same and
can be rejected by the device.
5–13
Loading...