Texas Instruments TLV320AIC11IPFB, TLV320AIC11CPFB Datasheet

GeneralĆPurpose LowĆV oltage

1.1Vto3.6VI/O16ĆBit
22ĆKSPS DSP CODEC

TLV320AIC11

Data Manual

2000 AAP Data Converter Group

SLWS100

IMPORTANT NOTICE

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright  2000, Texas Instruments Incorporated

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Definitions and Terminology 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Register Functional Summary 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Device Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Operating Frequencies 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 ADC Signal Channel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 DAC Signal Channel 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 MIC Input 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 Antialiasing Filter 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 Sigma-Delta ADC 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 Decimation Filter 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 Sigma-Delta DAC 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.9 Interpolation Filter 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.10 Analog and Digital Loopback 2–5. . . . . . . . . . . . . . . . . . . . . . . . .

2.1.11 FIR Overflow Flag 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.12 Bypass Mode 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.13 Automatic Cascading Detection (ACD) 2–6. . . . . . . . . . . . . . . .

2.1.14 Low-Power Mode 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.15 Event-Monitor Mode 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Reset and Power-Down Functions 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Software and Hardware Reset 2–7. . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Software and Hardware Power Down 2–7. . . . . . . . . . . . . . . . . .

2.3 Clock Source 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Data Out (DOUT) 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Data Out, Master Mode 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 Data Out, Slave Mode 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Data In (DIN) 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 FC (Hardware Secondary Communication Request) 2–8. . . . . . . . . . . . .

2.7 Frame-Sync Function for TLV320AIC11 2–8. . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 Frame-Sync (FS) Function—Continuous-Transfer Mode

(Master Only) 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

2.7.2 Frame-Sync (FS) Function—Fast-Transfer Mode

(Slave Only) 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.3 Frame-Sync (FS) Function—Master Mode 2–11. . . . . . . . . . . . .

2.7.4 Frame-Sync (FS) Function—Slave Mode 2–11. . . . . . . . . . . . . .

2.7.5 Frame-Sync Delayed (FSD) Function, Cascade Mode 2–12. . .

2.8 Multiplexed Analog Input and Output 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.1 Multiplexed Analog Input 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.2 Analog Output 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.3 Single-Ended Analog Input 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.4 Single-Ended Analog Output 2–14. . . . . . . . . . . . . . . . . . . . . . . . .

3 Serial Communications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Primary Serial Communication 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Secondary Serial Communication 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Register Programming 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Hardware Secondary Serial Communication Request 3–4. . . .

3.2.3 Software Secondary Serial Communication Request 3–5. . . .

3.3 Direct Configuration Mode 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Continuous Data Transfer Mode 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 DIN and DOUT Data Format 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Primary Serial Communication DIN and

DOUT Data Format 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 Secondary Serial Communication DIN and

DOUT Data Format 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3 Direct Configuration DCSI Data Format 3–8. . . . . . . . . . . . . . . .

4 Specifications 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Absolute Maximum Ratings Over Operating Free-Air

Temperature Range 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Recommended Operating Conditions 4–1. . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Electrical Characteristics Over Recommended Operating

Free-Air Temperature Range 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Digital Inputs and Outputs, Fs = 8 kHz,

Output Not Loaded 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 ADC Path Filter, Fs = 8 kHz 4–2. . . . . . . . . . . . . . . . . . . . . . . . .

4.3.3 ADC Dynamic Performance, Fs = 8 kHz 4–2. . . . . . . . . . . . . . .

4.3.4 ADC Channel Characteristics 4–3. . . . . . . . . . . . . . . . . . . . . . . .

4.3.5 DAC Path Filter, Fs = 8 kHz 4–3. . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.6 DAC Dynamic Performance 4–3. . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.7 DAC Channel Characteristics 4–4. . . . . . . . . . . . . . . . . . . . . . . .

4.3.8 Op-Amp Interface (A1, A3, A4) 4–4. . . . . . . . . . . . . . . . . . . . . . .

4.3.9 Op-Amp Interface (A1, A3, A4) 4–4. . . . . . . . . . . . . . . . . . . . . . .

4.3.10 Power-Supply Rejection 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.11 Power Supply 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Timing Requirements 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 Master Mode Timing Requirements 4–5. . . . . . . . . . . . . . . . . . .

4.4.2 Slave Mode Timing Requirements 4–5. . . . . . . . . . . . . . . . . . . .

iv

5 Parameter Measurement Information 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Mechanical Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A—Register Set A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

2–1 Timing Sequence of ADC Channel (Primary Communication Only) 2–1. . . . . .

2–2 Timing Sequence of ADC Channel (Primary and

Secondary Communication) 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Timing Sequence of DAC Channel (Primary Communication Only) 2–3. . . . . .

2–4 Timing Sequence of DAC Channel (Primary and Secondary

Communication) 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Typical Microphone Interface 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Cascading 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Event Monitor Mode Timing 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Internal Power-Down Logic 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Timing Diagram for the FS Pulse Mode (M1M0 = 00) 2–9. . . . . . . . . . . . . . . . . .

2–10 Timing Diagram for the SPI_CP0 Mode (M1M0 = 01) 2–9. . . . . . . . . . . . . . . . .

2–11 Timing Diagram for the SPI_CP1 Mode (M1M0 = 10) 2–10. . . . . . . . . . . . . . . . .

2–12 Timing Diagram for the FS Frame Mode (M1M0 = 11) 2–10. . . . . . . . . . . . . . . .

2–13 Master Device Frame-Sync Signal With Primary and Secondary

Communication ( No Slaves) 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Master Device’s FS Output to DSP and FSD Output to the Slave 2–11. . . . . . .

2–15 Cascade Mode Connection (to DSP Interface) 2–12. . . . . . . . . . . . . . . . . . . . . . .

2–16 Master-Slave Frame-Sync Timing 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–17 INP and INM Internal Self-Biased Circuit (2.5 V for 5-V Operation

and 1.5 V for 3-V Operation) 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–18 Differential Output Drive (Ground-Referenced) 2–13. . . . . . . . . . . . . . . . . . . . . . .

2–19 Single-Ended Input 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–20 Single-Ended Output 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Primary Serial Communication Timing 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Hardware and Software Secondary Communication Request 3–2. . . . . . . . . . .

3–3 Device 3/Register 1 Read Operation Timing Diagram 3–3. . . . . . . . . . . . . . . . . .

3–4 Device 3/Register 1 Write Operation Timing Diagram 3–4. . . . . . . . . . . . . . . . . .

3–5 FS Output When Hardware Secondary Serial Communication

Is Requested Only Once (No Slave) 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Output When Hardware Secondary Serial Communication Is

Requested (Three Slaves) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 FS Output During Software Secondary Serial Communication Request

(No Slave) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

3–8 Direct Configuration 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Direct Configuration Mode Timing 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 Continuous Data Transfer Mode Timing 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 Primary Communication DIN and DOUT Data Format 3–8. . . . . . . . . . . . . . . .

3–12 Secondary Communication DIN and DOUT Data Format 3–8. . . . . . . . . . . . . .

3–13 Direct Communication DCSI Data Format 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 FS and FSD Timing 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Serial Communication Timing 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 FFT–ADC Channel, Fs = 8 kHz, Input = –3 dB 5–2. . . . . . . . . . . . . . . . . . . . . . . .

5–4 FFT–DAC Channel, Fs = 8 kHz, Input = –3 dB 5–2. . . . . . . . . . . . . . . . . . . . . . . .

5–5. FFT–ADC Channel, Fs = 8 kHz, Input = –1 dB 5–3. . . . . . . . . . . . . . . . . . . . . . .

5–6 FFT–DAC Channel, Fs = 8 kHz, Input = 0 dB 5–3. . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 Serial Interface Modes 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Least Significant Bit Control Function 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1 Introduction

The TL V320AIC1 1 provides high resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital
(A/D) using oversampling sigma-delta technology. It allows 2-to-1 MUX inputs with built-in antialiasing filter and
amplification for general-purpose applications such as telephone hybrid interface, electret microphone preamp, etc.
Both IN and AUX inputs accept normal analog signals. This device consists of a pair of 16-bit synchronous serial
conversion paths (one for each direction), and includes an interpolation filter before the DAC and a decimation filter
after the ADC. The FIR filters can be bypassed to offer flexibility and power savings. Other overhead functions
provided on-chip include timing (programmable sample rate, continuous data transfer, and FIR bypass) and control
(programmable-gain amplifier, communication protocol, etc.). The sigma-delta architecture produces high-resolution
analog-to-digital and digital-to-analog conversion at low system cost.

The TL V320AIC1 1 design enhances communication with the DSP. The continuous data transfer mode fully supports
TI’s DSP autobuffering (ABU) to reduce DSP interrupt service overhead. The automatic cascading detection (ACD)
makes cascade programming simple and supports a cascade operation of one master and up to seven slaves. The
direct-configuration mode for host interface uses a single-wire serial port to directly program internal registers without
interference from the data conversion serial port, or without resetting the entire device. The event monitor mode
allows the DSP to monitor external events like telephone’s ring and off-hook detection.

In the lower-power mode, the TLV320AIC11 converts data at a sampling rate of 8 KSPS consuming only 39 mW.
The programmable functions of this device are configured through a serial interface that can be gluelessly interfaced

to any DSP that accepts 4-wire serial communications, such as the TMS320UC54x. The options include software
reset, device power-down, separate control for ADC and DAC turnoff, communications protocol, signal-sampling
rate, gain control, and system-test modes, as outlined in Appendix A.

The TLV320AIC11 is particularly suitable for a variety of applications in hands-free car kits, VOIP, cable modem,
speech, and telephony area including low-bit rate, high-quality compression, speech enhancement, recognition, and
synthesis. Its low-group delay characteristic makes it suitable for single or multichannel active-control applications.

The wide range of low-voltage I/O (1.1 V–3.6 V) enables the AIC11 to interface with a single power supply, or with
dual power supplies for mixed low-voltage DSP systems such as the TMS320UC54x. This feature eliminates the
need for external level-shifting and reduces power consumption.

The TL V320AIC11 is characterized for commercial operation from 0°C to 70°C, and industrial operation from –40°C
to 85°C.

1.1 Features

• 16-bit oversampling sigma-delta A/D converter

• 16-bit oversampling sigma-delta D/A converter

• Maximum output conversion rate:

– 22 ksps with on-chip FIR filter
– 88 ksps with FIR bypassed

• Voiceband bandwidth in FIR-bypassed mode and final sampling rate at 8 ksps
– 90-dB SNR/ADC and 87-dB SNR/DAC with DSP’s FIR (FIR bypassed @ 88 ksps/5 V)
– 87-dB SNR/ADC and 85-dB SNR/DAC with DSP’s FIR (FIR bypassed @88 ksps/3.3 V)

• On-chip FIR produced 84-dB SNR for ADC and 85-dB SNR for DAC over 11-kHz BW

• Built-in functions including PGA, antialiasing analog filter, and op-amps for general-purpose interface (such

as MIC interface and hybrid interface)

1–1

• Glueless serial port interface to DSPs (TI TMS320UC54x or standard DSPs)

• Automatic cascading detection (ACD) makes cascade programming simple and allows up to 8 devices to

be connected in cascade.

• On-fly reconfiguration modes include secondary-communication mode and direct-configuration mode (host
interface).

• Continuous data-transfer mode for use with autobuffering (ABU) to reduce DSP interrupt service overhead

• Event-monitor mode provides external-event control, such as RING/OFF-HOOK detection

• Programmable ADC and DAC conversion rate

• Programmable input and output gain control

• Separate software control for ADC and DAC power-down

• Low-voltage (DV

• Analog (A V

• Digital (DV

DD1

DD2

) 1.1-V to 3.6-V digital I/O

DD1

and AV

) 3 V to 5.5 V core power supply

DD2

) 3 V to 5.5 V core power supply

• Power dissipation (PD) of 39 mW typical for 8-ksps at 3.3 V

• Hardware power-down mode to 0.2 mW

• Internal and external reference voltage (V

ref

)

• Differential and single-ended analog input/output

• 2s-complement data format

• Test mode, which includes digital loopback and analog loopback

• 600-ohm output driver

• VHDL code for serial interface available

1–2

1.2 Functional Block Diagram

Receiver or MIC Amp

AURXFP

AURXCP

AURXM

INP

INM

OUTP

OUTM

DTXOP

DTXIM

DTXIP

DTXOM

+

A1

–

VMID

@ 5 mA

Analog

Loopback

Transmitter Amp

–

A3

+

+

A4

–

MUX

1.5 V
or

2.5V

Anti-

Aliasing

Filter

PGA

PGA

Low
Pass
Filter

A2

Sigma-

Delta

ADC

Vref

Sigma-

Delta

DAC

Decimation Filter

Sync
Filter

ADREFP
ADREFM

DAREFP
DAREFM

Interpolation Filter

Sync
Filter

Internal Clock Circuit

FIR

Filter

FIR

Filter

Interface

Circuit

Div

256xN

Digital

Loopback

DOUT

DIN
M/S
FSD
FS

SCLK
FLAG
DCSI
ALTI

FC
M0
M1

MCLK

1–3

1.3 Terminal Assignments

T

I/O

DESCRIPTION

INM

INPAVAV

PFB PACKAGE

(TOP VIEW)

DD1

SS

NC

VMID

AV

SS

NC

SS

AV

NC

FILT

NC

AURXFP

AURXM

AURXCP

DTXOP

DTXOM

DTXIP

DTXIM

OUTP

OUTM

M0
M1

PWRDWN

NOTE: All NC pins should be left unconnected.

1.4 Ordering Information

A

0°C to 70°C TLV320AIC11C

–40°C to 85°C TLV320AIC11I

PACKAGE

48-TQFP PFB

47 46 45 44 4348 42

1
2
3
4
5
6
7
8
9
10
11
12

14 15

13

SS

DV

RESET

17 18 19 20

16

DD1

DOUT

DV

DIN

NC

SCLK

MCLK

40 39 3841

22 23 24

21

FSD

FS

37

FC

FLAG

36
35
34
33
32
31
30
29
28
27
26
25

NC
NC
AV

DD2

AV

SS

NC
NC
DV

DD2

DV

SS

NC
M/S
ALTIN
DCSI

1.5 Terminal Functions

TERMINAL

NAME NO.

ALTIN 26 I Serial input in the
AURXCP 3 I Receiver-path/GP amplifier noninverting input. It needs to be connected to AVSS if not used.
AURXM 2 I Receiver-path amplifier A1 inverting input, or inverting input to auxiliary analog input. It needs to be connected

AURXFP 1 I Receiver-path amplifier A1 feedback, or noninverting input to auxiliary analog input. It needs to be connected

AV

DD1

AV

DD2

AV

SS

DCSI 25 I Direct configuration serial input for directly programming of internal control registers
DIN 17 I Data input. DIN receives the DAC input data and register data from the external digital signal processor (DSP),

1–4

45
34

33, 40, 42,46I Analog ground

to AVSS if not used. It can also be used for general-purpose amplification.

to AVSS if not used. It can also be used for general-purpose amplification.

I Analog ADC power supply (3 V to 5.5 V)

and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low. DIN is at high
impedance when FS is not activated.

event monitor

mode

1.5 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

DOUT 16 O Data output. DOUT transmits the ADC output bits and registers data, and is synchronized to SCLK and FS.

DTXIM 7 I Transmitter-path amplifier A3 analog inverting input. It can also be used for general-purpose amplification.
DTXIP 6 I Transmitter-path amplifier A4 analog noninverting input. Can also be used for general-purpose

DTXOP 4 O Transmitter-path amplifier A3 feedback for positive output. It can also be used for general-purpose

DTXOM 5 O Transmitter path amplifier A4 feedback for negative output. It can also be used for general-purpose

DV

DD1

DV

DD2

DV

SS

FC 24 I Hardware request for secondary communication
FILT 38 O Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 2.5 V. The optimal

FLAG 23 O Controlled by bit D4 of control register 3. If D4=0 (default), the FLAG pin outputs the communication flag that

FS 22 I/O Frame sync. When FS goes low, DIN begins receiving data bits and DOUT begins transmitting data bits. In

FSD 21 O Frame-sync delayed output. The FSD output synchronizes a slave device to the frame sync of the master

INM 48 I Inverting input to analog modulator. INM requires an external R-C antialias filter with low output impedance if

INP 47 I Noninverting input to analog modulator. INP requires an external R-C antialias filter with low output

M0 10 I Combine with M1 to select serial interface mode (frame-sync mode)
M1 11 I Combine with M0 to select serial interface mode (frame-sync mode)
MCLK 20 I Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.
M/S 27 I Master/slave select input. When M/S is high, the device is the master, and when M/S is low, it is a slave.
NC 18, 28, 31,

OUTM 9 O DAC’s inverting output. OUTM is functionally identical with and complementary to OUTP.
OUTP 8 O DAC’s noninverting output. OUTP can also be used alone for single-ended operation.
PWRDWN 12 I Power down. When PWRDWN is pulled low, the device goes into a power-down mode, the serial interface is

RESET 13 I Reset. The reset function is provided to initialize all the internal registers to their default values. The serial

SCLK 19 I/O Shift clock. SCLK signal clocks serial data into DIN and out of DOUT during the frame-sync interval. When

VMID 43 O Reference voltage output at AVDD/2

15 I Dedicated 1.1-V to 3.6-V digital power supply for low-voltage I/O
30 I Dedicated 3-V to 5.5-V digital power supply for core CODEC

14, 29 I Digital ground

32, 35, 36,
37, 39, 41,

44

Data is sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when FS is not
activated.

amplification.

amplification.

amplification.

capacitor value is 0.1 µF (ceramic). This voltage node should be loaded only with a high-impedance dc load.

goes low/high to indicate primary-communication/secondary-communication interval, respectively. If D4=1,
the FLAG pin outputs the value of D3.

master mode, FS is internally generated and is low during data transmission to DIN and from DOUT . In slave
mode, FS is externally generated.

device. FSD is applied to the slave FS input and has the same duration as the master FS signal.

the internal antialias filter is bypassed.

impedance if the internal antialias filter is bypassed.

No connection

disabled, and most of the high-speed clocks are disabled. However, all register values are sustained and the
device resumes full-power operation without reinitialization when PWRDWN is pulled high again.
PWRDWN resets the counters only and preserves the programmed register contents. See paragraph 2.2.2
for more information.

port can be configured to the default state accordingly. See Appendix A,

Reset and Power-Down Functions

configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync signal
frequency by 256 (cascade devices < 5) or 512 (cascade devices > 4). When configured as an input (M/S
low), SCLK is generated externally and must be synchronous with the master clock and frame sync.

for detailed descriptions.

Register Set

, and Subsection 2.2.1,

1–5

1.6 Definitions and Terminology

Data transfer interval The time during which data is transferred from DOUT to DIN. The interval is 16 shift clocks

and the data transfer is initiated by the falling edge of the FS signal.

Signal data This refers to the input signal and all of the converted representations through the ADC

channel, and the signal through the DAC channel to the analog output. This is in contrast
with the purely-digital software control data.

Primary
communication

Secondary
communication

SPI Serial peripheral interface
Frame/pulse sync Frame/pulse sync refers only to the falling edge of the signal FS that initiates the data-

Frame/pulse sync and
sampling period

f

s

ADC channel ADC channel refers to all signal-processing circuits between the analog input and the

DAC channel DAC channel refers to all signal-processing circuits between the digital data word applied

Host A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK.
Dxx Bit position in the primary data word (xx is the bit number).
DSxx Bit position in the secondary data word (xx is the bit number).
d The alpha character

PGA Programmable gain amplifier
FIR Finite-duration impulse response
DCSI Direct configuration serial interface for host control

Primary communication refers to the digital data-transfer interval. Since the device is syn­chronous, the signal data words from the ADC channel and to the DAC channel occur si­multaneously .

Secondary communication refers to the digital control and configuration data-transfer in­terval into DIN, and the register read-data cycle from DOUT . The data transfer occurs when
requested by hardware or software.

transfer interval. The primary FS starts the primary communication, and the secondary FS
starts the secondary communication.

Frame/Pulse sync and sampling period is the time between falling edges of successive
primary FS signals and it is always equal to 256xSCLK if the number of cascading devices
is less than 5, or 512 xSCLK if the number of cascading devices is greater than 4.

The sampling frequency

digital conversion result at DOUT.

to DIN and the differential output analog signal available at OUTP and OUTM.

d

represents valid programmed or default data in the control-register

format (see Section 3.2,

Secondary Serial Communication

) when discussing other data bit

portions of the register.

1–6

1.7 Register Functional Summary

There are five control registers, which are used as follows:
Register 0 The no-op register . Addressing register 0 allows secondary-communication request without altering any

other registers.

Register 1 Control register 1. The data in this register has the following functions:

• Produce the output flag to indicate a decimator FIR filter overflow (read cycle only)

• Enable of general-purpose op-amps A1, A3, and A4

• Enable/bypass ADC’s analog antialiasing filter

• Select normal or auxiliary analog input

• Control 16-bit or (15+1)-bit mode of DAC operation

• Enable/bypass the decimator FIR filter

• Enable/bypass the interpolator FIR filter

Register 2 Control register 2. The data in this register has the following functions:

• Control of the low-power mode that converts data at the rate of 8 ksps

• Control of the N-divide register that determines the filter clock rate and sample period

Register 3 Control register 3. The data in this register has the following functions:

• Software reset and power down

• Selection of analog loopback, digital loopback, and event monitor mode

• Control of continuous data transfer mode

• Control of the value of one-bit general-purpose output flag

• Control the output of FLAG pin

• Enable/disable ADC path

• Enable/disable DAC path

• Control of 16-bit or (15+1)-bit mode of ADC operation

Register 4 Control register 4. The data in this register has the following functions:

• Control of the 4-bit gain of input amplifier

• Control of the 4-bit gain of output amplifier

1–7

1–8

2 Functional Description

2.1 Device Functions

2.1.1 Operating Frequencies

The sampling frequency represented by the frequency of the primary communication is derived from the master clock
(MCLK) input with the following equation:

Fs = Sampling (conversion) frequency = MCLK/(256 × N), N = 1, 2..., 32

The inverse of the sampling frequency is the time between the falling edges of two successive primary frame-sync
signals. This time is the conversion period. For example, to set the conversion rate to 8 kHz, MCLK = 256 × N × 8000.

NOTE: The value of N is defined in control register 2 and its power-up value is 32.

2.1.2 ADC Signal Channel

Both IN (INP, INM) and AUX (AURXFP, AURXM) inputs can use the built-in antialiasing filter that can be bypassed
by writing a 1 to bit D5 of control register 1. The AUX input can also be connected to the general-purpose amplifier
A1 for general-purpose applications, such as electret-microphone interface and 2-to-4-wire hybrid interface, by
writing a 1 to bit D6 of control register 1. Bit D4 of control register 1 selects between IN or AUX for the ADC. The
selected input signal is amplified by the PGA and applied to the ADC input. The ADC converts the signal into
discrete-output digital words in 2s-complement data format, corresponding to the analog-signal value at sampling
time. These 16-bit (or 15-bit) digital words, representing sampled values of the analog input signal after PGA, are
clocked out of the serial port (DOUT) at the positive edge of SCLK during the frame-sync (FS) interval at the rate of
one bit for each SCLK and one word for each primary communication. During secondary communication, the data
previously programmed into the registers can be read out. If a register read is not required, all 16 bits are cleared to
0 in the secondary communication. This read operation is accomplished by sending the appropriate register address
(D11-D9) with the read bit (D12) set to 1 during present secondary communication. The timing sequence is shown
in Figures 2–1 and 2–2.

The decimation FIR filter can be bypassed by writing a
be turned off for power savings by writing

0 1 15 16

SCLK

FS

DOUT

(16-bit)

DOUT

(15+1-bit)

NOTES: A. M/S is used to indicate whether the 15-bit data comes from a master or a slave device (master: M/S=1, slave: M/S=0).

B. The MSB (D15) is stable (the host can latch the data in at this time) at the falling edging of SCLK number 0; the last bit (D0,M/S)

is stable at the falling edging of SCLK number 15.

D15

MSB LSB

D15
MSB

01

to bits D2 and D1 of control register 3.

D14

D14

1

to bit D2 of control register 1. The whole ADC channel can

……

16 SCLKs

……
……

……

D1

LSB

D0

M/SD1

Figure 2–1. Timing Sequence of ADC Channel (Primary Communication Only)

2–1

Primary Secondary

Primary

16 SCLKs

FS

DOUT

(16-bit)

DOUT

(15+1-bit)

NOTES: A. M/S bit (D15) in the secondary communication is used to indicate whether the register data (address and content) come from a

master device or a slave device if read bit is set. Otherwise, it is all 0s except M/S bit (master: M/S=1, slave: M/S=0).

B. The number of SCLKs between FS (primary) and FS (secondary) is 128 if cascading devices are less than 5, or 256 if cascading

devices are greater than 4.

C. The number of SCLKs per data sampling period is 256 if cascading devices are less than 5, or 512 if cascading devices are greater

than 4.

16–bit ADC Data

15–bit ADC Data + M/S

# SCLKs (See Note B)

# SCLKs Per Sampling Period (See Note C)

16 SCLKs

M/S+ Register Data/

M/S+ All 0 (See Note A)

M/S+ Register Data/

M/S+ All 0 (See Note A)

Figure 2–2. Timing Sequence of ADC Channel (Primary and Secondary Communication)

2.1.3 DAC Signal Channel

DIN received the 16-bit serial data word (2s complement) from the host during the primary communication interval.
These 16-bit digital words, representing analog output signal before PGA, are clocked into the serial port (DIN) at
the falling edge of SCLK during the frame-sync interval, one bit for each SCLK and one word for each primary
communication interval. The data are converted to a pulse train by the sigma-delta DAC comprised of a
digital-interpolation filter and a digital 1-bit modulator. The output of the modulator is then passed to an internal
low-pass filter to complete the signal reconstruction. Finally, the resulting analog signal is applied to the input of a
programmable-gain amplifier is capable of differentially driving a 600-ohm load at OUTP and OUTM. The timing
sequence is shown in Figure 2–3.

During secondary communication, the digital control and configuration data, together with the register address, are
clocked in through DIN (see Appendix A for register map). These 16-bit data are used either to initialize the register
or read out register content through DOUT . If a register initialization is not required, a no-operation word (D15-D9 are
all set to 0) can be used. If D12 is set to 1, the content of the control register, specified by D7-D0, will be send out
through DOUT during the same secondary communication (see section 2.1.5). The timing sequence is shown in
Figure 2–4.

The interpolation FIR filter can be bypassed by writing a

1

to bit D1 of control register 1. The whole DAC channel can

be turned off for power savings by writing 10 to bits D2 and D1 of control register 3.

2–2

SCLK

0 1 15 16

14

……

16 SCLKs

FS

DIN

(16-bit)

DIN

(15+1-bit)

NOTE A: d0 = 0 means no secondary-communication request (software secondary-request control, see Section 3.2).

D15

MSB LSB

D15
MSB

D14

D14

……
……

……

D1

LSB

D0

D0=0D1

(see Note A)

Figure 2–3. Timing Sequence of DAC Channel (Primary Communication Only)

Primary Secondary

FS

DIN (16-bit)

(see Note A)

DIN

(15+1-bit)

16 SCLKs

16–bit DAC Data

15–bit DAC Data +

D0 = 1 (See Note B)

# SCLKs Between

FS (Primary) and

FS (Secondary)

(see Note C)

16 SCLKs

Register Read/Write

Register Read/Write

Primary

# SCLKs Between Sampling Period (See Note D)

NOTES: A. FC has to be set high for a secondary communication request when 16-bit DAC data format is used (see Section 3.2).

B. D0 = 1 means secondary communication request (software secondary request control, see Section 3.2)
C. The number of SCLKs between FS (Primary) and FS (Secondary) is 128 if cascading devices are less than 5, or 256 if cascading

devices are greater than 4.

D. The number of SCLKs per data sampling period is 256 if cascading devices are less than 5, or 512 if cascading devices are greater

than 4.

Figure 2–4. Timing Sequence of DAC Channel (Primary and Secondary Communication)

2–3