Texas Instruments TLC8188CDA Datasheet
TLC8188
10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR
SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Supports Both CIS and CCD Sensors
D
10-Bit, 4 MSPS, A/D Converter
D
Differential Nonlinearity Error: ±0.5 LSB Typ
D
Integral Nonlinearity Error: ±0.6 LSB Typ
D
8-Bit Offset Correction DAC
D
PGA With 6-Bit Gain Resolution
D
Auto-cycling Gain and Offset Control
D
Single 5-V Supply Operation
D
Very Low Power: 190 mW Typical
D
Control by Parallel and Serial Interface
D
Internal Reference Voltages
D
32-Pin TSSOP Package
description
The TLC8188 is a highly-integrated monolithic
analog signal processor/digitizer designed to
interface the contact image sensor (CIS) and linear charge-coupled device (CCD) image sensors in scanner
applications. The input of the TLC8188 allows direct connection to the CIS and direct ac coupling of the linear
CCD. The TLC8188 performs all the analog processing functions necessary to maximize the dynamic range,
correct various errors associated with the CIS and the linear CCD sensors, and then digitize the results with an
on-chip analog-to-digital converter (ADC). The key components of the TLC8188 include: input clamp circuitry
and a correlated double sampler (CDS), a programmable gain amplifier (PGA) with auto-cycling gain control, a
programmable offset correction controlled by a digital-to-analog converter (DAC), a 10-bit, 4 MSPS pipeline
ADC, a bidirectional parallel bus and a three-wire serial port for easy microprocessor interface, and internal
reference voltages.
Designed in advanced CMOS process, the TLC8188 operates from a single 5-V power supply and its digital
interface is 3 V compatible. The normal power consumption of the TLC8188 is just 190 mW.
Fully integrated analog processing circuitry , high throughput rate, single supply operation and low cost make the
TLC8188 an ideal CIS/linear CCD sensor interfacing solution for imaging applications such as scanners and
multifunctional office equipment (printer/scanner/facsimile/copier).
The device is available in a 32-pin TSSOP package and is specified over the 0°C to 70°C operating temperature
range.
AVAILABLE OPTIONS
PACKAGED DEVICE
T
A
SMALL OUTLINE
(DA)
0°C to 70°C TLC8188CDA
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OP0
OP1
OP2
OP3
OP4
DIV
DD
DIGND
OP5
OP6
OP7
OP8
OP9
DV
DD
DGND
ADCCLK
SCK/RNW
RPO
RMO
RIN
GIN
BIN
AV
DD
AGND
CLAMP
SR
SV
MA0/ACYC
MA1
OE
NRESET
SEN/STB
SDI/DNA
DA PACKAGE
(TOP VIEW)
TLC8188
10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR
SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
8-BIT
DAC
CLAMP
Control
Logic
MUX
RIN
MUX
GRN
OS
BLUE
OS
RED
OS
CDS
(S/H)
PGA
MUX
GRN
GAIN
BLUE
GAIN
RED
GAIN
10-BIT
ADC
THREE
STATE
LATCHES
ADCCLK
SV
MA0/ACYC
MA1
SR
NRESET
SDI/DNA
SCK/RNW
SEN/STB
SERIAL
PORT
8
6
INTERNAL
REFERENCE
OP (0 – 9)
OE
CLAMP RPO RMOAV
DD
DV
DD
DIV
DD
AGND DGND DIGND
GIN
BIN
TLC8188
10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR
SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
ADCCLK 15 I ADC conversion clock input.
AGND 26 Analog ground
AV
DD
27 Analog supply voltage, 5 V
BIN 28 I Blue channel input
CLAMP 25 I CCD input clamp signal, active high
DGND 14 Digital ground
DIGND 7 Digital interface circuit ground
DIV
DD
6 Digital interface circuit supply voltage, 3 V to 5 V
DV
DD
13 Digital supply voltage, 5 V
GIN 29 I Green channel input
MA1, MA0/ACYC 21, 22 I MA1 and MA0 select the color to which all internal MUX (input, gain, offset) will point. When in
auto-cycling mode, the input mux and internal registers are auto-cycled by the ACYC. The ACYC is a
control signal such as a line start pulse that defines the start of a current scanning line.
NRESET 19 I Power-on reset and Interface mode control. If SEN/STB is 1 when NRESET goes high then the device
is in parallel configuration data input mode. If SEN/STB is 0 when NRESET goes high then the device
is in serial data input mode.
OE
20 I Three-state output enable, active low
OP(0–4) 1 – 5 I/O Three-state bi-directional data bus, OP0 and OP1 are output only.
OP(5–9) 8 – 12 I/O Three-state bi-directional data bus.
RIN 30 I Red channel input
RMO 31 O Ref– output for external decoupling
RPO 32 O Ref+ output for external decoupling
SCK/RNW 16 I Serial interface: serial clock
Parallel interface: 1 – OP(9–2) is output bus, 0 – OP(9–2) is input bus
SDI/DNA 17 I Serial interface: serial interface input data
Parallel interface: 1 – data, 0 – address
SEN/STB 18 I Serial interface: serial data transfer enable, active high.
Parallel interface: strobe, active low.
SR 24 I CCD reset level sample pulse input
SV 23 I CCD signal level sample pulse input
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
–0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range –0.3 V to V
CC
+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage V
CC
+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range –0.3 V to V
CC
+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating
virtual junction temperature range, T
J
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TLC8188
10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR
SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
power supplies
MIN NOM MAX UNIT
Analog supply voltage, A V
DD
4.5 5.5 V
Digital supply voltage, DV
DD
4.5 5.5 V
Digital interface supply voltage, DIV
DD
2.7 5.5 V
digital inputs
MIN NOM MAX UNIT
High-level input voltage, V
IH
DIVDD = 3 V to 5.5 V 0.8DIV
DD
V
Low-level input voltage, V
IL
DIVDD = 3 V to 5.5 V 0.2DIV
DD
V
Input ADCCLK frequency 4 MHz
Input SCLK frequency 13.3 MHz
electrical characteristics over recommended operating free-air temperature range,
AV
DD
= DVDD = 5 V, ADCCLK = 4 MHz (unless otherwise noted)
total device
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
AVDD operating current 35 40 mA
p
1 mA
DIV
DD
operating current
5 pF loading, all outputs switching 2 mA
Device power consumption 190 mW
Device power consumption, power down mode 7 mW
analog-to-digital converter (ADC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 Bits
INL Integral nonlinearity ±0.6 ±2 LSB
DNL Differential nonlinearity ±0.5 ±1 LSB
No missing codes
Full-scale input voltage 4 V
PP
Input capacitance 15 pF
Conversion rate 4 MHz
ADC output latency 4
ADCCLK
cycles
correlated double sampler (CDS) and programmable gain amplifier (PGA)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CDS sample rate 4 MHz
Analog input voltage 4 V
Input capacitance 5 pF
PGA gain control resolution 6 Bits
PGA gain 1 5 V/V
PGA gain accuracy ±5%
PGA output settling time 125 ns
New gain settling time 125 ns
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