TEXAS INSTRUMENTS TLC5924, SLVS626 Technical data

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On/Off

Input
Shift

Register

DCInput

Shift

Register

7−bitDCRegister

Delay

x0

ConstantCurrent

Driver

LOD

MODE

0 1

MODE

0

1

0

15

111

0

On/OffRegister

0

6

0

0

01

Temperature

ErrorFlag

(TEF)

LEDOpen
Detection

(LOD)

7−bitDCRegister

Delay

x1

ConstantCurrent

Driver

LOD

On/OffRegister

7

13

1

1

7−bitDCRegister

Delay

x15

ConstantCurrent

Driver

LOD

On/OffRegister

105

111

15

15

BLANK

0

Max.OUTn

Current

GNDVCC SINSCLK

SOUT

IREF

XERR

XLA

T

MODE

OUT0

OUT1

OUT15

PGND

BLANK

BLANK

BLANK

16

16

112

1

VUP

VUP

VUP

VUP

16-CHANNEL LED DRIVER WITH DOT CORRECTION AND PRE-CHARGE FET

FEATURES APPLICATIONS

• 16 Channels

• Drive Capability

– 0 to 80 mA (Constant-Current Sink)

• Constant Current Accuracy: ±1% (typical)

• Serial Data Interface

• Fast Switching Output: Tr/ Tf= 10ns (typical)

• CMOS Level Input/Output

• 30 MHz Data Transfer Rate

• V

• Operating Temperature = –40 ° C to 85 ° C

• LED Supply Voltage up to 17 V

• 32-pin HTSSOP( PowerPAD™) and QFN

• Dot Correction

• Controlled In-Rush Current

• Pre-Charge FET

• Error Information

= 3.0 V to 5.5 V

CC

Packages

– 7 bit (128 Steps)
– individual adjustable for each channel

– LOD: LED Open Detection
– TEF: Thermal Error Flag

TLC5924

SLVS626 – JUNE 2006

• Monocolor, Multicolor, Fullcolor LED Display

• Monocolor, Multicolor LED Signboard

• Display Backlighting

• Multicolor LED lighting applications

DESCRIPTION

The TLC5924 is a 16 channel constant-current sink
driver. Each channel has a On/Off state and a
128-step adjustable constant current sink (dot
correction). The dot correction adjusts the brightness
variations between LED, LED channels and other
LED drivers. Both dot correction and On/Off state are
accessible via a serial data interface. A single
external resistor sets the maximum current of all 16
channels.

Each constant-current output has a pre-charge FET
that enables an improvement in image quality of the
dynamic-drive LED display.

The TLC5924 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an over-temperature
condition.

FUNCTIONAL BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2006, Texas Instruments Incorporated

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TLC5924

SLVS626 – JUNE 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

(1)

(1)

T

A

–40 ° C to 85 ° C

ORDERING INFORMATION

Package Part Number

32-pin, HTSSOP, PowerPAD™ TLC5924DAP

32-pin, 5 mm x 5 mm QFN TLC5924RHB

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com .

ABSOLUTE MAXIMUM RATINGS

(1) (2)

TLC5924 UNIT

V

Supply voltage

CC

V

Pre-charge voltage –0.3 to 16 V

UP

I

Output current (dc) I

O

V

Input voltage range

I

V

Output voltage range

O

ESD rating

T

Storage temperature range –40 to 150 °C

stg

Power dissipation rating at (or
above) TA= 25 ° C

(2)

to I

(2)

(2)

(OUT0)

V

(BLANK)

V

(SOUT)

V

(OUT0)

(OUT15)

, V

, V

, V

(XLAT)

(SCLK)

, V

(XERR)

to V

(OUT15)

, V

(SIN)

, V

(MODE)

(IREF)

–0.3 to 6 V

90 mA
–0.3 to V
–0.3 to V

-0.3 to V

+ 0.3 V

CC

+ 0.3 V

CC

UP

HBM (JEDEC JESD22-A114, Human Body Model) 2 kV
CDM (JEDEC JESD22-C101, Charged Device Model) 500 V

HTSSOP (DAP) 42.54 mW/ ° C

(3)

QFN (RHB) 27.86 mW/ ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) See SLMA002 for more information about PowerPAD™

V

RECOMMENDED OPERATING CONDITIONS—DC Characteristics

V

Supply voltage 3 5.5 V

CC

V

Pre-charge voltage 3 15 V

UP

V

Voltage applied to output, (Out0 - Out15) V

O

V

High-level input voltage 0.8 VCC VCC V

IH

V

Low-level input voltage GND 0.2 VCC V

IL

I

High-level output current V

OH

I

Low-level output current V

OL

I

Constant output current OUT0 to OUT15 80 mA

OLC

T

Operating free-air temperature range -40 85 ° C

A

2

= 5 V at SOUT –1 mA

CC

= 5 V at SOUT, XERR 1 mA

CC

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MIN NOM MAX UNIT

V

UP

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TLC5924

SLVS626 – JUNE 2006

RECOMMENDED OPERATING CONDITIONS—AC Characteristics

V

= 3 V to 5.5 V, TA= -40°C to 85°C (unless otherwise noted)

CC

MIN TYP MAX UNIT

f

SCLK

t

wh0

t

wh1

t

su0

t

su1

t

su1a

t

su2

t

su3

t

h0

t

h1

t

h1a

t

h2

t

h3

(1) " ↑ " and " ↓ " indicates a rising edge, and a falling edge respectively.

ELECTRICAL CHARACTERISTICS

V

CC

V

OH

V

OL

I

I

I

CC

I

OLC

I

LO0

I

LO1

∆ I
∆ I

∆ I

∆ I

R

(ON)

T

(TEF)

V

(LOD)

V

(IREF)

(1) Measured at device start-up temperature. Once the IC is operating (self heating), lower ICCvalues will be seen. See Figure 20 .
(2) Not tested. Specified by design.

Clock frequency SCLK 30 MHz

, t

CLK pulse duration SCLK=H/L 16 ns

wl0

XLAT pulse duration XLAT=H 20 ns

SIN to SCLK ↑

(1)

10

SLCK ↑ to XLAT ↓ (dot correction data) 10

Setup time SCLK ↑ to XLAT ↑ (ON/OFF data) 10 ns

MODE ↑ ↓ to SCLK ↑ 10
MODE ↑ ↓ to XLAT ↑ 10
SCLK ↑ to SIN 10
XLAT ↓ to SCLK ↑ (dot correction data) 10

Hold time XLAT ↑ to SCLK ↑ (ON/OFF data) 10 ns

SCLK ↑to MODE ↑ ↓ 10
XLAT ↓ to MODE ↑ ↓ 10

= 3 V to 5.5 V, TA= –40 ° C to 85 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage IOH= –1 mA, SOUT VCC– 0.5 V
Low-level output voltage IOL= 1 mA, SOUT 0.5 V
Input current VI= V

No data transfer, All output OFF, VO= 1 V, R
k Ω

No data transfer, All output OFF, VO= 1 V, R

Supply current mA

k Ω
Data transfer 30 MHz, All output ON, VO= 1 V,

R
Data transfer 30 MHz, All output ON, VO= 1 V,

R

Constant sink current All output ON, VO= 1 V, R

All output OFF, VO= 15 V, R

Leakage output current

OUT15
V

Constant sink current error All output ON, VO= 1 V, R

OLC0

Constant sink current error ± 4% ± 8.5%

OLC1

Line regulation ± 1 ± 4 %/V

OLC2

Load regulation ± 2 ± 6 %/V

OLC3

device to device, averaged current from OUT0 to OUT15,
R

All output ON, VO= 1 V, R
OUT0 to OUT15, V

All output ON, VO= 1 V to 3 V, R

OUT0 to OUT15
Pre-charge FET on-resistance V
Thermal error flag threshold Junction temperature, rising temperature
LED open detection threshold 0.3 0.4 V
Reference voltage output R

or GND, BLANK, XLAT, SCLK, SIN, MODE –1 1 µ A

CC

= 10

(IREF)

= 1.3

(IREF)

= 1.3 k Ω

(IREF)

= 600 Ω

(IREF)

= 600 Ω 70 80 90 mA

(IREF)

= 600 Ω , OUT0 to

(IREF)

= 5.5 V, No TEF and LOD 10 µ A

XERR

= 600 Ω , OUT0 to OUT15 ± 1% ± 4%

(IREF)

= 600 Ω

(IREF)

= 600 Ω ,

(IREF)

= 3 V to 5.5 V

CC

= 600 Ω ,

(IREF)

= 3 V, VO= 0 V, OUT0 to OUT15 10 K Ω

UP

= 600 Ω 1.20 1.24 1.28 V

(IREF)

(2)

36 65

150 160 180 ° C

15

32

(1)

0.1 µ A

6

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1
2
3

4
5
6
7
8
9

10
11
12
13
14
15
16

32
31
30

29
28
27
26
25
24

23
22
21
20
19
18
17

GND

BLANK

XLAT

SCLK

SIN

VUP
OUT0
OUT1

PGND

OUT2
OUT3
OUT4
OUT5

PGND

OUT6
OUT7

VCC
IREF
MODE
XERR
SOUT
VUP
OUT15
OUT14
PGND
OUT13
OUT12
OUT11
OUT10
PGND
OUT9
OUT8

THERMAL

PAD

SOUT24VUP23OUT1522OUT1421PGND20OUT1319OUT1218OUT1

1

17

OUT1016

PGND15

OUT914

OUT813

OUT712

OUT611

PGND10

OUT59

OUT4

8

OUT3

7

OUT2

6

PGND

5

OUT1

4

OUT0

3

VUP

2

SIN

1

XERR 25

MODE 26

IREF 27

VCC 28

GND 29

BLANK 30

XLAT 31

SCLK 32

RHBPACKAGE

(TOPVIEW)

(QFN)

DAPPACKAGE

(TOPVIEW)

TLC5924

SLVS626 – JUNE 2006

DISSIPATION RATINGS

PACKAGE

32-pin HTSSOP with PowerPAD

soldered

32-pin HTSSOP with PowerPAD

unsoldered

32-pin QFN 3482 mW 27.86 mW/ ° C 2228 mW 1811 mW

(1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information.

(1)

(1)

SWITCHING CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

r0

Rise time ns

t

r1

t

f0

Fall time ns

t

f1

t

pd0

t

pd1

t

pd2

Propagation delay time ns

t

pd3

t

pd4

t

pd5

t

Output delay time OUTn ↑ to OUT(n+1) ↑ , OUTn ↓ to OUT(n+1) ↓ (see

d

POWER RATING DERATING FACTOR POWER RATING POWER RATING

TA< 25 ° C ABOVE TA = 25 ° C TA= 70 ° C TA= 85 ° C

5318 mW 42.54 mW/ ° C 3403 mW 2765 mW

2820 mW 22.56 mW/ ° C 1805 mW 1466 mW

SOUT(see
OUTn, V
SOUT (see
OUTn, V
SCLK ↑ to SOUT ↑ ↓ (see
MODE ↑↓ to SOUT ↑ ↓ (see
BLANK ↑ ↓ to OUT0 ↑ ↓ (see
XLAT ↑ to OUT0 ↑ ↓ (see
OUTn ↑ ↓ to XERR ↑ ↓ (see
XLAT ↑ to I

(1)

) 16

= 5 V, TA= 60 ° C, DCx = 7F (see

CC

(1)

) 16

= 5 V, TA= 60 ° C, DCx = 7F (see

CC

OUT

(dot-correction) (see

(3) (4)

) 30

(3)

) 30

(5)

), Sink current On/Off 80

(5)

) 60

(6)

) 1000

(7)

) 1000

(2)

) 10 30

(2)

) 10 30

(5)

) 14 22 30 ns

(1) See Figure 4 . Defined as from 10% to 90%
(2) See Figure 5 . Defined as from 10% to 90%
(3) See Figure 4 , Figure 16
(4) " ↑ " and " ↓ " indicates a rising edge, and a falling edge respectively.
(5) See Figure 5 and Figure 16
(6) See Figure 5 , Figure 6 , and Figure 16
(7) See Figure 5

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Terminal Functions

TERMINAL

NAME

BLANK 2 30 I
GND 1 29 Ground

IREF 31 27 I/O Reference current terminal
MODE 30 26 I
OUT0 7 3 O Constant current output

OUT1 8 4 O Constant current output
OUT2 10 6 O Constant current output
OUT3 11 7 O Constant current output
OUT4 12 8 O Constant current output
OUT5 13 9 O Constant current output
OUT6 15 11 O Constant current output
OUT7 16 12 O Constant current output
OUT8 17 13 O Constant current output
OUT9 18 14 O Constant current output
OUT10 20 16 O Constant current output
OUT11 21 17 O Constant current output
OUT12 22 18 O Constant current output
OUT13 23 19 O Constant current output
OUT14 25 21 O Constant current output
OUT15 26 22 O Constant current output

PGND Power ground
VUP 6, 27 2, 23 Pre-charge power supply voltage
SCLK 4 32 I
SIN 5 1 I Data input of serial I/F

SOUT 28 24 O Data output of serial I/F
VCC 32 28 Power supply voltage

XERR 29 25 O

XLAT 3 31 I

TSSOP QFN

NO. I/O DESCRIPTION

Blank (Light OFF). When BLANK=H, All OUTn outputs are forced to VUP level. When
BLANK=L, ON/OFF of OUTn outputs are controlled by input data.

Mode select. When MODE=L, SIN, SOUT, SCLK, XLAT are connected to ON/OFF control
logic. When MODE=H, SIN, SOUT, SCLK, XLAT are connected to dot-correction logic.

9, 14, 5, 10,

19, 24 15, 20

Data shift clock. Note that the internal connections are switched by MODE (pin #30). At
SCLK ↑ , the shift-registers selected by MODE shift the data.

Error output. XERR is open drain terminal. XERR transistions from H to L when LOD or TEF
detected.

Data latch signal. When MODE = L (ON/OFF data mode), XLAT is an edge-triggered latch
signal of ON/OFF registers. The serial data in ON/OFF input shift registers is latched into the
ON/OFF registers at the rising edge of XLAT. When MODE = H (DC data mode), XLAT is a
level-triggered latch signal of dot correction registers. The serial data in DC input shift
registers is written into dot correction registers when XLAT = H. The data in dot correction
registers is held constant when XLAT = L.

TLC5924

SLVS626 – JUNE 2006

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VCC

INPUT

GND

400 W

SOUT

GND

10 W

XERR

GND

20 W

SOUT

15 pF

OUTn

VUP

51 Ω

15pF

TLC5924

SLVS626 – JUNE 2006

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

(Note: Resistor values are equivalent resistance and not tested).

Figure 1. Input Equivalent Circuit (BLANK, XLAT, SCLK, SIN, MODE)

Figure 2. Output Equivalent Circuit

Figure 3. Output Equivalent Circuit (XERR)

PARAMETER MEASUREMENT INFORMATION

Figure 4. Test Circuit for tr0, tf0, t

Figure 5. Test Circuit for tr1, tf1, t

, t

pd0

pd1

, t

, t

pd2

pd3

, t

pd5

td

6

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XERR

470 kΩ

PARAMETER MEASUREMENT INFORMATION (continued)

TLC5924

SLVS626 – JUNE 2006

Figure 6. Test Circuit for t

pd4

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I

MAX

+

V

IREF

R

IREF

40

I

Outn

+

I

MAX

DC

n

127

DC15.0

105

DC15.6

111

DC14.6

104

MSB

DCOUT15

DC0.0

0

DC1.07DC0.6

6

LSB

DCOUT0

DCOUT14 − DCOUT1

TLC5924

SLVS626 – JUNE 2006

PRINCIPLES OF OPERATION

Setting Maximum Channel Current

The maximum output current per channel is set by a single external resistor, R
IREF and GND. The voltage on IREF is set by an internal band gap V
maximum channel current is equivalent to the current flowing through R

with a typical value of 1.24V. The

(IREF)

(IREF)

maximum output current per channel can be calculated by Equation 1 :

where:
V

= 1.24V typ.

IREF

R

= User selected external resistor ®

IREF

Figure 17 shows the maximum output current, I

resistor between IREF terminal to ground, and I

should not be smaller than 600 Ω)

IREF

, versus R

OLC

is the constant output current of OUT0,.....OUT15. A variable

OLC

(IREF)

. In Figure 17 , R

power supply may be connected to the IREF pin through a resistor to change the maximum output current per
channel. The maximum output per channel is 40 times the current flowing out of the IREF pin. The maximum
current from IREF equals 1.24V/600 Ω .

, which is placed between

(IREF)

multiplied by a factor of 40. The

is the value of the

(IREF)

(1)

Setting Dot-Correction

The TLC5924 has the capability to fine adjust the current of each channel, OUT0 to OUT15 independently. This
is also called dot correction. This feature is used to adjust the brightness deviations of LED connected to the
output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 7-bit word. The channel
output can be adjusted in 128 steps from 0% to 100% of the maximum output current I
channels must be entered at the same time. Equation 2 determines the output current for each OUTn:

where:
I

= the maximum programmable current of each output

Max

DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127)
n = 0, 1, 2 ... 15
Dot correction data are entered for all channels at the same time. The complete dot correction data format

consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 7 shows the DC data format. The DC15.6 in Figure 7 stands
for the 6thmost significant bit for output 15.

. Dot correction for all

MAX

(2)

Figure 7. DC Data Format

To input data into dot correction register, MODE must be set to high. The internal input shift register is then set
to 112-bit width. After all serial data is clocked in, a high level pulse of XLAT signal connects the serial data to
the dot correction register. The dot correction registers are level-triggered latches of XLAT signal. The serial
data is latched into the dot correction registers when XLAT goes low. The data in dot correction registers is held
constant when XLAT is low. BLANK signal does not need to be high to latch in new data. Since XLAT is a
level-triggered signal when MODE is high, SCLK and SIN must not be changed while XLAT is high. (Figure 16 ).

8

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