Texas Instruments TLC5902PZP Datasheet

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

80 mA × 16 Bits and 120 mA × 8 Bits
Drive Capability and Output Counts

D

5 mA to 80 mA/10 mA to 120 mA Constant
Current Output Range

D

Constant Currency Accuracy of ±4%
(Maximum Error Between Bits)

D

Constant Current Output Terminals
– 0.4 V (Output Current 0 to 40 mA)
– 0.7 V (Output Current 40 to 80 mA)

D

256 Gray Scale Display With Pulse Width
Control 256 Steps

D

Brightness Adjustment
– Output Current Adjustment for 32 Steps

(Adjustment for Brightness Deviation
Between LEDs)

– 8 Steps Brightness Control by 8 Times

Speed Gray Scale Control Clock
(Brightness Adjustment for Panel)

D

Protection
– WDT Function
– TSD Function

D

Clock Synchronized 8-Bit Parallel Input

D

Anode Common LED Type Applied

D

CMOS Input Signal Level
(Schmitt-Triggered Input for All Input
Terminals)

D

4.5 V to 5.5 V Power Supply Voltage

D

15 V Maximum Output Voltage

D

15 MHz Maximum Data Transfer Rate

D

4 MHz Maximum Gray Scale Clock
Frequency

D

–20°C to 85°C Operating Free-Air
T emperature Range

D

100-Pin HTQFP Package
(PD = 4.7 W, T

A

= 25°C)

description

The TLC5902 is a constant current driver that incorporates shift register, data latch, and constant current
circuitry with a current value adjustable and 256 gray-scale display that uses pulse width control. The output
current can be selected as maximum 80 mA with 16 bits or 120 mA with 8 bits. The current value of the constant
current output is set by one external resister. After this device is mounted on a printed-circuit board (PCB), the
brightness deviation between LEDs (ICs) can be adjusted using an external data input, and the brightness
control for the panel can be adjusted using the brightness adjustment circuitry. Moreover, the device
incorporates watchdog timer (WDT) circuitry , which turns the constant current output off when the scan signal
is stopped during dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns constant
current output off when the junction temperature exceeds the limit.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

NC
DOUT5
DOUT6

NC
NC

GNDANA
WD_CAP
PV
IREF
OUT15
TEST2
NC
GNDLED

NC
OUT14

NC
NC
GNDLED
NC
NC
OUT12

DIN4
DIN6

DIN7

TS_ENA

VCCLOG

NC

MODE

GNDLOG

NC

OUT0

NC

GNDLED

NC

NC
OUT1
OUT2

NC

GNDLED

NC

NC
OUT3

NCNCDIN3

DIN1

DIN0

GSCLK

BLANK

NC

NC

DOWNNCNC

BOUT

GSOUT

DOUT0

DOUT1

DOUT2

DOUT3

DOUT4

NC

NC

OUT4

NC

GNDLED

OUT5

NC

GNDLED

OUT7

NC

GNDLED

NC

OUT10

NC

NCNCNC

NC

OUT9

HTQFP PACKAGE

(TOP VIEW)

DIN5

TEST1

WDT

RSEL

DCLK

VCCANA

OUT13

OUT6

GNDLED

NC

NC

OUT8

OUT11

NC

DOUT7

LA TCH

ENABLE

DIN2

BC_ENA

NC

CC

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

TSD

DOUT0

DOUT7

BC_ENA

RSEL

DIN0

DIN7

DCLK

MODE

GSCLK

BLANK

TS_ENA

WDT

WD_CAP

IREF

GSOUT

BOUT

DOWN

DCLK

Controller

OUT0 OUT15

WDT

Shift Register and Data Latch

Brightness Control

Register

16 × 8 Bits

Shift Register

Data Latch

8 Bits

Gray Scale

Counter

16 × 8 Bits

Comparator

LATCH

ENABLE

16 Bits

Constant Current Driver

Current Reference

Circuit

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram for shift register and data latch

Comparator

DCLK

Controller

Comparator

DOUT(0–7)

BC_ENA

RSEL

DIN(0–7)

DCLK

MODE

Q7 Q15Q0

Q0

Q15

1 × 8 Bits Shift Register

(Brightness Control)

1 × 8 Bits Latch

(Brightness Control)

To
8 Bits Gray Scale Counter
Current Reference
Circuitry

16 × 8 Bits

Shift Register

(Gray Scale Data))

16 × 8 Bits
Data Latch

(Gray Scale Data))

LATCH

ENABLE

Comparator

Constant Current Driver

Control Line
Data (8 Bits)

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent input and output schematic diagrams

VCCLOG

Input

INPUT

GNDLOG

VCCLOG

OUTPUT

GNDLOG

GNDLOG

OUTn

GNDLED

OUTn

DOUT (0–7), GSOUT, BOUT

DOWN

DOWN

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

BC_ENA 85 I

Brightness control enable. When BC_ENA is low, the brightness control function is disabled. At
this time, the brightness control latch is reset to 1Fh. Output current value is 100% of setting value
by an external resistor and the frequency division ratio of GSCLK is 1/1.

BLANK 68 I

Blank (Light off). When BLANK is high, all the output of the constant current driver is turned off.
All the output is turned on (LED on) synchronizing to the falling edge of GCLK after next rising edge

of GCLK when BLANK goes from high to low.
BOUT 57 O Blank signal delay. BOUT is output with the addition of delay time to BLANK.
CONDUCTIVE

PAD

package

surface

Heat sink pad

DCLK 65 I

Clock input for data transfer. The input data of DIN is synchronized to the rising edge of DCLK, and

transferred to DOUT. DCLK is valid at the rising edge after ENABLE goes low.
DIN7–DIN0

70,71,72,73,
76,77,78,79

I Input for shift register for both gray scale data and brightness control. It is 8 bits parallel data.

DOUT7–DOUT0

47,48,49,51,
52,53,54,55

O Output for shift register for both gray scale data and brightness control.

DOWN 60 O

Shutdown. DOWN is configured as an open collector. It goes low when the constant current output

is shut down by the WDT or TSD function.
ENABLE 64 I Data transfer enable. When ENABLE is high, data is not transferred.
GNDANA 43 Analog ground. (Internally connected to GNDLOG and GNDLED)

GNDLED

5,10,15,20,29,

36,90,96

LED driver ground (Internally connected to GNDANA and GNDLOG)
GNDLOG 84 Logic ground. (Internally connected to GNDANA and GNDLED)
GSCLK 69 I

Clock input for gray scale. The gray scale display is accomplished by lighting the LED until the

number of GSCLK counted is equal to the data latched.
GSOUT 56 O Clock delay for gray scale. GSOUT is output with addition of delay time to GSCLK

IREF 40 I

Constant current control setting. LED current is set to the desired value by connecting an external

resistor between IREF and GND. The 38 times current is compared to current across external

resistor sink on output terminal.

LATCH 61 I

Latch. When LATCH is high, data on shift register goes through the latch. When LA TCH is low, data

is latched. Accordingly, if data on the shift register is changed during LATCH high, this new value

is latched.
MODE 83 I

8/16 bits select. When the MODE is high, the 16 bits output is selected. When the MODE is low,

the 8 bits output is selected.

OUT0–OUT15

87,93,94,100,

3,7,8,12,13,17,

18,22,26,32,

33,39

O Constant current output

PV

CC

41 LED driver power supply voltage

RSEL 66 I

Shift register latch switching. When RSEL is low, the shift register and latch for gray scale are

selected. When RSEL is high, the shift register and latch for brightness control are selected.
TEST1, TEST2 88,38 I TEST. Factory test terminal. TEST should be connected to GND for normal operation.

TS_ENA 80 I

TSD (Thermal shutdown) enable. When TS_ENA is high, TSD is enabled. When TS_ENA is low,

TSD is disabled.
VCCANA 45 Analog power supply voltage
VCCLOG 81 Logic power supply voltage

WD_CAP 42 I

WDT detection time adjustment. The capacitor for WDT detection time adjustment is connected

between WD_CAP and GND. When WD_CAP is directly connected to GND, the WDT function

is disabled.

WD 62 I

WDT scan input. By applying a scan signal to this terminal, the scan signal can be monitored and

constant current output can be turned off. LED is protected from damage from burning when the

scan signal is stopped during the constant period. The scan signal should be applied to this

terminal by connecting W_CAP to GND even though no WDT function is used.

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables

Truth Table (Data)

BC_ENA

ENABLE DCLK RSEL LATCH MODE DOUT0 – DOUT7 OPERATION/FUNCTION

L X X X X X No change Data latch for brightness control is set to 1Fh.
X H X X X X No change

Data transfer for gray scale and brightness
control does not occur.

X L ↑ H X X

Shift register for
brightness control

Data of DIN0 to DIN7 is clocked into the shift
register for brightness control.

X L ↑ L X H

Data for shift register
before 16 bytes (written
before 16 times)

Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.

X L ↑ L X L

Shift register for gray
scale before 8 bytes
(written before 8 times)

Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.

H X X H H X No change

Shift register for brightness control goes through
data latch for brightness control.

X X X L H X No change

Shift register for gray scale goes through data
latch for gray scale.

H X X X L X No change

The value for the shift register selected by RSEL
is latched.

Truth Table (Display/Protection)

BLANK

GSCLK MODE WDT WD_CAP TS_ENA OUT0~15 DOWN

OPERATION/

FUNCTION

H X X X X X Off Hi–Z

L ↓ H X X X

16 bits operation mode. The output is turned on if
all the gray scale data is not zero on the falling edge
of GCLK after the next rising edge of GCLK when
BLANK goes from high to low. Each output turns off
on the falling edge of GSCLK, corresponding to
each gray scale data.

Hi–Z

L ↓ L X X X

8 bits operation mode. The output is turned on if all
the gray scale data is not zero on the falling edge
of GCLK after the next rising edge of GCLK when
BLANK goes from high to low. Each output turns off
on the falling edge of GSCLK corresponding to
each gray scale data.

Hi–Z

L X X CLK capacitor X

Turn off if the level of WDT is not changed within
time set by capacitor connected to WD_CAP.

L

Recover when
the level of

WDT changes.
L X X CLK L X WDT function is disabled. Hi–Z
L X X CLK H X WDT function is disabled. Hi–Z

L X X X X H Turn off if junction temperature exceeds the limit. L

Set TS_ENA to

low for recovery