Texas Instruments TLC5902PZP Datasheet

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

80 mA × 16 Bits and 120 mA × 8 Bits
Drive Capability and Output Counts

D

5 mA to 80 mA/10 mA to 120 mA Constant
Current Output Range

D

Constant Currency Accuracy of ±4%
(Maximum Error Between Bits)

D

Constant Current Output Terminals
– 0.4 V (Output Current 0 to 40 mA)
– 0.7 V (Output Current 40 to 80 mA)

D

256 Gray Scale Display With Pulse Width
Control 256 Steps

D

Brightness Adjustment
– Output Current Adjustment for 32 Steps

(Adjustment for Brightness Deviation
Between LEDs)

– 8 Steps Brightness Control by 8 Times

Speed Gray Scale Control Clock
(Brightness Adjustment for Panel)

D

Protection
– WDT Function
– TSD Function

D

Clock Synchronized 8-Bit Parallel Input

D

Anode Common LED Type Applied

D

CMOS Input Signal Level
(Schmitt-Triggered Input for All Input
Terminals)

D

4.5 V to 5.5 V Power Supply Voltage

D

15 V Maximum Output Voltage

D

15 MHz Maximum Data Transfer Rate

D

4 MHz Maximum Gray Scale Clock
Frequency

D

–20°C to 85°C Operating Free-Air
T emperature Range

D

100-Pin HTQFP Package
(PD = 4.7 W, T

A

= 25°C)

description

The TLC5902 is a constant current driver that incorporates shift register, data latch, and constant current
circuitry with a current value adjustable and 256 gray-scale display that uses pulse width control. The output
current can be selected as maximum 80 mA with 16 bits or 120 mA with 8 bits. The current value of the constant
current output is set by one external resister. After this device is mounted on a printed-circuit board (PCB), the
brightness deviation between LEDs (ICs) can be adjusted using an external data input, and the brightness
control for the panel can be adjusted using the brightness adjustment circuitry. Moreover, the device
incorporates watchdog timer (WDT) circuitry , which turns the constant current output off when the scan signal
is stopped during dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns constant
current output off when the junction temperature exceeds the limit.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

NC
DOUT5
DOUT6

NC
NC

GNDANA
WD_CAP
PV
IREF
OUT15
TEST2
NC
GNDLED

NC
OUT14

NC
NC
GNDLED
NC
NC
OUT12

DIN4
DIN6

DIN7

TS_ENA

VCCLOG

NC

MODE

GNDLOG

NC

OUT0

NC

GNDLED

NC

NC
OUT1
OUT2

NC

GNDLED

NC

NC
OUT3

NCNCDIN3

DIN1

DIN0

GSCLK

BLANK

NC

NC

DOWNNCNC

BOUT

GSOUT

DOUT0

DOUT1

DOUT2

DOUT3

DOUT4

NC

NC

OUT4

NC

GNDLED

OUT5

NC

GNDLED

OUT7

NC

GNDLED

NC

OUT10

NC

NCNCNC

NC

OUT9

HTQFP PACKAGE

(TOP VIEW)

DIN5

TEST1

WDT

RSEL

DCLK

VCCANA

OUT13

OUT6

GNDLED

NC

NC

OUT8

OUT11

NC

DOUT7

LA TCH

ENABLE

DIN2

BC_ENA

NC

CC

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

TSD

DOUT0

DOUT7

BC_ENA

RSEL

DIN0

DIN7

DCLK

MODE

GSCLK

BLANK

TS_ENA

WDT

WD_CAP

IREF

GSOUT

BOUT

DOWN

DCLK

Controller

OUT0 OUT15

WDT

Shift Register and Data Latch

Brightness Control

Register

16 × 8 Bits

Shift Register

Data Latch

8 Bits

Gray Scale

Counter

16 × 8 Bits

Comparator

LATCH

ENABLE

16 Bits

Constant Current Driver

Current Reference

Circuit

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram for shift register and data latch

Comparator

DCLK

Controller

Comparator

DOUT(0–7)

BC_ENA

RSEL

DIN(0–7)

DCLK

MODE

Q7 Q15Q0

Q0

Q15

1 × 8 Bits Shift Register

(Brightness Control)

1 × 8 Bits Latch

(Brightness Control)

To
8 Bits Gray Scale Counter
Current Reference
Circuitry

16 × 8 Bits

Shift Register

(Gray Scale Data))

16 × 8 Bits
Data Latch

(Gray Scale Data))

LATCH

ENABLE

Comparator

Constant Current Driver

Control Line
Data (8 Bits)

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent input and output schematic diagrams

VCCLOG

Input

INPUT

GNDLOG

VCCLOG

OUTPUT

GNDLOG

GNDLOG

OUTn

GNDLED

OUTn

DOUT (0–7), GSOUT, BOUT

DOWN

DOWN

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

NO.

I/O

DESCRIPTION

BC_ENA 85 I

Brightness control enable. When BC_ENA is low, the brightness control function is disabled. At
this time, the brightness control latch is reset to 1Fh. Output current value is 100% of setting value
by an external resistor and the frequency division ratio of GSCLK is 1/1.

BLANK 68 I

Blank (Light off). When BLANK is high, all the output of the constant current driver is turned off.
All the output is turned on (LED on) synchronizing to the falling edge of GCLK after next rising edge

of GCLK when BLANK goes from high to low.
BOUT 57 O Blank signal delay. BOUT is output with the addition of delay time to BLANK.
CONDUCTIVE

PAD

package

surface

Heat sink pad

DCLK 65 I

Clock input for data transfer. The input data of DIN is synchronized to the rising edge of DCLK, and

transferred to DOUT. DCLK is valid at the rising edge after ENABLE goes low.
DIN7–DIN0

70,71,72,73,
76,77,78,79

I Input for shift register for both gray scale data and brightness control. It is 8 bits parallel data.

DOUT7–DOUT0

47,48,49,51,
52,53,54,55

O Output for shift register for both gray scale data and brightness control.

DOWN 60 O

Shutdown. DOWN is configured as an open collector. It goes low when the constant current output

is shut down by the WDT or TSD function.
ENABLE 64 I Data transfer enable. When ENABLE is high, data is not transferred.
GNDANA 43 Analog ground. (Internally connected to GNDLOG and GNDLED)

GNDLED

5,10,15,20,29,

36,90,96

LED driver ground (Internally connected to GNDANA and GNDLOG)
GNDLOG 84 Logic ground. (Internally connected to GNDANA and GNDLED)
GSCLK 69 I

Clock input for gray scale. The gray scale display is accomplished by lighting the LED until the

number of GSCLK counted is equal to the data latched.
GSOUT 56 O Clock delay for gray scale. GSOUT is output with addition of delay time to GSCLK

IREF 40 I

Constant current control setting. LED current is set to the desired value by connecting an external

resistor between IREF and GND. The 38 times current is compared to current across external

resistor sink on output terminal.

LATCH 61 I

Latch. When LATCH is high, data on shift register goes through the latch. When LA TCH is low, data

is latched. Accordingly, if data on the shift register is changed during LATCH high, this new value

is latched.
MODE 83 I

8/16 bits select. When the MODE is high, the 16 bits output is selected. When the MODE is low,

the 8 bits output is selected.

OUT0–OUT15

87,93,94,100,

3,7,8,12,13,17,

18,22,26,32,

33,39

O Constant current output

PV

CC

41 LED driver power supply voltage

RSEL 66 I

Shift register latch switching. When RSEL is low, the shift register and latch for gray scale are

selected. When RSEL is high, the shift register and latch for brightness control are selected.
TEST1, TEST2 88,38 I TEST. Factory test terminal. TEST should be connected to GND for normal operation.

TS_ENA 80 I

TSD (Thermal shutdown) enable. When TS_ENA is high, TSD is enabled. When TS_ENA is low,

TSD is disabled.
VCCANA 45 Analog power supply voltage
VCCLOG 81 Logic power supply voltage

WD_CAP 42 I

WDT detection time adjustment. The capacitor for WDT detection time adjustment is connected

between WD_CAP and GND. When WD_CAP is directly connected to GND, the WDT function

is disabled.

WD 62 I

WDT scan input. By applying a scan signal to this terminal, the scan signal can be monitored and

constant current output can be turned off. LED is protected from damage from burning when the

scan signal is stopped during the constant period. The scan signal should be applied to this

terminal by connecting W_CAP to GND even though no WDT function is used.

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables

Truth Table (Data)

BC_ENA

ENABLE DCLK RSEL LATCH MODE DOUT0 – DOUT7 OPERATION/FUNCTION

L X X X X X No change Data latch for brightness control is set to 1Fh.
X H X X X X No change

Data transfer for gray scale and brightness
control does not occur.

X L ↑ H X X

Shift register for
brightness control

Data of DIN0 to DIN7 is clocked into the shift
register for brightness control.

X L ↑ L X H

Data for shift register
before 16 bytes (written
before 16 times)

Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.

X L ↑ L X L

Shift register for gray
scale before 8 bytes
(written before 8 times)

Data of DIN0 to DIN7 is clocked into the first byte
of the shift register for gray scale data.

H X X H H X No change

Shift register for brightness control goes through
data latch for brightness control.

X X X L H X No change

Shift register for gray scale goes through data
latch for gray scale.

H X X X L X No change

The value for the shift register selected by RSEL
is latched.

Truth Table (Display/Protection)

BLANK

GSCLK MODE WDT WD_CAP TS_ENA OUT0~15 DOWN

OPERATION/

FUNCTION

H X X X X X Off Hi–Z

L ↓ H X X X

16 bits operation mode. The output is turned on if
all the gray scale data is not zero on the falling edge
of GCLK after the next rising edge of GCLK when
BLANK goes from high to low. Each output turns off
on the falling edge of GSCLK, corresponding to
each gray scale data.

Hi–Z

L ↓ L X X X

8 bits operation mode. The output is turned on if all
the gray scale data is not zero on the falling edge
of GCLK after the next rising edge of GCLK when
BLANK goes from high to low. Each output turns off
on the falling edge of GSCLK corresponding to
each gray scale data.

Hi–Z

L X X CLK capacitor X

Turn off if the level of WDT is not changed within
time set by capacitor connected to WD_CAP.

L

Recover when
the level of

WDT changes.
L X X CLK L X WDT function is disabled. Hi–Z
L X X CLK H X WDT function is disabled. Hi–Z

L X X X X H Turn off if junction temperature exceeds the limit. L

Set TS_ENA to

low for recovery

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings (see Note 1)

†

Logic supply voltage, V

CC(LOG)

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage for constant current circuit, PVCC –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog supply voltage, V

CC(ANA)

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (DC), I

OL(C)

90 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range –0.3 V to V

CC(LOG)

0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V(

OUTn)

, V(

BOUT)

and V(

GSOUT)

–0.3 V to V

CC(LOG)

0.3 V. . . . . . . . . . . . . . . . . . . . .

Output voltage range, V(

OUTn)

and V(

DOWN)

–0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation at (or below) T

A

= 25°C (see Note 2) 4.7 W. . . . . . . . . . . . . . . . . . . . . . . . .

Operating free air temperature range, TA –20°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to GNDLOG terminal.

2. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.

recommended operating conditions

dc characteristics over recommended ranges of operating free-air temperature,
V

CC(LOG)

= V

CC(ANA)

= PVCC = 4.5 V to 5.5 V (unless otherwise noted)

MIN

NOM MAX UNIT

Logic supply voltage, V

CC(LOG)

4.5 5 5.5 V

Supply voltage for constant current circuit,
PV

CC

4.5 5 5.5 V

Analog power supply, V

CC(ANA)

4.5 5 5.5 V

Voltage between VCC, V(

DEF1)

(see Note 3)

V

DEF1

= V

CC(LOG)

– V

CC(ANA)

V

CC(LOG)

– PV

CC

, V

CC(ANA)

– PV

CC

–0.3 0 0.3 V

Voltage between GND, V(

DEF2)

(see Note 3)

V

(DEF2)

= GND(LOG) – GND(ANA)

GND(LOG) – GND(LED)

, GND(ANA) –

GND(LED)

–0.3 0 0.3 V

High-level input voltage, V

IH

0.8 V

CC(LOG)

V

CC(LOG)

V

Low-level input voltage, V

IL

GND(LOG) Á 0.2 V

CC(LOG)

V

High-level output current, I

O(H)

V

CC(LOG)

= 4.5 V, DOUT0 to DOUT7,

BOUT, GSOUT

–1

Low-level output current, I

V

CCLOG

= 4.5 V, DOUT0 to DOUT7,

BOUT, GSOUT

1

mA

,

O(L)

V

CC(LOG)

= 4.5 V, DOWN 5 mA

Constant output current, I

OL(C)

OUT0 to OUT15 5 80 mA

NOTE 3: Each voltage is supplied by single power supply, not a separated power supply.

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (continued)

ac characteristics over recommended ranges of operating free-air temperature,
V

CC(LOG)

= V

CC(ANA)

= PVCC = 4.5 V to 5.5 V (unless otherwise noted)

MIN

TYP MAX UNIT

At single operation 15

DCLK clock frequenc

y,

f

(DCLK)

At cascade operation 10

MH

z

DCLK pulse duration (high or low level), t

w(h)/tw(l)

20 ns

Frequency division ratio 1/1 4 MHz

GSCLK clock frequency, f

(GSCLK)

Frequency division ratio 1/1, T

A

= 25°C,

V

CCLOG

= V

CCANA

= PVCC = 5 V

8 MHz

GSCLK pulse duration (high or low level), t

w(h)/tw(l)

75 ns

WDT clock frequency, f

(WDT)

5 MHz

WDT pulse duration (high or low level), t

w(h)/tw(l)

50 ns

LAT pulse duration (high or low level), t

w(h)

LATCH 50 ns

Rise/fall time, tr/t

f

100 ns
DINn – DCLK 10
LATCH – DCLK 15
BLANK – GSCLK 20

Setup time, t

su

ENABLE – DCLK 15

ns
LATCH – GSCLK 10
RSEL – DCLK 10
RSEL – LATCH 20
DINn – DCLK 15
LATCH – DCLK 30

Hold time, t

n

ENABLE – DCLK 20

ns
RSEL – DCLK 20
RSEL – LATCH 20

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, MIN/MAX: V

CC(LOG)

= V

CCANA

= PVCC = 4.5 V to 5.5 V , TA = –20°C to 85°C

TYP: V

CC(LOG)

= V

CC(ANA)

= PVCC = 5 V, TA = 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High–level output voltage

IOH = –1 mA, DOUT0 to DOUT7,
GSOUT, BOUT

V

CC(LOG)

–0.5V

V

V

Low–level output volta

g

e

IOL = 1 mA, DOUT0 to DOUT7, GSOUT,
BOUT

0.5
V

OL

g

IOL = 5 mA DOWN 0.5

I

I

Input current VI = V

CC(LOG)

or GND(LOG) ±1 µA

I

(OG)

pp

Input signal is static, TS_ENA = H,
WD_CAP = OPEN

1

I

(LOG)

Supply current (logic)

Data transfer, DCLK = 15 MHz,
GSCLK = 1 MHz

18 30

mA

pp

LED turns on, R

(IREF)

= 590 Ω 3 5

I

(ANA)

Supply current (analog)

LED turns off, R

(IREF)

= 590 Ω 3 5

mA

R

(IREF)

= 1180 Ω, LED turns off 15 20

R

(IREF)

= 590 Ω, LED turns off 30 40

I

(PVCC)

Supply current (constant current driver)

VO = 1 V, R

(IREF)

= 1180 Ω,

16 bits output turns on

25 35

mA

VO = 1 V, R

(IREF)

= 590 Ω,

16 bits output turns on

50 70

I

OL(C1)

p

V

O

= 1 V, V

(IREF)

= 1.24 V ,

R

(IREF)

= 1180 Ω

35 40 45 mA

I

OL(C2)

Constant output current

V

O

= 1 V, V

(IREF)

= 1.24 V ,

R

(IREF)

= 590 Ω

70 80 90 mA

I

lkg

Constant output leakage current

V

O

= 15 V , R

(IREF)

= 590 Ω,

LED turn off

10 µA

∆I

OL(C)

Constant output current error between bit

V

CC(LOG)

= V

CC(ANA)

= PVCC = 5 V,

V

(IREF)

= 1.24 V , R

(IREF)

= 590 Ω,

All bits turns on, VO = 1 V

±1% ±4%

I∆

OL(C1)

Changes in constant output current
depend on supply voltage

V

(IREF)

= 1.24 V ±1% ±4% V

I∆

OL(C2)

Changes in constant output current
depend on output voltage

V

(IREF)

= 1.24 V , R

(IREF)

= 1180 Ω,

1 bit output turns on, VO = 1 V to 3 V

±1% ±2% V

T(

tsd)

TSD detection temperature (thermal
shutdown circuit)

Junction temperature 150 160 170 °C

T(

wdt)

WDT detection time (watch–dog timer
circuit)

No external capacitor 1 3 8 ms

V(

IREF)

Voltage reference BC_ENA = L, R

(IREF)

= 590 Ω 1.24 V

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, CL = 15 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DOUT 12 30
OUT 250

trRise time

GSOUT 13 30

ns

BOUT 13 30
DOUT 8 20
OUT 150

tfFall time

GSOUT 10 25

ns

BOUT 10 25
OUTn+1 – OUTn 8 15
BLANK ↑ – OUT0 350 500

p

GSCLK ↓ – OUT0 350 500

tdPropagation delay time

DCLK ↑ – DOUT 15 30 50

ns

GSCLK – GSOUT 10 25 50
BLANK – BOUT 10 25 50

timing requirements

50%

90%

10%

100%

0%

100%

0%

50%

100%

0%

t

d

50%

100%

0%

V

IH

V

IL

t

r

t

f

VIH OR V

OH

VIL OR V

OL

t

w(h)

t

w(l)

VIH OR V

OH

VIL OR V

OL

VIH OR V

OH

VIL OR V

OL

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

constant current output selection by user (80 mA × 16 bits or 120 mA × 8 bits)

When MODE terminal is set to high, output is selected as 80 mA × 16 bits. When MODE terminal is set to low,
output is selected as 120 mA × 8 bits. By this setting, the internal shift register and latch are changed. Note that
two constant output terminals should be tied, such as OUT0 to OUT1 and OUT2 to OUT3 when 8-bit output is
selected.

MODE OUTPUT

H 80 mA x 16 bits
L 120 mA x 8 bits

setting for constant current value

On the constant current output terminals (OUT0 to OUT15), approximately 38 times the current that flows
through the external resistor, R

(IREF)

(connected between IREF and GND), can flow. The external resistor value

is calculated using the following equation.

I

(OUTn)

(mA)^38 1.24(V)

R

(IREF)

(kW)

More current flows if IREF is connected to GND directly.

shift register latch for gray scale data

The shift register latch for gray scale data is set as 8 × 8 bits configuration each at 8 bit mode, and as 16 x 8
bits configuration each at 16-bit mode. By setting RSEL to low, the shift register latch for gray scale data is
selected. Data structure shows that DIN0 corresponds to LSB, and DIN7 to MSB. This results in 28 = 256 steps
gray scale. The latched data is compared to GSCLK (clock for gray scale) counts, and constant current output
continues to turn on until these values are equal.

shift register latch for brightness control

The shift register latch for brightness control is configured with 1 × 8 bits each. The data input terminal and latch
terminal are common to shift register latch for gray scale data. By setting RSEL to low, the shift register latch
for gray scale data is selected, and by setting RSEL to high, the shift register latch for brightness control is
selected. If the brightness control function is not used, BC_ENA terminal should be pulled low. Since the
brightness control latch is reset to initial value of 0001 11 1 1h, it is not necessary to write data to shift register latch
for brightness control. When power is up, latch data is undetermined. Data should be written to shift register
latch when the brightness control function is used. Also, rewriting the latch value for brightness control is
inhibited when the LED is turned on.

RSEL SHIFT REGISTER LATCH SELECTED

L Shift register latch for gray scale data
H Shift register latch for brightness control

(1)

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

write data to both shift register latches

The shift register latch is selected using the RSEL terminal. The data input method is the same for both shift
register latches. The data is applied to DIN0 to DIN7 of 8-bits data input terminal, and transferred synchronizing
to DCLK. The data of DIN0 to DIN7 is transferred to the direction from OUT0 to OUT15 synchronizing to DCLK.
The shift register for brightness control is 1-bit length resulting in one time of DCLK input. The shift register for
gray scale data is 8-bits length at 8-bit mode resulting in eight times of DCLK, and 16-bit length at 16-bit mode
resulting in 16 times of DCLK input. At the number of DCLK input for each case, output data appear on DOUT0
to DOUT7. When LA TCH

goes from low to high, data is latched internally . Then, when LATCH goes low, data

is held. RSEL switching should be done when DCLK and LATCH are low.

brightness control latch configuration

The brightness control latch is configured as DIN0 corresponds to LSB, and DIN7 to MSB. The lower 5 bits are
assigned for output current adjustment, and the upper 3 bits are for a frequency division ratio setting of GSCLK.

DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

MSB ⋅ ⋅⋅⋅ ⋅ ⋅⋅⋅ ⋅ ⋅⋅⋅ ⋅ ⋅⋅⋅ ⋅ ⋅⋅⋅ ⋅ ⋅⋅⋅ LSB

0

†

0 0 1 1 1 1 1

Frequency division ratio setting of GSCLK Output current setting

†

BC_ENA is low.

output current adjustment – brightness adjustment between ICs

By using the lower 5 bits of the brightness control latch, output current can be adjusted to 32 steps. When output
current is set to 100% by the external resistor at 1 1 1 1 1h of the latched value, it is adjusted as 1 step or 32 steps
of 1.6% current ratio between 100 and 51.6%. By using this function, the brightness control between modules
(ICs) can be adjusted, sending the desired data externally even if ICs are mounted on PCB. When BC_ENA
is pulled low, the latch is reset to the initial value of 00011111h, and the output current is set to 100%.

CODE CURRENT RATIO (%) 20 (mA) 80 (mA) V

IREF

(TYP)

MSB 00000 LSB 51.6 10.3 41.3 0.64

⋅
⋅
⋅
⋅

⋅
⋅
⋅
⋅

⋅
⋅
⋅
⋅

⋅
⋅
⋅
⋅

⋅
⋅
⋅
⋅

11110 98.4 19.7 78.7 1.22

11111

†

100 20.0 80.0 1.24

†

BC_ENA is low.

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

frequency division ratio setting for GSCLK(clock for gray scale) – panel brightness adjustment

By using the upper 3 bits of the brightness control latch, GSCLK can be divided into 1/1 to 1/8. If GSCLK is set
to 8 times the speed (256 × 8 = 2048) of the frequency during the horizontal scanning time, the brightness can
be adjusted to 8 steps by selecting the frequency division ratio. Thus, the total panel brightness can be adjusted
at once and applied to the brightness of day or night. When BC_ENA is pulled low, GSCLK is not divided. When
BC_ENA is pulled high, the brightness can be adjusted as shown in the following table.

CODE

FREQUENCY DIVISION RATIO RELATIVE BRIGHTNESS RATIO

(%)

MSB 000 LSB

†

1/1 12.5
001 1/2 25.0
010 1/3 37.5
011 1/4 50.0
100 1/5 62.5
101 1/6 75.0
110 1/7 87.5
111 1/8 100

†

BC_ENA is low.

constant output current operation

The constant current output turns on (sink constant current) if all the gray-scale data latched into the gray-scale
latch is not zero on the falling edge of GCLK, after the next rising edge of GCLK when BLANK goes from high
to low. After that, the number of the falling edge is counted by the 8-bit gray scale counter . Output counted that
corresponds to gray-scale data is turned off (stop to sink constant current). If the shift register for gray scale is
updated during LATCH

high, data on the gray-scale data latch is also updated, affecting the number of gray
scale of constant current output. Accordingly , during the on state of constant current output, LATCH is kept to
low and the gray-scale data latch is held. When unconnected constant current output terminals exist, operation
is complete after writing zero (data for LED turn off) to the corresponding gray-scale data latch. If this action is
not completed, the supply current (I

PVCC

) in the constant current driver portion increases.

protection

This device incorporates WDT and TSD functions. In WDT or TSD functions, the current output is stopped (Logic
portion is still operating). By monitoring the DOWN terminal, these failures are detected immediately. Since
DOWN

output is configured as an open collector, outputs of multiple ICs are brought together.

WDT

When the scan signal is stopped during a fixed period in dynamic scanning operation, the constant current
output is turned off, preventing the LED from burning damage. The time detected can be set using the external
capacitor (C1). The typical value is approximately 3 ms without a capacitor, 33 ms with a 1000 pF capacitor,
and 300 ms with a 0.01 µF capacitor. Once the scan signal is applied again, the abnormal status is released
and normal operation is resumed. During static operation, the WDT function is disabled, connecting WD_CAP
to GND. The scan signal should be applied to the WDT terminal even though the WDT function is not used.

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Figure 1. WDT Operational Time

3000

300

33

3

010310

4

10

5

C1 – External Capacitor – pF

t – Time – ms

WDT Operational Time T (ms) ≅ 3+0.03 × C1 (pF)

Figure 2. WDT Usage Example

TLC5902

WDT

WD_CAP

Scan Signal

C1

TSD (thermal shutdown)

When the junction temperature exceeds the limit, TSD functions and turns the constant current output off. When
TSD is used, TS_ENA is pulled high. When TSD is not used, TS_ENA is pulled low. To recover to normal
operation, the power supply is turned off or TS_ENA is pulled low.

noise reduction

concurrent switching noise reduction

The concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time.
T o prevent this noise, the device has delay output terminals such as GSOUT and BOUT for GSCLK and BLANK
respectively . Connecting these outputs to GSCLK and BLANK terminals of the next stage IC allows differences
in the switching time between ICs to be made. When GSCLK is output to GSOUT through the device, duty is
changed, so that the number of stages to be connected will be limited to a maximum of 10 at GSCLK = 4 MHz.

output slope

The on and off time of constant current output at an output current of 80 mA is approximately 150 ns and 250 ns
respectively . It is ef fective in reducing concurrent switching noise that occurs when multiple outputs turn on or
off at the same time.

delay between constant current output

The constant current output has a delay time of approximately 8 ns between output. It means approximately
120 ns delay time exists between OUT0 and OUT15. This time difference by delay is effective for reduction of
concurrent switching noise as well as output slope. This delay time has the same value at 8-bits or 16-bits
operation mode.

TLC5902
LED DRIVER

SLLS382 – DECEMBER 1999

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

noise reduction (continued)

power supply

VCCLOG, VCCANA, and PVCC are supplied by a single power supply to minimize voltage differences between
these terminals.

The bypass capacitor is located between power supply and GND to eliminate the variation of power supply
voltage.

GND

Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally
connected to reduce noise influence.

heat sink pad

The heat sink pad should be connected to GND to eliminate the noise influence since it is connected to the
bottom side of the IC chip. Also, the desired thermal effect is obtained by connecting this pad to the PCB pattern
with better thermal conductivity.

–20 25 85

0

1.48

3.2

4.7

2.4

0

TA – Free-Air Temperature – °C

Output Voltage (Constant Current) – V

– Total Power Dissipation – W

P

D

NOTES: A. IC is mounted on PCB. PCB size: 102 × 76 × 1.6 [mm3], four layers with internal two layer having plane. The thermal pad is soldered

to PCB pattern of 10 mm2. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.

VCCLOG = VCCANA = PVCC = 5 V, I

OL(C)

= 80 mA, ICC is typical value

B. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad.

Figure 3. Power Rating

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

0

10

20

30

40

50

60

70

80

90

0.1 1 10

NOTE: The output current is at 16 bit output.

When 8-bit output, it will be the current of sum of two
outputs. This sum current should be set up with the range
of 10 mA to 120 mA. The resistor, R

IRF

, should be located
as close as possible to IREF terminal to eliminate the noise
influence.

Conditions : V

O

+

1V,V

(IREF)

+

1.24 V

I

OL(C)

(mA)

0

V

(IREF)

(V)

R

(IREF)

(k

W

38

R

(IREF)

(kW)

0

47

I

OL(C)

(mA)

I

OL(C)

– mA

R

(IREF)

– kΩ

Figure 4. Current on Constant Current Output vs External Resistor

R

IREF

= 4.70 k

0

1.00.20 0.4 0.6 0.8

100

10

0.1 0.3 0.5 0.7 0.9

20

30

40

50

60

70

80

90

R

IREF

= 2.35 k

R

IREF

= 1.57 k

R

IREF

= 1.18 k

R

IREF

= 940

R

IREF

= 780

R

IREF

= 670

R

IREF

= 590

Minimum voltage applied

Ω
Ω

Ω
Ω

Ω
Ω

Ω

Ω

V

O – Output Voltage –V

I

OL(C)

– mA

NOTE: VCCLOG = VCCANA = PVCC = 5 V, TA = 25°C.

Figure 5. Current on Constant Current Output vs Voltage Applied To Constant Current Output Terminal

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Figure 6. Timing Diagram (Shift Register for Gray Scale Data)

tsu(ENABLE–DCLK)

DIN0

DCLK

ENABLE

DIN7

LATCH

DOUT0

DOUT7

RSEL

1/f(DCLK)

th(ENABLE–DCLK)

tsu(DIN–DCLK) th(DIN–DCLK) t

w(l)

(DCLK) t

w(h)

(DCLK)

D00_A D01_A D02_A D0E_A D00_B D01_B

D0E_B

D0F_B

D00_C D01_C D02_C

D70_A D71_A D72_A D7E_A D7F_A D70_B D71_B

D7E_B D7F_B

D70_C D71_C D72_C

th(LATCH–DCLK) tsu(LATCH–DCLK)

td(DCLK–DOUT) t

w(h)

(LATCH)

D00_A D01_A D0E_A D0F_A D00_B

D0F_A

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ÎÎ

ÎÎ

ÎÎ

D70_A D71_A D7E_A D7F_A D70_B

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

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ÎÎ

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ÎÎ

ÎÎ

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ÎÎ

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ÎÎ

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ÎÎ

ÎÎ

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Figure 7. Timing Diagram (Brightness Control Register)

#

Internal brightness control latch

DIN0

DCLK

ENABLE

DIN7

LATCH

BCL_0

#

BCL_7

#

RSEL

tsu(RSEL–DCLK)

D00_A D04_A D05_A D06_A D07_A D08_A D09_A D0A_A D00_B

D70_A D71_A D72_A D73_A D74_A D75_A D76_A D77_A D78_A D79_A

D7A_A

BC_ENA

DOUT0

DOUT7

th(RSEL–DCLK)

tsu(RSEL–LATCH

)

D01_A D03_AD02_A

D70_B D71_B

t

h

(RSEL–LATCH

)

D05_A

D75_A

D06_A

D76_A

D0n–2_N

D7n–2_N

D0n–1_N D02_A D05_A

D06_A

D07_A

D0n_N

D00_A

D75_A

D76_A

D77_A

D7n_N

D70_A

D7n–1_N D72_A

D01_B

D0n–1_N

D7n–1_N

D02_A

D72_A

Default Value ”1”

Default Value ”0”

ÎÎ

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ÎÎ

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ÎÎ

ÎÎ

ÎÎ

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Figure 8. Timing Diagram (Constant Current Output)

(Note1)

(Note1) (Note1)

(Note1)OFF

GSCLK

BLANK

WDT

DOWN

LATCH

1/f(GSCLK)

t

w(l)

(GSCLK)

t

w(h)

(GSCLK)

td(GSCLK–OUT0)

tsu(BLANK–GSCLK)

td(BLANK–OUT0)

OUT0

OUT15

td(OUTn+1–OUTn)

t

wd

1/f(WDT)

t

w(l)

(WDT)

t

w(h)

(WDT)

td(GSCLK–OUT0)

td(GSCLK–GSOUT)

td(BLANK–BOUT)

BOUT

GSOUT

t

su

(LATCH

–GSCLK)

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ÎÎ

ÎÎ

OFF OFF

OFF OFF OFF

ON(Note1)

ON(Note1)

HI–z

NOTE 1: ON or OFF, or ON time is varied depending on the gray scale data and BLANK.

TLC5902

LED DRIVER

SLLS382 – DECEMBER 1999

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PZP (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK

0,13 NOM

50

26

Thermal Pad
(see Note D)

0,75
0,45

0,25

Seating Plane

4146929/A 04/99

Gage Plane

0,27

75

0,17

76

100

SQ

SQ

1

15,80

16,20

14,20
13,80

12,00 TYP

1,05
0,95

1,20 MAX

51

25

0,50

M

0,08

0,08

0°–7°

0,15
0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The dimensions of the thermal
pad are 2 mm × 2 mm (maximum). The pad is centered on the bottom of the package.

E. Falls within JEDEC MS-026

PowerPAD is a trademark of Texas Instruments Incorporated.

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright  1999, Texas Instruments Incorporated