Texas Instruments TLC5628IN, TLC5628IDWR, TLC5628CN, TLC5628CDWR, TLC5628CDW Datasheet
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Eight 8-Bit Voltage Output DACs
D
5-V Single-Supply Operation
D
Serial Interface
D
High-Impedance Reference Inputs
D
Programmable 1 or 2 Times Output Range
D
Simultaneous Update Facility
D
Internal Power-On Reset
D
Low-Power Consumption
D
Half-Buffered Output
applications
D
Programmable V oltage Sources
D
Digitally Controlled Amplifiers/Attenuators
D
Mobile Communications
D
Automatic Test Equipment
D
Process Monitoring and Control
D
Signal Synthesis
description
The TLC5628C and TLC5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered
reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two
times the reference voltages and GND and are monotonic. The device is simple to use, running from a single
supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.
Digital control of the TLC5628C and TLC5628I are over a simple three-wire serial bus that is CMOS compatible
and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word
comprises eight bits of data, three DAC select bits, and a range bit, the latter allowing selection between the
times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values
to be written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital
inputs feature Schmitt triggers for high-noise immunity.
The 16-terminal small-outline (D) package allows digital control of analog functions in space-critical
applications. The TLC5628C is characterized for operation from 0°C to 70°C. The TLC5628I is characterized
for operation from –40°C to 85°C. The TLC5628C and TLC5628I do not require external trimming.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(DW)
PLASTIC DIP
(N)
0°C to 70°C TLC5628CDW TLC5628CN
–40°C to 85°C TLC5628IDW TLC5628IN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DACB
DACA
GND
DATA
CLK
V
DD
DACE
DACF
DACC
DACD
REF1
LDAC
LOAD
REF2
DACH
DACG
N OR DW PACKAGE
(TOP VIEW)
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Serial
Interface
× 2
DAC
DAC
× 2
× 2
DAC
DAC
× 2
LDAC
REF1
+
–
+
–
+
–
+
–
+
–
+
–
REF2
CLK
DATA
LOAD
DACA
DACD
DACE
DACH
9
8
8
8
8
LatchLatch
Latch Latch
LatchLatch
Latch Latch
Power-On
Reset
14
11
5
4
12
13
2
15
7
10
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
CLK 5 I Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock
applied to the CLK terminal.
DACA 2 O DAC A analog output
DACB 1 O DAC B analog output
DACC 16 O DAC C analog output
DACD 15 O DAC D analog output
DACE 7 O DAC E analog output
DACF 8 O DAC F analog output
DACG 9 O DAC G analog output
DACH 10 O DAC H analog output
DATA 4 I Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.
Each data bit is clocked into the register on the falling edge of the clock signal.
GND 3 I Ground return and reference terminal
LDAC 13 I Load DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serial
interface. The DAC outputs are only updated when LDAC is taken from high to low.
LOAD 12 I Serial interface load control. When LDAC is low, the falling edge of the LOAD signal latches the digital data into
the output latch and immediately produces the analog voltage at the DAC output terminal.
REF1 14 I Reference voltage input to DAC ABCD. This voltage defines the analog output range.
REF2 11 I Reference voltage input to DAC EFGH. This voltage defines the analog output range.
V
DD
6 I Positive supply voltage
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
The TLC5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in T able 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer . Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance
of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to the
reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2
is used by DACE through DACH.
Each DAC output is buffered by a configurable-gain output amplifier , that can be programmed to times 1 or times
2 gain.
On power up, the DACs are reset to CODE 0.
Each output voltage is given by:
VO(DACA|B|C|D|E|F|G|H)+REF
CODE
256
(1)
RNG bit value)
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.
Table 1. Ideal Output Transfer
D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE
0 0 0 0 0 0 0 0 GND
0 0000001 (1/256) × REF (1+RNG)
• ••••••• •
• ••••••• •
0 1111111 (127/256) × REF (1+RNG)
1 0000000 (128/256) × REF (1+RNG)
• ••••••• •
• ••••••• •
1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG)
data interface
With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have
been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as
shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low . When
LDAC is high during serial programming, the new value is stored within the device and can be transferred to
the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit
(MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4.
A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0
DAC Update
CLK
DATA
LOAD
t
su(DATA-CLK)
t
v(DATA-CLK)
t
su(CLK-LOAD)
t
w(LOAD)
t
su(LOAD-CLK)
Figure 1. LOAD-Controlled Update (LDAC = Low)
TLC5628C, TLC5628I
OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
data interface (continued)
CLK
DATA
LOAD
LDAC
DAC Update
A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0
t
su(DATA-CLK)
t
v(DATA-CLK)
t
w(LDAC)
t
su(LOAD–LDAC)
Figure 2. LDAC-Controlled Update
A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0
CLK
DATA
LOAD
LDAC
CLK Low
A2
Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low)
A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0
CLK
DATA
LOAD
LDAC
CLK Low
A2
Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word
T able 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output
range. When RNG = low, the output range is between the applied reference voltage and GND, and when
RNG = high, the range is between twice the applied reference voltage and GND.
Table 2. Serial Input Decode
A2 A1 A0 DAC UPDATED
0 0 0 DACA
0 0 1 DACB
0 1 0 DACC
0 1 1 DACD
1 0 0 DACE
1 0 1 DACF
1 1 0 DACG
1 1 1 DACH
Loading...