Texas Instruments TLC32040MJ, TLC32040MFK, TLC32040IN, TLC32040CN, TLC32040CFN Datasheet

Download

TLC32040M

ANALOG INTERFACE CIRCUIT

SGLS031 – MAY 1990

• Advanced LinCMOS Silicon-Gate Process

Technology

J PACKAGE (TOP VIEW)

• 14-Bit Dynamic Range ADC and DAC

FSR

REF

FSX

1 2 3 4 5 6 7 8 9 10 11 12 13 14

• Variable ADC and DAC Sampling Rate up to

19200 Samples Per Second

• Switched-Capacitor Antialiasing Input Filter

and Output-Reconstruction Filter

• Serial Port for Direct Interface to

SMJ320E14, SMJ32020, SMJ320C25, and SMJ320C30 Digital Processors

• Synchronous or Asynchronous ADC and

DAC Conversion Rates With Programmable Incremental ADC and DAC Conversion Timing Adjustments

• Serial Port Interface to SN54299

Serial-to-Parallel Shift Register for Parallel

RESET

EODR

MSTR CLK

DGTL GND SHIFT CLK

EODX

WORD/BYTE

Interface to SMJ320C10, SMJ320C15, SMJ320E15, or Other Digital Processors

description

FK PACKAGE

(TOP VIEW)

The TLC32040M interface circuit is a complete

EODR

FSR

analog-to-digital and digital-to-analog input/ output system on a single monolithic CMOS chip. This device integrates a band-pass switched-capacitor antialiasing input filter, a 14-bit-resolution A/D converter, four microprocessor-compatible serial port modes, a 14-bit-resolution D/A converter, and a low-pass switched-capacitor output reconstruction filter. The device offers numerous combinations of master clock input frequencies and conversion/

MSTR CLK

REF DGTL GND SHIFT CLK

EODX

5 6 7 8 9

12 13

RESETNUNUNUIN+

3212827

426

14 15 16 1718

sampling rates, which can be changed via digital processor control.

FSX

Typical applications for this integrated circuit include modems (7.2-, 8-, 9.6-, 14.4-, and

19.2-kHz sampling rate), analog interface for digital signal processors (DSPs), speech recognition/storage systems, industrial process control, biomedical instrumentation, acoustical signal processing, spectral analysis, data acquisition, and instrumentation

NU–Nonusable; no external connection should be made to

these pins.

WORD/BYTE

recorders. Four serial modes, which allow direct interface to the SMJ320E14, SMJ32020, SMJ320C25, and SMJ320C30 digital signal processors, are provided. Also, when the transmit and receive sections of the analog interface circuit (AIC) are operating synchronously, it will interface to two SN54299 serial-to-parallel shift registers.These serial-to-parallel shift registers can then interface in parallel to the SMJ320C10, SMJ320C15, SMJ320E15, other digital signal processors, or external FIFO circuitry . Output data pulses are emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate between two transmitted bytes. A flexible control scheme is provided so that the functions of the integrated circuit can be selected and adjusted coincidentally with signal processing via software control.

28 27 26 25 24 23 22 21 20 19 18 17 16 15

NU NU IN+ IN– AUX IN+ AUX IN– OUT+ OUT– V

CC+

CC–

ANLG GND ANLG GND NU NU

IN–

AUX IN+

AUX IN–

OUT+

OUT–

ANLG GND

CC+ CC–

Advanced LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–1

TLC32040M ANALOG INTERFACE CIRCUIT

description (continued)

The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic transitional) low-pass and high-pass filters, respectively, and a fourth-order equalizer. The input filter is implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite filter can be switched out of the signal path. A selectable, auxiliary , differential analog input is provided for applications where more than one analog input is required.

The A/D and D/A converters each have 14 bits of resolution. The A/D and D/A architectures ensure no missing codes and monotonic operation. An internal voltage reference is provided on the TLC32040M to ease the design task and to provide complete control over the performance of the integrated circuit. The internal voltage reference is brought out to a pin and is available to the designer. Separate analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum. The only exception is the DAC sample and hold, which utilizes pseudo-differential circuitry.

The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter with a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed by a continuous-time filter to eliminate images of the digitally encoded signal.

The TLC32040M is characterized for operation from –55°C to 125°C.

functional block diagram

IN+

OUT+

OUT–

IN–

AUX

IN+

AUX

IN–

M U

CC+VCC–

–

ANLG

GND

Band-Pass Filter

Receive Section

–

Transmit Section

DTGL

GND

(DIG)

Low-Pass Filter

M U X

Serial

A/D

Internal Voltage

Reference

D/A

REF RESET

Port

FSR

EODR

MSTR CLK

SHIFT CLK

WORD/BYTE

FSX

EODX

4–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TLC32040M

ANALOG INTERFACE CIRCUIT

NAME NO.

ANLG GND 17, 18 Analog ground return for all internal analog circuits. Not internally connected to DGTL GND. AUX IN+ 24 I Noninverting auxiliary analog input stage. This input can be switched into the band-pass filter and A/D converter

AUX IN– 23 I Inverting auxiliary analog input (see the above AUX IN+ pin description). DGTL GND 9 Digital ground for all internal logic circuits. Not internally connected to ANLG GND. DR 5 O This pin is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits

DX 12 I This pin is used to receive the DAC input bits and timing and control information from the TMS320. This serial

EODR 3 O End of data receive.(See the WORD/BYTE pin description and the Serial Port TIming dIagram.) During the

EODX 11 O End of data transmit. See WORD/BYTE description and Serial Port Timing diagram. During the word-mode timing,

FSR 4 O Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description, FSR

FSX 14 O Frame sync transmit. When this terminal goes low, the SMJ320 serial port will begin transmitting bits to the AIC

IN+ 26 I Noninverting input to analog input amplifier stage IN– 25 I Inverting input to analog input amplifier stage MSTR CLK 6 I The master clock signal is used to derive all the key logic signals of the AIC, such as the shift clock, the

OUT+ 22 O Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads

OUT– 21 O Inverting output of analog output power amplifier. Functionally identical with and complementary to OUT+. REF 8 I/O The internal voltage reference is brought out on this terminal. Also an external voltage reference can be applied

RESET 2 I A reset function is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. This reset function

I/O

path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs will replace the IN+ and IN– inputs. If the bit is a 0, the IN+ and IN– inputs will be used (see the AIC DX data word format section).

from the AIC to the TMS320 serial port is synchronized with the SHIFT CLK signal.

transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT CLK signal.

word-mode timing, this signal is a low-going pulse that occurs immediately after the 16 bits of A/D information have been transmitted from the AIC to the TMS320 serial port. This signal can be used to interrupt a microprocessor upon completion of serial communications. Also, this signal can be used to strobe and enable external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept low until the second byte has been transmitted. The TMS3201 1 or TMS320C17 can use this low-going signal to dif ferentiate between the two bytes as to which is first and which is second.

this signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control or register information have been transmitted from the SMJ320 serial port to the AIC. This signal can be used to interrupt a microprocessor upon the completion of serial communications. Also, this signal can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low after the first byte has been transmitted from the SMJ320 serial port to the AIC and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to differentiate between the two bytes as to which is first and which is second.

is held low during bit transmission. When FSR goes low, the SMJ320 serial port will begin receiving bits from the AIC via the DR pin of the AIC. The most significant DR bit will be present on DR before FSR Port Timing and Internal Timing Configuration diagrams.) FSR

via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE held low during bit transmission (see the Serial Port Timing and Internal Timing Configuration diagrams).

switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal Timing Configuration).

directly in either a differential or a single-ended configuration.

to this terminal.

initiates serial communications between the AIC and DSP. The reset function will initialize all AIC registers including the control register. After a negative-going pulse on RESET an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA’ and RA’, will be reset to 1. The control register bits will be reset as follows (see AIC DX data word format section). d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1 This initialization allows normal serial-port communication to occur between the AIC and the DSP.

DESCRIPTION

goes low. (See Serial

does not occur after secondary communication.

description, FSX is

, the AIC registers will be initialized to provide

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–3

TLC32040M ANALOG INTERFACE CIRCUIT

Terminal Functions (Continued)

NAME NO.

SHIFT CLK 10 O The shift clock signal is obtained by dividing the master clock signal frequency by four. This signal is used to clock

CC+

CC–

WORD/BYTE 13 I

I/O

the serial data transfers of the AIC, described in the WORD/BYTE description (see the Serial Port Timing and Internal Timing Configuration diagrams).

7 Digital supply voltage, 5 V ±5% 20 Positive analog supply voltage, 5 V ±5% 19 Negative analog supply voltage, –5 V ±5%

This terminal, in conjunction with a bit in the control register, is used to establish one of four serial modes. These four modes are described below.

AIC transmit and receive sections are operated asynchronously.

The following description applies when the AIC is configured to have asynchronous transmit and receive sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format), the transmit and receive sections will be asynchronous.

L Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit bytes.

The operation sequence is as follows (see Serial Port Timing diagrams)

1. FSX or FSR is brought low.

2. One 8-bit byte is transmitted or one 8-bit byte is received.

3. EODX or EODR is brought low.

4. FSX

5. One 8-bit byte is transmitted or one 8-bit byte is received.

6. EODX

7. FSX

H Serial port directly interfaces with the serial port of the SMJ32020, SMJ320C25, or SMJ320C30 and

communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams):

1. FSX

2. One 16-bit word is transmitted or one 16-bit word is received.

3. FSX 4 EODX or EODR emits a low-going pulse.

AIC transmit and receive sections are operated synchronously.

If the appropriate data bit in the control register is a 1, the transmit and receive sections will be configured to be synchronous. In this case, the band-pass switched-capacitor filter and the A/D conversion timing will be derived from TX Counter A, TX Counter B, and TA, TA’, and TB registers, rather than the RX Counter A, RX Counter B, and RA, RA’, and RB registers. In this case, the AIC FSX and FSR timing will be identical during primary data communication; however , FSR will not be asserted during secondary data communication since there is no new A/D conversion result. The synchronous operation sequences are as follows (see Serial Port Timing diagrams ).

L Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit bytes. The

operation sequence is as follows (see Serial Port Timing diagrams).

1. FSX or FSR are brought low.

2. One 8-bit byte is transmitted and one 8-bit byte is received.

3. EODX

4. FSX and FSR emit positive frame-sync pulse that are four shift-clock cycles wide.

5. One 8-bit byte is transmitted and one 8-bit byte is received.

6. EODX or EODR are brought high.

7. FSX or FSR are brought high.

H Serial port directly interfaces with the serial port of the SMJ32020, SMJ320C25, or SMJ320C30 and

communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams):

1. FSX

2. One 16-bit word is transmitted and one 16-bit word is received.

3. FSX and FSR are brought high.

4. EODX or EODR emit low-going pulses. Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port, with additional NOR and AND gates, will interface to two SN54299 serial-to-parallel shift registers. Interfacing the AIC to the SN54299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel data bus communications between the AIC and the digital signal processor. The operation sequence is the same as the above sequence (see Serial Port Timing diagrams).

or FSR emits a positive frame-sync pulse that is four shift-clock cycles wide.

or EODR is brought high.

or FSR is brought high.

or FSR is brought low. or FSR is brought high.

and EODR are brought low.

and FSR are brought low.

DESCRIPTION

4–4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ANALOG INTERFACE CIRCUIT

INTERNAL TIMING CONFIGURATION

TLC32040M

Master Clock

5.184 MHZ (1)

10.368 MHZ (2)

20.736 MHz (1)

41.472 MHz (2)

XTAL

Osc

Optional External Circuitry for Full-Duplex Modems

153.6 kHz Clock (1)

Divide

by 135

TMS320

DSP

Commercial

External

Front-End

Full-Duplex

Split-Band

Filters

TA Register

(5 Bits)

d0, d1 = 0,0 d0, d1 = 1, 1‡

TX Counter A [TA = 9 (1)] [TA = 18 (2)] (6 Bits)

RA Register

(5 Bits)

Divide by 4

TA’ Register

Adder/

Subtractor

(6 Bits)

d0, d1 = 0,1 d0, d1 = 1,0‡

RA’ Register

Adder/

Subtractor

(6 Bits)

(2s Compl)

576-kHz Pulses

(6 Bits)

(2s Compl)

Divide by 2

TB Register

(6 Bits)

TX Counter B TB = 40, 7.2 kHz TB = 36, 8.0 kHz TB = 30, 9.6 kHz TB = 20, 14.4 kHz TB = 15, 19.2 kHz

Divide by 2

RB Register

(6 Bits)

Shift Clock

1.296 MHz (1)

2.592 MHz (2)

Low-Pass Switched Cap Filter CLK = 288 kHz Square Wave

D/A Conversion Frequency

Band-Pass Switched Cap Filter CLK = 288 kHz Square Wave

d0, d1 = 0,0 d0, d1 = 1,1‡

RX Counter A [TA = 9 (1)] [TA = 18 (2)] (6 Bits)

SCF Clock Frequency =

†

Split-band filtering can alternatively be performed after the analog input function via software in the SMJ320.

‡

These control bits are described in the AIC DX data word format section.

d0, d1 = 0,1 d0, d1 = 1,0‡

576-kHz Pulses

RX Counter B RB = 40, 7.2 kHz RB = 36, 8.0 kHz RB = 30, 9.6 kHz RB = 20, 14.4 kHz RB = 15, 19.2 kHz

Master Clock Frequency

2 × Contents of Counter A

A/D Conversion Frequency

NOTE: Frequency 1, 20.736 MHz is used to show how 153.6 kHz (for a commercially available modem split-band filter clock), popular speech

and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as submultiples of the crystal oscillator frequency . Since these derived frequencies are synchronous submultiples of the crystal frequency, aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages. Frequency 2, 41.472 MHz is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital signal processors

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–5

TLC32040M ANALOG INTERFACE CIRCUIT

explanation of internal timing configuration

All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing the master clock input signal frequency by four.

SCF Clock Frequency

Conversion Frequency

Shift Clock Frequency

TX Counter A and TX Counter B, which are driven by the master clock signal, determine the D/A conversion timing. Similarly, RX Counter A and RX Counter B determine the A/D conversion timing. In order for the switched-capacitor low-pass and band-pass filters to meet their transfer function specifications, the frequency of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are not 288 kHz , the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of master clock frequency and TX Counter A and RX Counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can then be divided by TX Counter B and RX Counter B to establish the D/A and A/D conversion timings.

TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX Counter B are reloaded every A/D conversion period. TX Counter B and RX Counter B are loaded with the values in the TB and RB Registers, respectively . V ia software control, TX Counter A can be loaded with either TA Register, the T A Register less the T A ’ Register , or the T A Register plus the T A ’ Register . By selecting the T A Register less the T A’ Register option, the upcoming conversion timing will occur earlier by an amount of time that equals TA’ times the signal period of the master clock. By selecting the TA Register plus the TA’ Register option, the upcoming conversion timing will occur later by an amount of time that equals T A’ times the signal period of the master clock. Thus the D/A conversion timing can be advanced or retarded. An identical ability to alter the A/D conversion timing is provided. In this case, however, the RX Counter A can be programmed via software control with the RA Register, the RA Register less the RA’ Register, or the RA Register plus the RA’ Register.

Master Clock Frequency

2 Contents of Counter A

SCF Clock Frequency

Contents of Counter B

Master Clock Frequency

The ability to advance or retard conversion timing is particularly useful for modem applications. This feature allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance signal-tonoise performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies.

If the transmit and receive sections are configured to be synchronous (see the WORD/BYTE Terminal Functions table), then both the low-pass and band-pass switched-capacitor filter clocks are derived from TX Counter A. Also, both the D/A and A/D conversion timing are derived from TX Counter A and TX Counter B. When the transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter B, RA Register, RA’ Register, and RB Registers are not used.

4–6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description in the

TLC32040M

ANALOG INTERFACE CIRCUIT

AIC DR or DX word bit pattern

A/D or D/A MSB, 1st bit sent 1st bit sent of 2nd byte A/D or D/A LSB

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15

AIC DX data word format section

d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d2 d1 d0 COMMENTS

Primary DX serial communication protocol ← d15 (MSB) through d2 go to the D/A →

converter register

← d15 (MSB) through d2 go to the D/A →

converter register and RA + RA’ register values. The TX and RX Counter

← d15 (MSB) through d2 go to the D/A →

converter register and RA - RA’ register values. The TX and RX Counter

← d15 (MSB) through d2 go to the D/A →

converter register RA register values. The TX and RX Counter Bs are

NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (Primary Communications) to the AIC will initiate

Secondary Communications upon completion of the Primary Communications. Upon completion of the Primary Communication, FSX Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. in this manner, the Secondary Communication, if initiated, is interleaved between successive Primary Communications. This interleaving prevents the Secondary Communication from interfering with the Primary Communications and DAC timing, thus preventing the AIC from skipping a DAC output. It is important to note that in the synchronous mode, FSR

will remain high for four shift-clock cycles and will then go low and initiate the

0 0 The TX and RX Counter As are loaded with the TA and

RA register values. The TX and RX Counter Bs areloaded with TB and RB register values.

0 1 The TX and Counter As are loaded with the TA + TA’

Bs are loaded with the TB and RB register values. NOTE: d1 = 0, d0 = 1 will cause the next D/A and A/D conversion periods to be changed by the addition of TA ’ and RA’ master clock cycles, in which TA’ and RA ’ can be positive or negative or zero. Please refer to T able 1. AIC Responses to Improper Conditions.

1 0 The TX and Counter As are loaded with the TA - TA’

Bs are loaded with the TB and RB register values. NOTE: d1 = 0, d0 = 1 will cause the next D/A and A/D conversion periods to be changed by the subtraction of TA’ and RA’ Master Clock cycles, in which T A’ and RA can be positive or negative or zero. Please refer to Table 1. AIC Responses to Improper Conditions.

1 1 The TX and Counter As are loaded with the TA and

loaded with the TB and RB register values. After a delay of four shift-clock cycles, a secondary transmission will immediately follow to program the AIC to operate in the desired configuration.

will not be asserted during Secondary Communications.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–7

TLC32040M ANALOG INTERFACE CIRCUIT

secondary DX serial communication protocol

Control Register

reset function

A reset function is provided to initiate serial communications between the AIC and DSP. The reset function will initialize all AIC registers, including the control register. After power has been applied to the AIC, a negative-going pulse on RESET rate for a 5.184-MHz master clock input signal. The AIC, except the control register, will be initialized as follows (see AIC DX data word format section):

will initialize the AIC registers to provide an 8-kHz A/D and D/A conversion

TA 9 TA’ 1

TB 24

RA 9 RA’ 1 RB 24

d3 = 0/1 disables/enables the loopback function d4 = 0/1 disables/enables the AUX IN+ and AUX IN– terminals d5 = 0/1 asynchronous/synchronous transmit and receive sections d6 = 0/1 gain control bits (see gain control section) d7 = 0/1 gain control bits (see gain control section)

INITIALIZED

VALUE (HEX)

The control register bits will be reset as follows (see AIC DX data word format section):

d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1

This initialization allows normal serial port communications to occur between the AIC and DSP. If the transmit and receive sections are configured to operate synchronously and the user wishes to program different conversion rates, only the T A, TA ’, and TB registers need to be programmed, since both transmit and receive timing are synchronously derived from these registers (see the T erminal Functions table and AIC DX data word format section).

The circuit shown below provides a reset on power up when power is applied in the sequence given under power-up sequence. The circuit depends on the power supplies’ reaching their recommended values a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.

CC+

RESET

CC–

5 V

200 kΩ

0.5 µF

–5 V

4–8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040M

ANALOG INTERFACE CIRCUIT

power-up sequence

To ensure proper operation of the AIC and as a safeguard against latch-up, it is recommended that a Schottky diode with a forward voltage less than or equal to 0.4 V be connected from V In the absence of such a diode, power should be applied in the following sequence: ANLG GND and DGTL GND, V

CC–

, then V

and VDD. Also, no input signal should be applied until after power up.

CC+

AIC responses to improper conditions

The AIC has provisions for responding to improper conditions. These improper conditions and the response of the AIC to these conditions are presented in Table 1 below.

AIC register constraints

The following constraints are placed on the contents of the AIC registers:

to ANLG GND (see Figure 16).

CC–

1. TA register must be ≥ 4 in WORD mode (WORD/BYTE

2. TA register must be ≥ 5 in BYTE

mode (WORD/BYTE = low).

= high).

3. TA’ register can be either positive, negative, or zero.

4. RA register must be ≥ 4 in WORD mode (WORD/BYTE

5. RA register must be ≥ 5 in BYTE

mode (WORD/BYTE = low).

= high).

6. RA’ register can be either positive, negative, or zero.

7. (TA register ± TA’ register) must be > 1.

8. (RA register ± RA’ register) must be > 1.

9. TB register must be > 1.

Table 1. AIC Responses to Improper Conditions

IMPROPER CONDITION AIC RESPONSE

TA register + TA’ register = 0 or 1 TA register – TA’ register = 0 or 1

TA register + TA’ register < 0 MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A,

RA register + RA’ register = 0 or 1 RA register – RA’ register = 0 or 1

RA register + RA’ register = 0 or 1 MODULO 64 arithmetic is used to ensure that a positive value is loaded into the RX Counter

TA register = 0 or 1 RA register = 0 or 1

TA register < 4 in WORD mode TA register < 5 in BYTE RA register < 4 in WORD mode RA register < 5 in BYTE

TB register = 0 or 1 Reprogram TB register with 24 HEX RB register = 0 or 1 Reprogram TB register with 24 HEX AIC and DSP cannot communicate Hold last DAC output

mode

Reprogram TX Counter A with TA register value

i.e., TA register + TA’ register + 40 HEX is loaded into TX Counter A. Reprogram RX Counter A with RA register value

A, i.e., RA register + RA’ register + 40 HEX is loaded into RX Counter A. AIC is shutdown.

The AIC serial port no longer operates.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–9

TLC32040M ANALOG INTERFACE CIRCUIT

improper operation due to conversion times being too close together

If the difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the AIC operates improperly . In this situation, the second D/A conversion frame sync occurs too quickly , and there is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly programmed or if the A + A’ register or A – A’ register result is too small. When incrementally adjusting the conversion period via the A + A ’ register options, the designer should be careful not to violate this requirement (see following diagram).

Frame Sync,

, or FSR

FSX

Ongoing Conversion

t2 – t1 ≥ 1/19.2 kHz

asynchronous operation – more than one receive frame sync occurring between two transmit frame syncs

When incrementally adjusting the conversion period via the A + A ’ or A – A ’ register options, a specific protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC during an FSX

frame sync. The ongoing conversion period is then adjusted. However, either Receive Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental conversion period adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between t and t2, the receive conversion period adjustment will be performed during Receive Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B. The adjustment command only adjusts one transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive conversion periods, another command must be issued during a subsequent FSX (see figure below).

frame

FSX

Transmit Conversion Period

FSR

Receive

Conversion

Period A

Receive

Conversion

Period B

asynchronous operation – more than one transmit frame sync occurring between two receive frame syncs

When incrementally adjusting the conversion period via the A + A ’ or A – A ’ register options, a specific protocol is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment is performed near the end of the conversion period. The command to use the incremental conversion period adjust options is sent to the AIC during an FSX adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as shown in the figure on the following page. If the adjustment command is issued during Transmit Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t not sufficient time between t

and t2, Receive Conversion Period B will be adjusted. The receive portion of an

adjustment command may be ignored if the adjustment command is sent during a receive conversion period, which is already being or will be adjusted due to a prior adjustment command. For example, if adjustment

frame sync. The ongoing transmit conversion period is then

and t2. If there is

4–10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040M

ANALOG INTERFACE CIRCUIT

commands are issued during Transmit Conversion Periods A, B, and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is ignored since it was issued during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B adjustment command.

FSX

Transmit

Conversion

Period C

FSR

Receive Conversion Period A

Transmit

Conversion

Period A

Transmit

Conversion

Period B

Receive Conversion Period B

asynchronous operation – more than one set of primary and secondary DX serial communication occurring between two receive frame sync (see AIC DX data word format section)

The T A, T A ’, TB, and control register information that is transmitted in the secondary communications is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t t

, the T A, RA ’, and RB register information, which is sent during T ransmit Conversion Period A, will be applied

to Receive Conversion Period A. Otherwise, this information will be applied during Receive Conversion Period B. If RA, RA’, and RB register information has already been received and is being applied during an ongoing conversion period, any subsequent RA, RA ’, or RB information that is received during this receive conversion period will be disregarded (see diagram below).

Primary Secondary

FSX

Primary Secondary

and

FSR

Transmit

Conversion

Period A

Receive Conversion

Period A

Transmit

Conversion

Period B

Receive Conversion Period B

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Transmit

Conversion

Period C

4–11

TLC32040M ANALOG INTERFACE CIRCUIT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Supply voltage range, V Output voltage range, V Input voltage range, V

Digital ground voltage range –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package 300°C. . . . . . . . . . . . . . . . . . . . .

NOTE 1: Voltage values for maximum ratings are with respect to V

recommended operating conditions

Supply voltage, V Supply voltage, V Digital supply voltage, VDD (see Note 2) 4.75 5 5.25 V Digital ground voltage with respect to ANLG GND, DGTL GND 0 V Reference input voltage, V High-level input voltage, V Low-level input voltage, VIL (see Note 3) –0.3 0.8 V Maximum peak output voltage swing across RL at OUT+ or OUT– (single ended) (see Note 4) ±3 V Load resistance at OUT+ and/or OUT–, R Load capacitance at OUT+ and/or OUT–, C MSTR CLK frequency (see Note 5) 0.075 5 10.368 MHz Analog input amplifier common-mode input voltage (see Note 6) ±1.5 V A/D or D/A conversion rate 20 kHz Operating free-air temperature, T

NOTES: 2. V oltages at analog inputs and outputs, REF , V

and outputs and VDD are with respect to the DGTL GND terminal.

3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels and temperature only.

4. This applies when RL ≥ 300 Ω and offset voltage = 0.

5. The band-pass and low-pass switched-capacitor filter response specifications apply only when the switched-capacitor clock frequency is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of switched-capacitor filter clock frequency to 288 kHz.

6. This range applies when (IN+ – IN–) or (AUX IN+ – AUX IN–) equals ±6 V.

(see Note 2) 4.75 5 5.25 V

CC+

(see Note 2) –4.75 –5 –5.25 V

CC–

ref(ext)

(see Note 1) –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC+

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC–

PARAMETER MIN NOM MAX UNIT

(see Note 2) 2 4 V

2 VDD+0.3 V

CC+

, and V

, are with respect to the ANLG GND terminal. Voltages at digital inputs

CC–

300 Ω

100 pF

–55 125 °C

4–12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040M

ANALOG INTERFACE CIRCUIT

electrical characteristics over recommended operating free-air temperature range, V

= –5 V, VDD = 5 V (unless otherwise noted)

CC –

total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

CC+

CC–

ref

receive amplifier input

CMRR

NOTE 7: The test condition is a 0-dBm, 1-kHz input signal with an 8-kHz conversion rate.

transmit filter output

High-level output voltage VDD = 4.75 V, IOH = –300 µA 2.4 V Low-level output voltage VDD = 4.75 V, IOL = 2 mA 0.9 V Supply current from V Supply current from V Supply current from V Internal reference output voltage 2.9 3.3 V Temperature coefficient of internal

Vref

reference voltage Output resistance at REF 100 kΩ

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

A/D converter offset error (filters bypassed) 25 65 mV A/D converter offset error (filters in) 25 65 mV Common-mode rejection ratio at IN+, IN –,

or AUX IN+, AUX IN– Input resistance at IN+, IN–

or AUX IN+, AUX IN –, REF

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Output offset voltage at OUT+ or OUT– (single ended relative to ANLG GND)

Maximum peak output voltage swing between OUT+ and OUT– (differential output)

CC+ CC– DD

MSTR CLK

= 5.184 MHz 7 mA

200 ppm/ °C

See Note 7 35 55 dB

100 kΩ

15 75 mV

RL ≥ 300 Ω ±6 V

= 5 V,

CC +

40 mA

–40 mA

system distortion specifications, SCF clock frequency = 288 kHz

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Attenuation of second harmonic of Single ended VI = –0.5 dB to –24 dB referred to V A/D input signal Differential Single-ended tested at 25°C, See Note 8 62 70 Attenuation of third and higher Single ended VI = –0.5 dB to –24 dB referred to V harmonics of A/D input signal Differential Single-ended tested at 25°C, See Note 8 57 65 Attenuation of second harmonic of Single ended VI = –0 dB to –24 dB referred to V D/A input signal Differential See Note 8 62 70 Attenuation of third and higher Single ended VI = –0 dB to –24 dB referred to V harmonics of D/A input signal Differential See Note 8 57 65

†

All typical values are at TA = 25°C.

NOTE 8: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to V

300 Ω.

, 62 70

ref

, 57 65

ref

, 70

ref

, 65

ref

). The load impedance for the DAC is

ref

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–13

TLC32040M ANALOG INTERFACE CIRCUIT

electrical characteristics over recommended operating free-air temperature range, V

= –5 V, VDD = 5 V (unless otherwise noted) (continued)

CC –

CC +

= 5 V,

A/D channel signal-to-distortion ratio

†

PARAMETER

A/D channel signal-to-distortion ratio VI = –30 dB to –24 dB 44 50 56 dB

†

AV is the programmable gain of the input amplifier.

‡

A value > 58 is overrance and signal clipping occurs over range.

TEST CONDITIONS

(see Note 8)

VI = –6 dB to –0.5 dB 58 >58 VI = –12 dB to –6 dB 58 58 >58 VI = –18 dB to –12 dB 56 58 58 VI = –24 dB to –18 dB 50 56 58

VI = –36 dB to –30 dB 38 44 50 VI = –42 dB to –36 dB 32 38 44 VI = –48 dB to –42 dB 26 32 38 VI = –54 dB to –48 dB 20 26 32

AV = 1

MIN MAX MIN MAX MIN MAX

AV = 2

‡

†

>58

AV = 4

‡ ‡

†

UNIT

D/A channel signal-to-distortion ratio

PARAMETER

D/A channel signal-to-distortion ratio VI = –30 dB to –24 dB 44 dB

NOTE 8: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is

300 Ω.

TEST CONDITIONS

(see Note 8)

VI = –6 dB to 0 dB 58 VI = –12 dB to –6 dB 58 VI = –18 dB to –12 dB 56 VI = –24 dB to –18 dB 50

VI = –36 dB to –30 dB 38 VI = –42 dB to –36 dB 32 VI = –48 dB to –42 dB 26 VI = –54 dB to –48 dB 20

MIN MAX UNIT

gain and dynamic range

PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT

Absolute transmit gain tracking error while transmitting into 300 Ω

Absolute receive gain tracking error

Absolute gain of the A/D channel

Absolute gain of the D/A channel

All typical values are at TA = 25°C.

NOTE 9. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 db relative to V

–48-dB to 0-dB signal range, See Note 9

Signal input is a –0.5 dB, 1-kHz sinewave

Signal input is a 0-dB, 1-kHz sinewave

ref

±0.05 ±0.15 dB

0.2 dB

–0.3 dB

4–14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040M

ANALOG INTERFACE CIRCUIT

electrical characteristics over recommended operating free-air temperature range, V

= –5 V, VDD = 5 V (unless otherwise noted) (continued)

CC –

CC +

= 5 V,

power supply rejection and crosstalk attenuation

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

or V

CC+

rejection ratio, receive channel f = 30 kHz to 50 kHz measured at DR (ADC output) 45 V

or V

CC+

ratio, transmit channel (single ended) f = 30 kHz to 50 kHz measured at OUT+ 45

Crosstalk attenuation (differential)

supply voltage f = 0 to 30 kHz Idle channel, Supply signal at 200 mV p-p 30

CC–

supply voltage rejection f = 0 to 30 kHz Idle channel, Supply signal at 200 mV p-p 30

CC–

Transmit-to-receive DX = 00000000000000 70 80 Receive-to-transmit Inputs grounded 70 80

delay distortion, SCF clock frequency = 288 kHz ± 2%, input (IN+ – IN –) is ± 3-V sinewave

Please refer to filter response graphs for delay distortion specifications.

band-pass filter transfer function (see curves), SCF clock frequency = 288 kHz ± 2%, input (IN + – IN–) is a ±3-V sinewave (see Note 9)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f = 100 Hz –42 f = 170 Hz –25

Filter gain (see Note 10) Input signal reference is 0 dB 300 Hz ≤ f ≤ 3.4 kHz ±0.5 dB

f = 4 kHz –16 f ≥ 4.6 kHz –58

low-pass filter transfer function, SCF clock frequency = 288 kHz ±2% (see Note 10)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f ≤ 3.4 kHz ±0.5

Filter gain (see Note 11)

Output signal reference is 0 dB

f = 3.6 kHz –4 f = 4 kHz –30 f ≥ 4.4 kHz –58

serial port

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

†

All typical values are at TA = 25°C.

NOTES: 9. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (–0 db relative to V

High-level output voltage IOH = –300 µA 2.4 V Low-level output voltage IOL = 2 mA 0.4 V Input current ±10 µA Input capacitance 15 pF Output capacitance 15 pF

10. The above filter specifications are for a switched-capacitor filter clock range of 288 kHz ±2%. For switched-capacitor filter clocks

at frequencies other than 288 kHz ± 2%, the filter response is shifted by the ratio of switched-capacitor filter clock frequency to

288 kHz.

11. The filter gain outside of the pass band is measured with respect to the gain at 1 kHz. The filter gain within the pass band is measured with respect to the average gain within the pass band. The pass bands are 300 to 3400 Hz and 0 to 3400 Hz for the band pass and low-pass filters respectively.

ref

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–15

TLC32040M ANALOG INTERFACE CIRCUIT

operating characteristics over recommended operating free-air temperature range, V

= –5 V, VDD = 5 V

CC –

CC +

= 5 V,

noise (measurement includes low-pass and band-pass switched-capacitor filters)

PARAMETER TEST CONDITIONS TYP†MAX UNIT

Single ended 200 µV rms

Transmit noise DX input = 00000000000000, constant input code 300 500 µV rms

Receive noise (see Note 12) Inputs grounded, gain = 1

NOTE 12. This noise is referred to the input with a buffer gain of one. If the buffer gain is two or four , the noise figure will be correspondingly reduced.

The noise is computed by statistically evaluating the digital output of the A/D converter.

Differential

20 dBrnc0

300 475 µV rms

20 dBrnc0

timing requirements

serial port recommended input signals

PARAMETER MIN MAX UNIT

c(MCLK)

r(MCLK)

f(MCLK)

su(DX)

th(DX)

NOTE 13. RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached their

Master clock cycle time 100 192 ns Master clock rise time 10 ns Master clock fall time 10 ns Master clock duty cycle 42% 58% RESET pulse duration (see Note 13) 800 ns DX setup time before SCLK↓ 28 ns DX hold time before SCLK↓ t

recommended values.

c(SCLK)/4

serial port – AIC output signals

c(SCLK)

f(SCLK

r(SCLK)

d(CH-FL)

d(CH-FH)

d(CH-DR)

dw(CH-EL)

dw(CH-EH)

f(EODX)

f(EODR)

db(CH-EL)

db(CH-EH)

d(MH-SL)

d(MH-SH)

†

All typical values are at TA = 25°C.

Shift clock (SCLK) cycle time 400 ns

) Shift clock (SCLK) fall time 50 ns

Shift clock (SCLK) rise time 50 ns Shift clock (SCLK) duty cycle 50% Delay from SCLK↑ to FSR/FSX↓ 260 ns Delay from SCLK↑ to FSR/FSX↑ 260 ns DR valid after SCLK↑ 316 ns Delay from SCLK↑ to EODX/EODR↓ in WORD mode 280 ns Delay from SCLK↑ to EODX/EODR↑ in WORD mode 280 ns EODX fall time 15 ns EODR fall time 15 ns Delay from SCLK↑ to EODX/EODR↓ in BYTE mode 100 ns Delay from SCLK↑ to EODX/EODR↑ in BYTE mode 100 ns Delay from MSTR CLK ↑ to SCLK↓ 65 105 ns Delay from MSTR CLK ↑ to SCLK↓ 65 ns

PARAMETER MIN TYP†MAX UNIT

4–16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040M

ANALOG INTERFACE CIRCUIT

IN +

IN –

(Analog Input Signal Required for Full-Scale A/D Conversion)

Table 2. Gain Control Table

INPUT CONFIGURATIONS

Differential configuration 1 1 Analog input = IN+ – IN– 0 0

= AUX IN+ – AUX IN– 1 0 ±3 V Full scale

Single-ended configuration 1 1 Analog input = IN+ – ANLG GND 0 0

= AUX IN+ – ANLG GND 1 0 ±3 V Full scale

†

In this example, V

0.1 dB below full scale.

–

Rfb = R for d6 = 1, d7 = 1

Rfb = 2R for d6 = 1, d7 = 0 Rfb = 4R for d6 = 0, d7 = 1

is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not exceed

ref

–

d6 = 0, d7 = 0

CONTROL REGISTER BITS A/D CONVERSION

d6 d7 RESULT

0 1 ±1.5 V Full scale

AUX IN +

To MUX

AUX IN –

ANALOG INPUT

±6 V

Rfb = R for d6 = 1, d7 = 1

Rfb = 2R for d6 = 1, d7 = 0 Rfb = 4R for d6 = 0, d7 = 1

†

–

d6 = 0, d7 = 0

–

Full scale

Half scale±3 V

To MUX

Figure 1. IN+ and IN– Gain Figure 2. AUX IN+ and AUX IN–

Control Circuitry Gain Control Circuitry

(sin x)/x correction section

The AIC does not have (sin x)/x correction circuitry after the digital-to-analog converter. (sin x)/x correction can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are shown on the next page, are typical of the numerical correction accuracy that can be achieved for sample rates of interest. The filter requires only seven instruction cycles per sample on the SMJ320 DSPs. With a 200-ns instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively . This correction will add a slight amount of group delay at the upper edge of the 300 – 3000-Hz band.

(sin x)/x roll-off for a zero-order hold function

The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the various sampling rates is shown in the following table.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–17

TLC32040M ANALOG INTERFACE CIRCUIT

Table 3. (sin x)/x Roll-Off

sin π f/f

fs(Hz)

7200 8000

9600 14400 19200

20 log

(f = 3000 Hz)

(dB)

–2.64

–2.11

–1.44 –0.63 –0.35

Note that the actual AIC (sin x)/x roll-off will be slightly less than the above figures because the AIC has less than a 100% duty cycle hold interval.

correction filter

To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter shown below, is recommended.

π f/f

u(i +

(1– p1)P2

The difference equation for this correction filter is:

Yi)1+

p2(1*p1) (ui)1))

p1 Y

i where the constant p1 determines the pole locations. The resulting squared magnitude transfer function is:

H (f)

1 – 2p1 cos(2 π f/fs) + p1

(1 – p1)

y(i +

–1

4–18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040M

ANALOG INTERFACE CIRCUIT

correction results

T able 4 below shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz sampling rates.

Table 4. Optimum P Values

f (Hz)

300 600

900 1200 1500 1800 2100 2400 2700 3000

ERROR (dB) fs = 8000 Hz p1 = –0.14813 p2 = 0.9888

–0.099 –0.089 –0.054 –0.002

0.041

0.079

0.100

0.091 –0.043 –0.102

ERROR (dB) fs = 9600 Hz p1 = –0.1307 p2 = 0.9951

–0.043 –0.043

0 0 0

0.043

0.043 0

–0.043

SMJ320 software requirements

The digital correction filter equation can be written in state variable form as follows:

Y = k1Y + k2U

where k1 equals p1 (from the preceding page), k2 equals (1 – p1)p2 (from the preceding page), Y is the filter state, and U is the next I/O sample. The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the SMJ320 processor page pointer and memory configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with the following program:

ZAC LT K2 MPY U LTA K1 MPY Y APAC SACH (dma), (shift)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–19

TLC32040M ANALOG INTERFACE CIRCUIT

PARAMETER MEASUREMENT INFORMATION

SHIFT CLK

d(CH-FL)

FSR

, FSX

EODR, EODX

2 V 2 V 2 V 2 V 2 V 2 V 2 V

D15 D8

su(DX)

f(SCLK)

0.8 V 0.8 V

0.8 V

2 V

D14 D13 D9

0.8 V

D15 D14 D13 D9 D8

d(CH-DR)

h(DX)

r(SCLK)

d(CH-FH)

2 V 2 V

0.8 V

d(CH-FL)

0.8 V

(a) BYTE

Don’t Care

db(CH-EL)

-MODE TIMING

D7 D6 D2 D1

c(SCLK)

2 V

2 V2 V2 V

c(SCLK)

d(CH-FH)

D2D6 D1 D0

db(CH-EH)

SHIFT CLK

0.8 V

d(CH-FH)

2 V

FSX

, FSR

0.8 V

d(CH-FL)

0.8 V

d(CH-DR)

2 V

EODX, EODR

MSTR CLK

SHIFT CLK

D15 D14 D13 D12 D11 D2 D1 D0

su(DX)

h(DX)

dw(CH-EL)

0.8 V

(b) WORD-MODE TIMING

d(MH-SH)

Figure 3. Serial Port Timing

D0D1D2D11D12D13D14D15

d(MH-SL)

Don’t Care

dw(CH-EH)

2 V

4–20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ANALOG INTERFACE CIRCUIT

PARAMETER MEASUREMENT INFORMATION

TLC32040M

SMJ320C10

DEN

A0/PA0 A1/PA1

A2/PA2

DO–D15

CLK OUT

INT

SN54LS299

B C

SN54LS138

DO–D15

D8–D15

DO–D7

S1 G2

S0 G1

A–H

SN54LS299 S1

G2 S0 G1

A–H

CLK

QH′

SN54LS74

Figure 4. SMJ320C10/SMJ320C15/SMJ320E15-TLC32040M Interface Circuit

FSX

SHIFT CLK

MSTR CLK EODX

CLK OUT

DEN

S0, G1

D0–D15

CLK OUT

SN74LS138 Y1

SN74LS299 CLK

D0–D15

Valid

(a) IN INSTRUCTION TIMING

Valid

(b) OUT INSTRUCTION TIMING

Figure 5. SMJ320C10/SMJ320C15/SMJ320E15-TLC32040M Interface TIming

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–21

TLC32040M

ÎÎÎÎ

†

ANALOG INTERFACE CIRCUIT

–10

TYPICAL CHARACTERISTICS

AIC TRANSMIT CHANNEL FILTER

0.3

Magnitude

0.25

0.2

–20

–30

–40

–50

Magnitude – dB

–60

–70

–80

–90

†

Test conditions are V input = ±3-V sinewave, and TA = 25°C.

NOTES: A. Maximum relative delay (0 Hz to 600 Hz) = 125 µs

B. Maximum relative delay (600 Hz to 3000 Hz) = ±50 µs C. Absolute delay (600 Hz to 3000 Hz) = 700 µs

CC+

, V

CC–

See Note B

0.5 1.5 2.5 3.5 4.5

012345

Normalized Frequency – kHz ×

, and VDD within recommended operating conditions, SCF clock f = 288 kHz ±2%,

Group Delay

See Note A

See Note C

Figure 6

SCF Clock Frequency

288 kHz

0.15

0.1

0.05 0

0.05

0.1

0.15

0.2

Relative Group Delay – ms

4–22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

TLC32040 RECEIVE CHANNEL FILTER

See Note A

Magnitude

TLC32040M

ANALOG INTERFACE CIRCUIT

0.35

0.3

–10

–20 –30

–40

–50

Magnitude – dB

–60

–70 –80

–90

012345

Normalized Frequency – kHz ×

†

Test conditions are V input = ±3-V sinewave, and TA = 25°C.

NOTES: A. Maximum relative delay (200 Hz to 600 Hz) = 3350 µs

B. Maximum relative delay (600 Hz to 3000 Hz) = ±50 µs C. Absolute delay (600 Hz to 3000 Hz) = 1230 µs

CC+

, V

, and VDD within recommended operating conditions, SCF clock f = 288 kHz ±2%,

CC–

Group Delay

See Note B

See Note C

Figure 7

SCF Clock Frequency

288 kHz

0.25

0.2

0.15

0.1

0.05 0

Relative Group Delay – ms

0.05

0.1

0.15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–23

TLC32040M ANALOG INTERFACE CIRCUIT

A/D SIGNAL-TO-DISTORTION RATIO

INPUT SIGNAL

1-kHz Input Signal With an 8-kHz Conversion Rate

Gain = 4X

Signal-to-Distortion Ratio – dB

–50 –40 –3

Input Signal Relative to V

TYPICAL CHARACTERISTICS

Gain = 1X

–20 –10 0

– dB

ref

0.5

0.4

0.3

0.2

0.1

–0.1

Gain Tracking – dB

–0.2 –0.3

–0.4 –0.5

–50

†

A/D GAIN TRACKING

(GAIN RELATIVE TO GAIN

AT 0-dB INPUT SIGNAL)

1-kHz Input Signal 8-kHz Conversion Rate

–40

Input Signal Relative to V

ref

100–10–20–30

– dB

Figure 8 Figure 9

D/A CONVERTER SIGNAL-TO-DISTORTION RATIO

INPUT SIGNAL

100

1-kHz Input Signal into 600 Ω

8-kHz Conversion Rate

70 60

50 40

Signal-to-Distortion Ratio – dB

–50

Input Signal Relative to V

ref

– dB

D/A GAIN TRACKING

(GAIN RELATIVE TO GAIN

AT 0-dB INPUT SIGNAL)

1.0

1-kHz Input Signal into 600 Ω

0.8 8-kHz Conversion Rate

0.6

0.4

0.2

–0.2

Gain Tracking – dB

–0.4

–0.6

–0.8

–1

100–10–20–30–40

–50

Input Signal Relative to V

ref

– dB

100–10–20–30–40

4–24

Figure 10 Figure 11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

†

Test conditions are V

CC+

ANALOG INTERFACE CIRCUIT

, V

, and VDD within recommended operating conditions SCF clock f = 288 kHz ±2%, and TA = 25°C.

CC–

TLC32040M

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–25

TLC32040M ANALOG INTERFACE CIRCUIT

TYPICAL CHARACTERISTICS

ATTENUATION OF SECOND HARMONIC OF A/D INPUT

INPUT SIGNAL

100

90 80

70 60

50 40

30 20

Attenuation of Second Harmonic – dB

1-kHz Input Signal

8-kHz Conversion Rate

–50 –40 –30 –20 –10 0 10

Input Signal Relative to V

ref

– dB

Figure 12 Figure 13

†

ATTENUATION OF THIRD HARMONIC OF A/D INPUT

INPUT SIGNAL

100

1-kHz Input Signal 8-kHz Conversion Rate

90 80

70 60

50 40

30 20

Attenuation of Third Harmonic – dB

–50

Input Signal Relative to V

ref

– dB

100–10–20–30–40

ATTENUATION OF SECOND HARMONIC OF D/A INPUT

INPUT SIGNAL

100

1-kHz Input Signal into 600 Ω 8-kHz Conversion Rate

90 80

70 60

50 40

30 20

Attenuation of Second Harmonic – dB

–50

Input Signal Relative to V

ref

– dB

100–10–20–30–40

Figure 14 Figure 15

ATTENUATION OF THIRD HARMONIC OF D/A INPUT

INPUT SIGNAL

100

1-kHz Input Signal into 600 Ω

8-kHz Conversion Rate

70 60

50 40

30 20

Attenuation of Third Harmonic – dB

–50

–40 –30 –20 –10 0 10

Input Signal Relative to V

ref

– dB

†

Test conditions are V

4–26

CC+

, V

, and VDD within recommended operating conditions SCF clock f = 288 kHz ±2%, and TA = 25°C.

CC–

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ANALOG INTERFACE CIRCUIT

APPLICATION INFORMATION

CLKOUT

FSX

TMS32020/C25

†

Thomson Semiconductors

FSR

CLKR CLKX

MSTR CLK FSX DX FSR DR SHIFT CLK

TLC32040/TLC32041

TLC32042

CC+ REF

ANLG GND

CC–

DGTL GND

Figure 16. AIC Interface to SMJ32020/C25 Showing Decoupling Capacitors and Schottky Diode

C = 0.2 µF, Ceramic

†

BAT 42

0.1 µF

TLC32040M

5 V

–5 V

5 V

†

PRINCIPLES OF OPERATION

analog input

Two sets of analog inputs are provided. Normally, the IN + and IN – input set is used; however, the auxiliary input set, AUX IN+ and AUX IN–, can be used if a second input is required. Each input set can be operated in either differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain for the IN+, IN–, AUX IN+, and AUX IN– inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either input circuit can be selected via software control. It is important to note that a wide dynamic range is assured by the differential internal analog architecture and by the separate analog and digital voltage supplies and grounds.

A/D band-pass filter, A/D band-pass filter clocking, and A/D conversion timing

The A/D band-pass filter can be selected or bypassed via software control. The frequency response of this filter is presented in the following pages. This response results when the switched-capacitor filter clock frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz.

The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many options for attaining a 288-kHz band-pass switched-capacitor filter clock. These sections indicate that RX Counter A can be programmed to give a 288-kHz band-pass switched-capacitor filter clock for several master clock input frequencies.

The A/D conversion rate is then attained by frequency dividing the 288-kHz band-pass switched-capacitor filter clock with RX Counter B. Thus unwanted aliasing is prevented because the A/D conversion rate is an integral submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously locked.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–27

TLC32040M ANALOG INTERFACE CIRCUIT

PRINCIPLES OF OPERATION

A/D converter performance specifications

Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter operating characteristics section of this data sheet. The design of the A/D converter circuitry with switchedcapacitor techniques provides an inherent sample and hold.

analog output

The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs are brought out of the integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads directly in either a differential or single-ended configuration.

D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing

The frequency response of this filter is presented in the following pages. This response results when the low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.

The D/A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with TX Counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.

asynchronous versus synchronous operation

If the transmit section of the AIC (low-pass filter and DAC) and receive section (band-pass filter and ADC) are operated asynchronously, the low-pass and band-pass filter clocks are independently generated from the master clock signal. Also, the D/A and A/D conversion rates are independently determined. If the transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass and band-pass filters. In synchronous operation, the A/D conversion timing is derived from, and is equal to, the D/A conversion timing. (See description of WORD/BYTE

in the Terminal Functions table.)

D/A converter performance specifications

Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter operating characteristics section of the data sheet. The D/A converter has a sample and hold that is realized with a switched-capacitor ladder.

system frequency response correction

(Sin x)/x correction circuitry is performed in digital signal processor software. The system frequency response can be corrected via DSP software to 0.1-dB accuracy to a band-edge of 3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, which requires only seven SMJ320 instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1% and 1.3% for sampling rates of 8 and 9.6 kHz, respectively [see the (sin x)/x correction section for more details].

4–28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC32040M

ANALOG INTERFACE CIRCUIT

PRINCIPLES OF OPERATION

serial port

The serial port has four possible modes that are described in detail in the terminal functions table. These modes are briefly described below and in the description for terminal 13, WORD/BYTE

1. The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with the DSP in two 8-bit bytes.

2. The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with the SMJ32020, SMJ320C25, and the SMJ320C30.

3. The transmit and receive sections are operated synchronously, and the serial port interfaces directly with the DSP in two 8-bit bytes.

4. The transmit and receive sections are operated synchronously, and the serial port interfaces directly with the SMJ32020, SMJ320C25, SMJ302C30, or two SN54299 serial-to-parallel shift registers, which can then interface in parallel to the SMJ320C10, SMJ320C15, SMJ320E15 to any other digital signal processor, or to external FIFO circuitry.

operation with internal voltage reference

The internal reference eliminates the need for an external voltage reference and provides overall circuit cost reduction. Thus the internal reference eases the design task and provides complete control over the performance of the integrated circuit. The internal reference is brought out to a pin and is available to the designer. To keep the amount of noise on the reference signal to a minimum, an external capacitor can be connected between REF and ANLG GND.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4–29

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Texas Instruments TLC32040MJ, TLC32040MFK, TLC32040IN, TLC32040CN, TLC32040CFN Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual