Texas Instruments TLC2932IPWR, TLC2932IPWLE Datasheet

TLC2932

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

D

Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One

External Bias Resistor (R

BIAS

– Lock Frequency:

22 MHz to 50 MHz (V

= 5 V ±5%,

DD

TA = –20°C to 75°C, ×1 Output)
11 MHz to 25 MHz (VDD = 5 V ±5%,
TA = –20°C to 75°C, ×1/2 Output)

– Output Frequency . . . ×1 and ×1/2

Selectable

D

Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump

D

Independent VCO, PFD Power-Down Mode

D

Thin Small-Outline Package (14 terminal)

D

CMOS Technology

D

Typical Applications:
– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division

D

Application Report Available

D

CMOS Input Logic Level

†

description

PW PACKAGE

(TOP VIEW)

)

LOGIC V

LOGIC GND

†

Available in tape and reel only and ordered as the
TLC2932IPWLE.

NC – No internal connection

DD

SELECT

VCO OUT

FIN–A
FIN–B

PFD OUT

1
2
3
4
5
6
7

†

14
13
12
11
10

9
8

VCO V

DD

BIAS
VCO

IN

VCO GND
VCO INHIBIT
PFD INHIBIT
NC

The TLC2932 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (R

). The VCO has a 1/2 frequency divider at the output stage.

BIAS

The high-speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as a power-down mode. The TLC2932 is suitable for use as a high-performance PLL due
to the high speed and stable oscillation capability of the device.

functional block diagram

4

FIN–A
FIN–B

PFD INHIBIT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

5

Frequency

9

Detector

Phase

6

PFD OUT

AVAILABLE OPTIONS

T

A

–20°C to 75°C TLC2932IPWLE

VCO IN

BIAS

VCO INHIBIT

SELECT

PACKAGE

SMALL OUTLINE

(PW)

12
13

Voltage-

Controlled

10

Oscillator

2

Copyright  1997, Texas Instruments Incorporated

3

VCO OUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TLC2932

I/O

DESCRIPTION

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

Terminal Functions

TERMINAL

NAME NO.

FIN–A 4 I Input reference frequency f
FIN–B 5 I Input for VCO external counter output frequency f

LOGIC GND 7 GND for the internal logic.
LOGIC V

NC 8 No internal connection.
PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state, see Table 3.
PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
BIAS 13 I Bias supply. An external resistor (R

SELECT 2 I VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when low, the

VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO

VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
VCO GND 11 GND for VCO.
VCO OUT 3 O VCO output. When the VCO INHIBIT is high, VCO output is low.
VCO V

DD

DD

1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce

14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling

counter.

cross-coupling between supplies.

oscillation frequency range.

output frequency is ×1, see Table 1.

oscillation frequency .

between supplies.

(REF IN)

is applied to FIN–A.

(FIN–B)

) between VCO VDD and BIAS supplies bias for adjusting the

BIAS

. FIN–B is nominally provided from the external

detailed description

VCO oscillation frequency

The VCO oscillation frequency is determined by an external resistor (R
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. The bias resistor
value for the minimum temperature coefficient is nominally 3.3 kΩ with 3-V at the VCO V
nominally 2.2 kΩ with 5-V at the VCO V

terminal. For the lock frequency range refer to the recommended

DD

operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.

VCO Oscillation Frequency Range

osc

(f )

VCO Oscillation Frequency

1/2 V

VCO Control Voltage (VCO IN)

Bias Resistor (R

DD

BIAS

)

) connected between the VCO V

BIAS

DD

terminal and

DD

Figure 1. VCO Oscillation Frequency

2

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VCO output frequency 1/2 divider

TLC2932

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

The TLC2932 SELECT terminal sets the f
f

output should be used for minimum VCO output jitter.

osc

osc

or 1/2 f

VCO output frequency as shown in Table 1. The 1/2

osc

Table 1. VCO Output 1/2 Divider Function

SELECT VCO OUTPUT

Low f

High 1/2 f

osc

osc

VCO inhibit function

The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode, refer to Table 2.

Table 2. VCO Inhibit Function

VCO INHIBIT VCO OSCILLATOR VCO OUTPUT I

Low Active Active Normal

High Stopped Low level Power Down

DD(VCO)

PFD operation

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.

FIN–A

FIN–B

V

OH

PFD OUT

Hi-Z

V

OL

Figure 2. PFD Function Timing Chart

PFD output control

A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-down mode for the PFD.

Table 3. VCO Output Control Function

PFD INHIBIT DETECTION PFD OUTPUT I

Low Active Active Normal

High Stopped Hi-Z Power Down

DD(PFD)

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3

TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

schematics

VCO block schematic

R

BIAS

VCO IN

VCO INHIBIT

PFD block schematic

BIAS

Bias

Control

Charge Pump

V

DD

VCO

Output

1/2

M
U
X

SELECT

VCO OUT

FIN–A

PFD OUT

PFD INHIBIT

absolute maximum ratings

Detector

FIN–B

†

Supply voltage (each supply), VDD (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range (each input), VI (see Note 1) –0.5 V to V

DD

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current (each input), II ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (each output), I

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Continuous total power dissipation, at (or below) TA = 25°C (see Note 2) 700 mW. . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA –20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to network GND.

2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.

4

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Suppl

oltage, V

(each suppl

see Note 3)

V

Lock frequency (×1 output)

MH

Lock frequency (×1/2 output)

MH

Bias resistor, R

kΩ

TLC2932

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

recommended operating conditions

PARAMETER MIN NOM MAX UNIT

pp

y v

Input voltage, VI (inputs except VCO IN) 0 V
Output current, IO (each output) 0 ±2 mA
VCO control voltage at VCO IN 0.9 V

NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage

and separated from each other.

DD

BIAS

pp

y,

p

p

electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)

VDD = 3 V 2.85 3 3.15
VDD = 5 V 4.75 5 5.25

DD

DD

VDD = 3 V 14 21
VDD = 5 V 22 50
VDD = 3 V 7 10.5
VDD = 5 V 11 25
VDD = 3 V 2.2 3.3 4.3
VDD = 5 V 1.5 2.2 3.3

V

V

z

z

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

V

IT

I

I

Z

i(VCO IN)

I

DD(INH)

I

DD(VCO)

NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.

High-level output voltage IOH = –2 mA 2.4 V
Low-level output voltage IOL = 2 mA 0.3 V
Input threshold voltage at SELECT, VCO INHIBIT 0.9 1.5 2.1 V
Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA
Input impedance VCO IN = 1/2 V
VCO supply current (inhibit) See Note 4 0.01 1 µA
VCO supply current See Note 5 5 15 mA

5. Current into VCO VDD, when VCO IN = 1/2 VDD, R

= 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.

BIAS

DD

10 MΩ

PFD section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

I

OZ

V

IH

V

IL

V

IT

C

i

Z

i

I

DD(Z)

I

DD(PFD)

NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.

High-level output voltage IOH = –2 mA 2.7 V
Low-level output voltage IOL = 2 mA 0.2 V

High-impedance-state output current
High-level input voltage at FIN–A, FIN–B 2.7 V

Low-level input voltage at FIN–A, FIN–B 0.5 V
Input threshold voltage at PFD INHIBIT 0.9 1.5 2.1 V
Input capacitance at FIN–A, FIN–B 5 pF
Input impedance at FIN–A, FIN–B 10 MΩ
High-impedance-state PFD supply current See Note 6 0.01 1 µA
PFD supply current See Note 7 0.1 1.5 mA

7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (V
inhibited.

I(PP)

PFD INHIBIT = high,
VI = VDD or GND

= 3 V, rectangular wave), NC = GND, no load, and VCO OUT is

±1 µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC2932

trRise time

ns

tfFall time

ns

ns

See Figures 4 and 5 and Table 4

ns

C

See Figure 4

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

operating characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

osc

t

s(fosc)

α

(fosc)

k

SVS(fosc)

NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.

Operating oscillation frequency R
Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs

Duty cycle at VCO OUT R
Temperature coefficient of oscillation frequency

Supply voltage coefficient of oscillation frequency

Jitter absolute (see Note 9) R

9. The low-pass-filter (LPF) circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent
on circuit layout and external device characteristics. The jitter specification was made with a carefully designed PCB with no device
socket.

= 3.3 kΩ, VCO IN = 1/2 V

BIAS

CL = 15 pF, See Figure 3 7 14
CL = 50 pF, See Figure 3 14
CL = 15 pF, See Figure 3 6 12
CL = 50 pF, See Figure 3 10

= 3.3 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%

BIAS

R

= 3.3 kΩ, VCO IN = 1/2 VDD,

BIAS

TA = –20°C to 75°C
R

= 3.3 kΩ, VCO IN = 1.5 V,

BIAS

VDD = 2.85 V to 3.15 V

= 3.3 kΩ 100 ps

BIAS

DD

15 19 23 MHz

0.04 %/°C

0.02 %/mV

PFD section

f

max

t

PLZ

t

PHZ

t

PZL

t

PZH

t

r

t

f

Maximum operating frequency 20 MHz
PFD output disable time from low level 21 50
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level 10 30
Rise time
Fall time

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

23 50
11 30

p

= 15 pF,

L

2.3 10 ns

2.1 10 ns

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2932

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

V

IT

I

I

Z

i(VCO IN)

I

DD(INH)

I

DD(VCO)

NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, and PFD is inhibited.

PFD section

V

OH

V

OL

I

OZ

V

IH

V

IL

V

IT

C

i

Z

i

I

DD(Z)

I

DD(PFD)

NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.

High-level output voltage IOH = –2 mA 4 V
Low-level output voltage IOL = 2 mA 0.5 V
Input threshold voltage at SELECT, VCO INHIBIT 1.5 2.5 3.5 V
Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA
Input impedance VCO IN = 1/2 V
VCO supply current (inhibit) See Note 4 0.01 1 µA
VCO supply current See Note 5 15 35 mA

5. Current into VCO VDD, when VCO IN = 1/2 VDD, R

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage IOH = 2 mA 4.5 V
Low-level output voltage IOL = 2 mA 0.2 V

High-impedance-state output current
High-level input voltage at FIN–A, FIN–B 4.5 V

Low-level input voltage at FIN–A, FIN–B 1 V
Input threshold voltage at PFD INHIBIT 1.5 2.5 3.5 V
Input capacitance at FIN–A, FIN–B 5 pF
Input impedance at FIN–A, FIN–B 10 MΩ
High-impedance-state PFD supply current See Note 6 0.01 1 µA
PFD supply current See Note 7 0.15 3 mA

7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (V
VCO OUT is inhibited.

= 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.

BIAS

PFD INHIBIT = high,
VI = VDD or GND

= 5 V, rectangular wave), PFD INHIBIT = GND, no load, and

I(PP)

DD

10 MΩ

±1 µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TLC2932

trRise time

ns

tfFall time

ns

ns

See Figures 4 and 5 and Table 4

ns

C

See Figure 4

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997

operating characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

osc

t

s(fosc)

α

(fosc)

k

SVS(fosc)

NOTES: 8: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.

Operating oscillation frequency R
Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs

Duty cycle at VCO OUT R
Temperature coefficient of oscillation frequency

Supply voltage coefficient of oscillation frequency

Jitter absolute (see Note 9) R

9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.

= 2.2 kΩ, VCO IN = 1/2 V

BIAS

CL = 15 pF, See Figure 3 5.5 10
CL = 50 pF, See Figure 3 8
CL = 15 pF, See Figure 3 5 10
CL = 50 pF, See Figure 3 6

= 2.2 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%

BIAS

R

= 2.2 kΩ, VCO IN = 1/2 VDD,

BIAS

TA = –20°C to 75°C
R

= 2.2 kΩ, VCO IN = 2.5 V,

BIAS

VDD = 4.75 V to 5.25 V

= 2.2 kΩ 100 ps

BIAS

DD

30 41 52 MHz

0.06 %/°C

0.006 %/mV

PFD section

f

max

t

PLZ

t

PHZ

t

PZL

t

PZH

t

r

t

f

Maximum operating frequency 40 MHz
PFD output disable time from low level 21 40
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level 6.5 20
Rise time
Fall time

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

20 40

7.3 20

p

= 15 pF,

L

2.3 10 ns

1.7 10 ns

8

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