TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
8-Bit Resolution
D
Easy Microprocessor Interface or
Stand-Alone Operation
D
Operates Ratiometrically or With 5-V
Reference
D
4- or 8-Channel Multiplexer Options With
Address Logic
D
Input Range 0 to 5 V With Single 5-V Supply
D
Remote Operation With Serial Data Link
D
Inputs and Outputs Are Compatible With
TTL and MOS
D
Conversion Time of 32 µs at
f
clock
= 250 kHz
D
Functionally Equivalent to the ADC0834
and ADC0838 Without the Internal Zener
Regulator Network
D
T otal Unadjusted Error...±1 LSB
description
These devices are 8-bit successiveapproximation analog-to-digital converters, each
with an input-configurable multichannel
multiplexer and serial input/output. The serial
input/output is configured to interface with
standard shift registers or microprocessors.
Detailed information on interfacing with most
popular microprocessors is readily available from
the factory.
The TLC0834 (4-channel) and TLC0838 (8-channel) multiplexer is software configured for single-ended or
differential inputs as well as pseudo-differential input assignments. The differential analog voltage input allows
for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference
input can be adjusted to allow encoding of any smaller analog voltage span to the full 8 bits of resolution.
The TLC0834C and TLC0838C are characterized for operation from 0°C to 70°C. The TLC0834I and TLC0838I
are characterized for operation from –40°C to 85°C. The TLC0834Q is characterized for operation from –40°C
to 125°C.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL
OUTLINE
(D)
SMALL
OUTLINE
(DW)
PLASTIC DIP
(N)
0°C to 70°C TLC0834CD TLC0838CDW TLC0834CN TLC0838CN
–40°C to 85°C TLC0834ID TLC0838IDW TLC0834IN TLC0838IN
–40°C to 125°C — — TLC0834QN —
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
CS
CH0
CH1
CH2
CH3
DGTL GND
V
CC
DI
CLK
SARS
DO
REF
ANLG GND
TLC0834 ...D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGTL GND
V
CC
NC
CS
DI
CLK
SARS
DO
SE
REF
ANLG GND
TLC0838 ...DW OR N PACKAGE
(TOP VIEW)
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CS
SE
Only
5-Bit Shift Register
ODD\
SELECT0
EN
MUX
Analog
START
SGL\
SELECT1
Circuits
To Internal
(see Note A)
DI
CLK
CS
R
D
CLK
TLC0838
TLC0838
TLC0834
CH7
CH5
CH6
COM
CH4
CH3
CH2
CH1
CH0
Comparator
SARS
CS
R
Start
S
CLK
CLK
Delay
Time
S
R
CS
DO
CS
CS
D
CLK
R
EOC
Register
Shift
9-Bit
R
CLK
First
LSB
Bit 1
Bits 0–7
First
MSB
Shot
One
Latch
and
Logic
SAR
R
CS
Bits 0–7
REF
Decoder
and
Ladder
EN
Flip-Flop
functional block diagram
NOTE A: For the TLC0834, DI is input directly to the D input of SELECT1; SELECT0 is forced to a high.
EVEN
DIF
18
15
14
18
18
18
18
12
16
18
17
1
2
3
4
5
6
7
8
9
18
B: Terminal numbers shown are for the DW or N package.
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional description
The TLC0834 and TLC0838 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE
, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–)
polarity . When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair . These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLC0838 can be used for a pseudo-differential input. In this mode, the voltage on
the common input is considered to be the negative differential input for all channel inputs. This voltage can be
any reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS
low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder
output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TLC0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE
is held
high on the TLC0838, the value of the LSB remains on the data line. When SE
is forced low, the data is then
clocked out as LSB-first data. (To output LSB first, SE
must first go low, then the data stored in the 9-bit shift
register outputs LSB first.) When CS
goes high, all internal registers are cleared. At this time, the output circuits
go to the high-impedance state. If another conversion is desired, CS
must make a high-to-low transition followed
by address information.
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
sequence of operation
SELECT
Bit 1
157
1
Bit
t
su
Hi-Z
SARS
Don’t Care
176201267
MSBLSB
LSB-First Data
MSB-First Data
EVEN
DIF
ODD
+Sign
SGLBit
Start
MSB
Mux Settling Time
DI
DO
CS
CLK
21201918141312123456 1011
t
conv
Hi-Z
Hi-Z
TLC0834 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS CHANNEL NUMBER
SGL/DIF
ODD/EVEN
L
L
H
H
L
H
L
H
CH0 CH1
SELECT BIT 1
L
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
CH2 CH3
+––
+
+––
+
+
+
+
+
TLC0834
H = high level, L = low level, – or + = terminal polarity for the selected
input channel
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
sequence of operation
1SGL ODD
Bit
LSB
MSB
LSB
765432101267
MSB
Time
Mux Settling
LSB Held LSB-First DataMSB-First Data
SE
Used to Control LSB-First Data
Hi-Z
Hi-Z
t
conv
Don’t Care
765432101267
MSB
LSB-First Data
MSB-First Data
MSB
Hi-Z
DO
SE
SARS
Hi-Z
SELSEL
+
Bit
0
0
1EVENDIF
DI
Bit
Start
CS
Addressing
Mux
t
su
t
su
CLK
2726252423222120191817161514131211
8765432
1
TLC0838
Sign
Bit
SE
DO
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC0838 MUX-ADDRESS CONTROL LOGIC T ABLE
MUX ADDRESS
SELECTED CHANNEL NUMBER
SELECT 0123
COM
SGL/DIF
ODD/EVEN
1 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
L L L L + –
L L L H +–
L L HL +–
L L HH +–
L H LL–+
L H LH –+
L H HL –+
L H HH –+
H L LL+ –
H L LH +–
HLHL+–
HLHH +–
HHLL+ –
HHLH +–
HHHL +–
HHHH +–
H = high level, L = low level, – or + = polarity of external input
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)
†
Supply voltage, V
CC
(see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range: Logic –0.3 V to V
CC
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog –0.3 V to V
CC
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, I
I
±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total input current ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.5 5 5.5 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
Clock frequency, f
clock
10 600 kHz
Clock duty cycle (see Note 2) 40% 60%
Pulse duration, CS high, t
wH(CS)
220 ns
Setup time, CS low, SE low, or data valid before CLK↑, tsu (see Figures 1 and 2) 350 ns
Hold time, data valid after CLK↑, th (see Figure 1) 90 ns
p
p
C suffix 0 70
°
Operating free-air temperature, T
A
I suffix –40 85
°C
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.
electrical characteristics over recommended range of operating free-air temperature, VCC = 5 V,
f
clock
= 250 kHz (unless otherwise noted)
digital section
C SUFFIX I SUFFIX
PARAMETER
TEST CONDITIONS
†
MIN
TYP
‡
MAX MIN
TYP
‡
MAX
UNIT
p
VCC = 4.75 V , IOH = –360 µA 2.8 2.4
VOHHigh-level output voltage
VCC = 4.75 V , IOH = –10 µA 4.6 4.5
V
V
OL
Low-level output voltage VCC = 5.25 V , IOL = 1.6 mA 0.34 0.4 V
I
IH
High-level input current VIH = 5 V VIH = 5 V 0.005 1 0.005 1 µA
I
IL
Low-level input current VIL = 0 VIL = 0 –0.005 –1 –0.005 –1 µA
I
OH
High-level output (source) current VOH = 0, TA = 25°C –6.5 –24 –6.5 –24 mA
I
OL
Low-level output (sink) current VOL = VCC, TA = 25°C 8 26 8 26 mA
High-impedance-state output
VO = 5 V, TA = 25°C 0.01 3 0.01 3
I
OZ
g
current (DO or SARS)
VO = 0,
TA = 25°C –0.01 –3 –0.01 –3
µ
A
C
i
Input capacitance 5 pF
C
o
Output capacitance 5 pF
†
All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified).
‡
All typical values are at VCC = 5 V, TA = 25°C.
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
analog and converter section
PARAMETER TEST CONDITIONS
†
MIN TYP‡MAX UNIT
–0.05
V
IC
Common-mode input voltage See Note 3
to
V
IC
g
VCC+0.05
On channel VI = 5 V 1
p
Off channel VI = 0 –1
I
I(stdby)
Standby input current (see Note 4)
On channel VI = 0 –1
µ
A
Off channel VI = 5 V 1
r
i(REF)
Input resistance to REF 1.3 2.4 5.9 kΩ
total device
PARAMETER MIN TYP‡MAX UNIT
I
CC
Supply current 0.6 1.25 mA
†
All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡
All typical values are at VCC = 5 V, TA = 25°C.
NOTES: 3. When channel IN– is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are
two on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC.Care must be taken during
testing at low VCC levels (4.5 V) because high-level analog input voltage (5 V) can, especially at high temperatures, cause the input
diode to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 5-V input range requires a minimum VCC of
4.950 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or of f channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state condition.
operating characteristics, VCC = 5 V, f
clock
= 250 kHz, tr = t
f
= 20 ns, TA = 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS
§
MIN TYP MAX UNIT
Supply-voltage variation error VCC = 4.75 V to 5.25 V ±1/16 ±1/4 LSB
Total unadjusted error (see Note 5) V
ref
= 5 V, TA = MIN to MAX ±1 LSB
Common-mode error Differential mode ±1/16 ±1/4 LSB
Propagation delay time, output
MSB-first data
p
1500
t
pd
gy,
data after CLK↓ (see Note 6) (see Figure 2)
LSB-first data
C
L
=
100pF
600
ns
CL = 10 pF, RL = 10 kΩ 250
t
dis
Output disable ti
me, DO or
SARS aft
er
CS↑ (
see Figure
3)
CL = 100 pF, RL = 2 kΩ 500
ns
t
conv
Conversion time (multiplexer-addressing time not included) 8
clock
periods
§
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time.
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50%
t
su
t
h
t
h
t
su
50%
V
CC
GND
GND
GND
0.4 V0.4 V
2 V
2 V
DI
0.4 V
CS
CLK
V
CC
V
CC
Figure 1. Data-Input Timing
t
su
t
pd
t
pd
SE
CLK
DO
50%
50%
50%
50%
50%
GND
GND
GND
V
CC
V
CC
V
CC
Figure 2. Data-Output Timing
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
S2 Open
S1 Closed
10%
10%
90%
t
r
VOLTAGE WAVEFORMS
S2 Closed
S1 Open
DO and SARS
t
r
S1
S2
LOAD CIRCUIT
(see Note A)
C
L
From Output
Under Test
Test
Point
CS
CS
t
dis
90%
10%
90%
50%
50%
V
CC
GND
GND
GND
GND
V
CC
–V
CC
V
CC
V
CC
R
L
DO and SARS
t
dis
NOTE A: CL includes probe and jig capacitance.
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
V
ref
– Reference V oltage – V
1010.10.01
V
I(+)
= V
I(–)
= 0 V
0
2
4
6
8
10
12
14
16
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
E
O(unadj)
– Unadjusted Offset Error – LSB
Figure 4
Figure 5
V
ref –
Reference Voltage – V
VCC = 5 V
f
clock
= 250 kHz
TA = 25°C
54321
0
0.25
0.5
0.75
1
1.25
0
1.5
LINEARITY ERROR
vs
REFERENCE VOLTAGE
– Linearity Error – LSB
E
L
Figure 6
TA – Free-Air Tempertature – °C
V
ref
= 5 V
f
clock
= 250 kHz
1007550250– 25
0.5
0.45
0.4
0.35
0.3
– 50
0.25
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
– Linearity Error – LSB
E
L
Figure 7
f
clock
– Clock Frequency – kHz
25°C
85°C
V
ref
= 5 V
VCC = 5 V
600500400300200100
3
2.5
2
1.5
1
0.5
0
0
LINEARITY ERROR
vs
CLOCK FREQUENCY
–40°C
– Linearity Error – LSB
E
L
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 8
TA – Free-Air Temperature — °C
f
clock
= 250 kHz
CS
= High
VCC = 5 V
VCC = 4.5 V
1007550250– 25
1.5
1
– 50
0.5
– Supply Current – mA
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
CC
I
VCC = 5.5 V
Figure 9
f
clock
– Clock Frequency – kHz
VCC = 5 V
TA = 25°C
1.5
1
0.5
5004003002001000
0
SUPPLY CURRENT
vs
CLOCK FREQUENCY
– Supply Current – mA
CC
I
TA – Free-Air Temperature – °C
VCC = 5 V
IOL (VOL = 5 V)
–IOH (VOH = 0 V)
IOL (VOL = 0.4 V)
20
25
15
10
5
1007550250–25–50
0
– Output Current – mA
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
I
O
–IOH (VOH = 2.4 V)
Figure 10
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Differential Nonlinearity – LSB
–1
Output Code
1
0.5
0
–0.5
0 32 64 96 128 160 192 224 256
V
ref
= 5 V
TA = 25°C
FCLK = 250 kHz
VDD = 5 V
Figure 11. Differential Nonlinearity With Output Code
Integral Nonlinearity – LSB
–1
Output Code
1
0.5
0
–0.5
0 32 64 96 128 160 192 224 256
V
ref
= 5 V
TA = 25°C
FCLK = 250 kHz
VDD = 5 V
Figure 12. Integral Nonlinearity With Output Code
Total Unadjusted Error – LSB
–1
Output Code
1
0.5
0
–0.5
0 32 64 96 128 160 192 224 256
V
ref
= 5 V
TA = 25°C
FCLK = 250 kHz
VDD = 5 V
Figure 13. Total Unadjusted Error With Output Code
TLC0834C, TLC0834I, TLC0838C, TLC0838I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS094C – MARCH 1995 – REVISED APRIL 1997
2–14
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