Texas Instruments TL081ACD, TL081ACP, TL081BCD, TL081BCP, TL081CD Schematic

+

−

+

−

OFFSET N1

IN +

IN −

OUT

IN +

IN −

OUT

TL082 (EACH AMPLIFIER) TL084 (EACH AMPLIFIER)

TL081

OFFSET N2

Product Folder

Sample & Buy

Technical Documents

Tools & Software

Support & Community

TL081,TL081A,TL081B,TL082,TL082A

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

TL08xx JFET-Input Operational Amplifiers

1 Features 3 Description

1

• Low Power Consumption: 1.4 mA/ch Typical

• Wide Common-Mode and Differential Voltage Ranges

• Low Input Bias Current: 30 pA Typical

• Low Input Offset Current: 5 pA Typical

• Output Short-Circuit Protection

• Low Total Harmonic Distortion: 0.003% Typical

• High Input Impedance: JFET Input Stage

• Latch-Up-Free Operation

• High Slew Rate: 13 V/μs Typical

• Common-Mode Input Voltage Range Includes V

CC+

2 Applications

• Tablets

• White goods

• Personal electronics

• Computers

The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TL084xD SOIC (14) 8.65 mm × 3.91 mm TL08xxFK LCCC (20) 8.89 mm × 8.89 mm TL084xJ CDIP (14) 19.56 mm × 6.92 mm TL084xN PDIP (14) 19.3 mm × 6.35 mm TL084xNS SO (14) 10.3 mm × 5.3 mm TL084xPW TSSOP (14) 5.0 mm × 4.4 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

TL082B,TL084,TL084A,TL084B

(1)

Schematic Symbol

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

www.ti.com

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (January 2014) to Revision I Page

• Added Pin Configuration and Functions section, Storage Conditions table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable

Information section ................................................................................................................................................................ 1

• Added Applications................................................................................................................................................................. 1

• Moved Typical Characteristics into Specifications section. ................................................................................................... 9

Changes from Revision G (September 2004) to Revision H Page

• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

• Deleted Ordering Information table. ....................................................................................................................................... 1

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4IN+ NC V

CC

− NC 3IN+

1IN+

NC

V

CC +

NC

2IN+

1IN −

1OUT

NC

3OUT

3IN −

4OUT

4IN −

2IN −

2OUT

NC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OUT

1IN− 1IN+

V

CC +

2IN+ 2IN−

2OUT

4OUT 4IN− 4IN+ V

CC −

3IN+ 3IN− 3OUT

1

2

3

4

8

7

6

5

1OUT

1IN− 1IN+

V

CC −

V

CC +

2OUT 2IN− 2IN+

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC 2OUT NC 2IN− NC

NC

1IN−

NC

1IN+

NC

1OUT

NC

2IN +

NC

V

CC+

V

CC −

1

2

3

4

8

7

6

5

OFFSET N1

IN −

IN +

V

CC −

NC V

CC +

OUT OFFSET N2

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5 Pin Configuration and Functions

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

TL082 FK Package

20-Pin LCCC

Top View

TL084 FK Package

20-Pin LCCC

Top View

TL081 and TL081x D, P, and PS Package

8-Pin SOIC, PDIP, and SO

Top View

TL082 and TL082x D, JG, P, PS and PW Package

8-Pin SOIC, CDIP, PDIP, SO, and TSSOP

Top View

TL084 and TL084x D, J, N, NS and PW Package

14-Pin SOIC, CDIP, PDIP, SO, and TSSOP

Top View

Pin Functions

TL081 TL082 TL084

NAME

1IN– — 2 5 2 3 I Negative input 1IN+ — 3 7 3 4 I Positive input 1OUT — 1 2 1 2 O Output 2IN– — 6 15 6 9 I Negative input 2IN+ — 5 12 5 8 I Positive input 2OUT — 7 17 7 10 O Output 3IN– — — — 9 13 I Negative input 3IN+ — — — 10 14 I Positive input 3OUT — — — 8 12 O Output 4IN– — — — 13 19 I Negative input 4IN+ — — — 12 18 I Positive input 4OUT — — — 14 20 O Output

SOIC, PDIP, CDIP,

SO PDIP, SO,

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

SOIC,

CDIP, PDIP, LCCC LCCC

SO, TSSOP

SOIC,

TSSOP

I/O DESCRIPTION

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Pin Functions (continued)

TL081 TL082 TL084

NAME

IN– 2 — — — — I Negative input IN+ 3 — — — — I Positive input

NC 8 — 9 — — Do not connect

OFFSET N1

OFFSET N2

OUT 6 — — — — O Output V

CC–

V

CC+

SOIC, PDIP, CDIP,

SO PDIP, SO,

1 — — — — — Input offset adjustment

5 — — — — — Input offset adjustment

4 4 10 11 16 — Power supply 7 8 20 4 6 — Power supply

SOIC,

CDIP, PDIP, LCCC LCCC

SO, TSSOP

1 3 4 6 8

11 13 14 16 18 17

SOIC,

TSSOP

1

5

7

11

15

I/O DESCRIPTION

www.ti.com

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

www.ti.com

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V

CC+

V

CC–

V

ID

V

I

T

A

T

C

T

stg

Supply voltage

Differential input voltage Input voltage Duration of output short circuit Continuous total power dissipation See Dissipation Rating Table

Operating free-air temperature °C

Operating virtual junction temperature 150 °C Case temperature for 60 seconds FK package TL08_M 260 °C Lead temperature 1,6 mm (1/16

inch) from case for 10 seconds Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential voltages, are with respect to the midpoint between V (3) Differential voltages are at IN+, with respect to IN−. (4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. (5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the

dissipation rating is not exceeded.

(2)

(3)

(2)(4)

(5)

TL08_C TL08_AC 0 70 TL08_BC

TL08_I –40 85 TL084Q –40 125 TL08_M –55 125

J or JG package TL08_M 300 °C

(1)

MIN MAX UNIT

CC+

and V

CC−

18 –18 ±30 V ±15 V

Unlimited

.

V

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

V

Electrostatic discharge V

(ESD)

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(1)

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V V V

T

A

Supply voltage 5 15 V

CC+

Supply voltage –5 –15 V

CC–

Common-mode voltage V

CM

CC–

+ 4 V

TL08xM –55 125

Ambient temperature °C

TL08xQ –40 125 TL08xI –40 85 TL08xC 0 70

VALUE UNIT

1000 1500

– 4 V

CC+

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

www.ti.com

6.4 Thermal Information

TL08xx

THERMAL METRIC

(1)

D (SOIC) N (PDIP) NS (SO) P (PDIP) PS (SO) PW (TSSOP)

8 PINS 14 14 PINS 14 PINS {PIN {PIN 8 PINS 14

UNIT

PINS COUNT} COUNT} PINS

PINS PINS

R

Junction-to-ambient

θJA

thermal resistance

(2)(3)

97 86 76 80 85 95 149 113 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Maximum power dissipation is a function of T

temperature is PD= (T

(3) The package thermal impedance is calculated in accordance with JESD 51-7.

J(max)

– TA) / R

. Operating at the absolute maximum TJof 150°C can affect reliability.

θJA

J(max)

, R

, and TA. The maximum allowable power dissipation at any allowable ambient

θJA

6.5 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI

V

= ±15 V (unless otherwise noted)

CC±

PARAMETER T

V

Input offset VO= 0,

IO

voltage RS= 50 Ω

TEST

CONDITIONS

25°C 3 15 3 6 2 3 3 6

range

Temperature

α

input 18 18 18 18 μV/°C

VIO

offset

coefficient of

VO= 0, Full RS= 50 Ω range

voltage

I

Input offset

IO

current

Input bias

IB

current

VO= 0

(2)

VO= 0

(2)

25°C 5 200 5 100 5 100 5 100 pA

range

25°C 30 400 30 200 30 200 30 200 pA

range

Common-

ICR

mode input voltage

25°C ±11 to ±11 to ±11 to ±11 to V

V

range Maximum RL= 10 kΩ 25°C ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 ±12 ±13.5

V

output V

OM

voltage swing

peak

RL≥ 10 kΩ ±12 ±12 ±12 ±12 RL≥ 2 kΩ ±10 ±12 ±10 ±12 ±10 ±12 ±10 ±12

range

Large-signal 25°C 25 200 50 200 50 200 50 200

A

B

r

CMRR VO= 0, 25°C 70 86 75 86 75 86 75 86 dB

k

differential VO= ±10 V,

VD

voltage RL≥ 2 kΩ amplification

Unity-gain

1

bandwidth Input

i

resistance Common-

mode rejection ratio

Supplyvoltage rejection 25°C 70 86 80 86 80 86 80 86 dB

SVR

ratio (ΔV

CC±

/ΔVIO)

VIC= V

ICR

RS= 50 Ω

VCC= ±15 V to ±9 V, VO= 0, RS= 50 Ω

range

25°C 3 3 3 3 MHz

25°C Ω

min,

TL081C, TL082C, TL081AC, TL082AC, TL081BC, TL082BC, TL081I, TL082I,

(1)

A

TL084C TL084AC TL084BC TL084I

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

Full

20 7.5 5 9

2 2 2 10 nA

10 7 7 20 nA

–12 –12 –12 –12

15 15 15 15

Full

15 15 25 25

12

10

12

10

12

10

UNIT

V/mV

12

10

mV

(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range for

TAis 0°C to 70°C for TL08_C, TL08_AC, TL08_BC and –40°C to 85°C for TL08_I.

(2) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Figure 13. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

www.ti.com

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Electrical Characteristics for TL08xC, TL08xxC, and TL08xI (continued)

V

= ±15 V (unless otherwise noted)

CC±

PARAMETER T

TEST

CONDITIONS

TL081C, TL082C, TL081AC, TL082AC, TL081BC, TL082BC, TL081I, TL082I,

(1)

A

TL084C TL084AC TL084BC TL084I

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNIT

Supply

I

current VO= 0,

CC

(each No load

25°C 1.4 2.8 1.4 2.8 1.4 2.8 1.4 2.8 mA

amplifier)

O2

Crosstalk attenuation

AVD= 100 25°C 120 120 120 120 dB

VO1/V

6.6 Electrical Characteristics for TL08xM and TL084x

V

= ±15 V (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS

V

IO

Input offset voltage VO= 0, RS= 50 Ω mV

(1)

T

A

25°C 3 6 3 9

Full range 9 15

Temperature

α

VIO

I

IO

I

IB

V

ICR

coefficient of input VO= 0, RS= 50 Ω Full range 18 18 μV/°C offset voltage

Input offset current

Input bias current

Common-mode input voltage range

(2)

VO= 0

(2)

VO= 0

25°C 5 100 5 100 pA

125°C 20 20 nA

25°C 30 200 30 200 pA

125°C 50 50 nA

25°C ±11 to ±11 to V

RL= 10 kΩ 25°C ±12 ±13.5 ±12 ±13.5

V

OM

A

VD

B

1

r

i

CMRR 25°C 80 86 80 86 dB

k

SVR

I

CC

Maximum peak output voltage swing

Large-signal differential voltage amplification

RL≥ 10 kΩ ±12 ±12 V RL≥ 2 kΩ ±10 ±12 ±10 ±12

VO= ±10 V, RL≥ 2 kΩ V/mV

Full range

25°C 25 200 25 200

Full range 15 15 Unity-gain bandwidth 25°C 3 3 MHz Input resistance 25°C Ω Common-mode VIC= V

rejection ratio VO= 0, RS= 50 Ω Supply-voltage

rejection ratio 25°C 80 86 80 86 dB (ΔV

/ΔVIO)

CC±

Supply current (each amplifier)

VCC= ±15 V to ±9 V, VO= 0, RS= 50 Ω

VO= 0, No load 25°C 1.4 2.8 1.4 2.8 mA

ICR

min,

VO1/VO2Crosstalk attenuation AVD= 100 25°C 120 120 dB

(1) All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. (2) Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown

in Figure 13. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as possible.

TL081M, TL082M TL084Q, TL084M

MIN TYP MAX MIN TYP MAX

–12 –12

15 15

12

10

12

10

UNIT

6.7 Operating Characteristics

V

= ±15 V, TA= 25°C (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VI= 10 V, RL= 2 kΩ, CL= 100 pF, See Figure 19

SR Slew rate at unity gain V/μs

VI= 10 V, RL= 2 kΩ, CL= 100 pF, TA= − 55°C to 125°C, 5 See Figure 19

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

(1)

8

(1)

13

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Operating Characteristics (continued)

V

= ±15 V, TA= 25°C (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

r

V

n

I

n

THD Total harmonic distortion 0.003%

Rise-time 0.05 μs overshoot factor 20%

Equivalent input noise voltage

Equivalent input noise current

VI= 20 V, RL= 2 kΩ, CL= 100 pF, See Figure 19

RS= 20 Ω

RS= 20 Ω, f = 1 kHz 0.01 pA/√Hz VIrms = 6 V, AVD= 1, RS≤ 1 kΩ, RL≥ 2 kΩ,

f = 1 kHz,

f = 1 kHz 18 nV/√Hz f = 10 Hz to 10 kHz 4 μV

6.8 Dissipation Rating Table

PACKAGE

D (14 pin) 680 mW 7.6 mW/°C 60°C 604 m/W 490 mW 186 mW

FK 680 mW 11.0 mW/°C 88°C 680 m/W 680 mW 273 mW

J 680 mW 11.0 mW/°C 88°C 680 m/W 680 mW 273 mW

JG 680 mW 8.4 mW/°C 69°C 672 m/W 546 mW 210 mW

TA≤ 25°C DERATING DERATE TA= 70°C TA= 85°C TA= 125°C

POWER RATING FACTOR ABOVE T

POWER RATING POWER RATING POWER RATING

A

www.ti.com

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

10 M1 M100 k10 k1 k100

f − Frequency − Hz

VOM − Maximum Peak Output V

oltage − V

0

±2.5

±5

±7.5

±10

±12.5

±15

See Figure 2

TA= 25°C

RL= 2 kΩ

V

CC

±

= ±10 V

V

CC

±

= ±5 V

V

OM

V

CC

±

= ±15 V

RL= 10 kΩ TA= 25°C See Figure 2

±15

±12.5

±10

±7.5

±5

±2.5

0

VOM − Maximum Peak Output V

oltage − V

f − Frequency − Hz

100 1 k 10 k 100 k 1 M 10 M

V

OM

V

CC

±

= ±5 V

V

CC

±

= ±10 V

V

CC

±

= ±15 V

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

www.ti.com

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

6.9 Typical Characteristics

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. The Figure numbers referenced in the following graphs are located in Parameter Measurement Information.

Table 1. Table of Graphs

Figure

versus Frequency Figure 1, Figure 2, Figure 3

V

OM

Maximum peak output voltage

Large-signal differential voltage versus Free-air temperature Figure 7

A

VD

amplification versus Load resistance Figure 8 Differential voltage amplification Figure 9

P

D

I

CC

I

IB

Total power dissipation versus Free-air temperature Figure 10 Supply current Input bias current versus Free-air temperature Figure 13

Large-signal pulse response versus Time Figure 14

V

O

Output voltage versus Elapsed time Figure 15 CMRR Common-mode rejection ratio versus Free-air temperature Figure 16 V

n

Equivalent input noise voltage versus Frequency Figure 17 THD Total harmonic distortion versus Frequency Figure 18

versus Free-air temperature Figure 4 versus Load resistance Figure 5 versus Supply voltage Figure 6

versus Frequency with feed-forward compensation

versus Free-air temperature Figure 11 versus Supply voltage Figure 12

Figure 1. Maximum Peak Output Voltage

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

vs

Frequency

Figure 2. Maximum Peak Output Voltage

vs

Frequency

−75

1

Voltage

Amplification − V/mV

T

− Free-Air Temperature − °C

125

1000

−50 −25 0 25 50 75 100

2

4

10

20

40

100

200

400

V

CC

±

= ±15 V

VO= ±10 V RL= 2 kΩ

A

− Large-Signal Differential

A

VD

0°

45°

180°

135°

90°

1

f − Frequency − Hz

10 M

10

6

10 100 1 k 10 k 100 k 1 M

10

1

10

2

10

3

10

4

10

5

Differential Voltage Amplification

V

CC

±

= ±5 V to ±15 V

RL= 2 kΩ TA= 25°C

Phase Shift

Voltage

Amplification

A

– Large-Signal Differential

A

VD

Phase Shift

0.1

0

R

− Load Resistance − kΩ

10

±15

±2.5

±5

±7.5

±10

±12.5

V

CC

±

= ±15 V

TA= 25°C See Figure 2

0.2 0.4 0.7 1 2 4 7

VOM − Maximum Peak Output V

oltage − V

V

OM

8

0

VOM − Maximum Peak Output V

oltage − V

|V

CC

±

| − Supply Voltage − V

16

±15

2 4 6 8 10 12 14

±2.5

±5

±7.5

±10

±12.5

RL= 10 kΩ TA= 25°C

V

OM

8

0

±2.5

±5

±7.5

±10

±12.5

±15

10 k 40 k 100 k 400 k 1 M 4 M 10 M

f − Frequency − Hz

VOM − Maximum Peak Output V

oltage − V

V

OM

V

CC

±

= ±15 V

RL= 2 kΩ See Figure 2

TA= −55°C

TA= 25°C

TA= 125°C

−75

0

VOM − Maximum Peak Output V

oltage − V

T

− Free-Air Temperature − °C

125

±15

−50 −25 0 25 50 75 100

±2.5

±5

±7.5

±10

±12.5

RL= 10 kΩ

V

CC

±

= ±15 V

See Figure 2

V

OM

RL= 2 kΩ

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

www.ti.com

Figure 3. Maximum Peak Output Voltage

vs

Frequency

Figure 5. Maximum Peak Output Voltage

vs

Load Resistance

Figure 4. Maximum Peak Output Voltage

vs

Free-Air Temperature

Figure 6. Maximum Peak Output Voltage

vs

Supply Voltage

Figure 7. Large-Signal Differential Voltage Amplification

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

vs

Free-Air Temperature

Figure 8. Large-Signal Differential Voltage Amplification and

Phase Shift

vs

Frequency

− 50

0.01

− Input Bias Current − nA

T

− Free-Air Temperature − C°

125

100

− 25 0 25 50 75 100

0.1

1

10

V

CC±

= 15 V±

I

IB

−6

t − Time − µs

3.5

6

0 0.5 1 1.5 2 2.5 3

−4

−2

0

2

4

Output

Input

V

CC

±

= ±15 V

RL= 2 kΩ

TA= 25°C

CL= 100 pF

V

O

V

I

− Input and Output V

oltages − V

and

−75

0

T

− Free-Air Temperature − °C

125

2

−50 −25 0 25 50 75 100

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

V

CC

±

= ±15 V

No Signal No Load

ICC − Supply Current Per

Amplifier − mA

CC±

I

0

|V

CC

±

| − Supply Voltage − V

16

2

2 4 6 8 10 12 14

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

TA= 25°C No Signal No Load

ICC − Supply Current Per

Amplifier − mA

CC±

I

See Figure 3

TA= 25 C°

C2 = 3 pF

V

CC±

= 15 V±

10

5

10

4

10

3

10

2

10

1 M100 k10 k1 k

10

6

10 M

f − Frequency With Feed-Forward Compensation − Hz

1

100

− Differential Voltage Amplification − V/mV

A

VD

−75

0

− Total Power Dissipation − mW

T

− Free-Air Temperature −C°

125

250

−50 −25 0 25 50 75 100

25

50

75

100

125

150

175

200

225

V

CC±

= 15 V±

No Signal No Load

TL084, TL085

TL082, TL083

TL081

P

D

www.ti.com

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Figure 9. Differential Voltage Amplification

vs

Frequency with Feed-Forward Compensation

Figure 10. Total Power Dissipation

vs

Free-Air Temperature

Figure 11. Supply Current per Amplifier Figure 12. Supply Current per Amplifier

vs vs

Free-Air Temperature Supply Voltage

Figure 13. Input Bias Current

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

vs

Free-Air Temperature

Figure 14. Voltage-Follower Large-Signal Pulse Response

10

0

− Equivalent Input Noise V

oltage − nV/Hz

f − Frequency − Hz

100 k

50

10

20

30

40

V

CC

±

= ±15 V

AVD= 10 RS= 20 Ω TA= 25°C

40 100 400 1 k 4 k 10 k 40 k

nV/

Hz

V

n

0.001

THD − T

otal Harmonic Distortion − %

1

40 k10 k4 k1 k400 100 k

f − Frequency − Hz

100

0.004

0.01

0.04

0.1

0.4

V

CC

±

= ±15 V

AVD= 1 V

I(RMS)

= 6 V

TA= 25°C

RL= 10 kΩ

V

CC±

= 15 V±

88

87

86

85

84

1007550250− 25− 50

89

125

T

− Free-Air Temperature −C°

CMRR − Common-Mode Rejection Ratio − dB

83

− 75

− 4

− Output Voltage − mV

t − Elapsed Time – sµ

1.2

28

0 0.2 0.4 0.6 0.8 1.0

0

4

8

12

16

20

24

V

O

V

CC±

= 15 V±

RL= 2 kΩ CL= 100 pF TA= 25 C° See Figure 1

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

www.ti.com

Figure 15. Output Voltage

vs

Elapsed Time

Figure 16. Common-Mode Rejection Ratio

vs

Free-Air Temperature

Figure 17. Equivalent Input Noise Voltage Figure 18. Total Harmonic Distortion

vs vs

Frequency Frequency

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

100 kΩ

C2

C1N1500 pF

+

−

OUT

IN −

TL081

N2

N1

100 kΩ

1.5 kΩ

V

CC −

+

−

OUT

IN −

IN +

V

I

CL= 100 pF

RL= 2 kΩ

+

−

OUT

V

I

10 kΩ

1 kΩ

R

L

CL= 100 pF

+

−

OUT

www.ti.com

7 Parameter Measurement Information

Figure 19. Test Figure 1 Figure 20. Test Figure 2

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Figure 21. Test Figure 3 Figure 22. Test Figure 4

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

C1

V

CC+

IN+

V

CC−

OFFSET N1

1080Ω

IN−

TL081 Only

64Ω

128Ω

64Ω

OUT

OFFSET N2

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

www.ti.com

8 Detailed Description

8.1 Overview

The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates wellmatched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient. Offset adjustment and external compensation options are available within the TL08xx family.

The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C. The Q-suffix devices are characterized for operation from –40°C to +125°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to +125°C.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Total Harmonic Distortion

Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices have a very low THD of 0.003% meaning that the TL08x devices will add little harmonic distortion when used in audio signal applications.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. These devices have a 13-V/μs slew rate.

8.4 Device Functional Modes

These devices are powered on when the supply is connected. This device can be operated as a single-supply operational amplifier or dual-supply amplifier depending on the application.

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

Vsup+

+

VOUT

RF

VIN

RI

Vsup-

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

www.ti.com

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

9 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TL08x series of operational amplifiers can be used in countless applications. The few applications in this section show principles used in all applications of these parts.

9.2 Typical Applications

9.2.1 Inverting Amplifier Application

A typical application for an operational amplifier in an inverting amplifier. This amplifier takes a positive voltage on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes negative voltages positive.

Figure 23. Schematic for Inverting Amplifier Application

9.2.1.1 Design Requirements

The supply voltage must be chosen such that it is larger than the input voltage range and output range. For instance, this application will scale a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to accommodate this application.

9.2.1.2 Detailed Design Procedure

Determine the gain required by the inverting amplifier:

(1)

(2)

Once the desired gain is determined, choose a value for RI or RF. Choosing a value in the kΩ range is desirable because the amplifier circuit will use currents in the milliamp range. This ensures the part will not draw too much current. This example will choose 10 kΩ for RI which means 36 kΩ will be used for RF. This was determined by Equation 3.

(3)

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

Input

−

+

−

TL084 Output C

Output BTL084

−

+

V

CC +

Output ATL084

−

+

V

CC +

TL084

V

CC +

100 kΩ

100 µF

1 µF

1 MΩ

100 kΩ

100 kΩ 100 kΩ

V

CC +

V

CC +

+

−

+

−

88.4 kΩ

18 pF

V

CC+

V

CC−

18 pF

88.4 kΩ

1N4148

V

CC−

V

CC+

1 kΩ

− 15 V

6 cos ωt

15 V

18 kΩ

(see Note A)

1 kΩ

6 sin ωt

1/2 TL082

18 kΩ

(see Note A)

+

−

−15 V

15 V

Output

1 kΩ

9.1 kΩ

3.3 kΩ

CF= 3.3 µF

RF= 100 kΩ

3.3 kΩ

TL081

f =

2π R

C

1

+

−

R1

C1 C2

R3

C3

V

CC −

V

CC +

TL081

OutputInput

R2

R1 = R2 = 2(R3) = 1.5 MΩ

fo=

2π R1 C1

1

= 1 kHz

C1 = C2 = = 110 pF

C3

2

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

0 0.5 1 1.5 2

Volts

Time (ms)

VIN

VOUT

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Typical Applications (continued)

9.2.1.3 Application Curve

Figure 24. Input and output voltages of the inverting amplifier

9.3 System Examples

www.ti.com

9.3.1 General Applications

Figure 25. 0.5-Hz Square-Wave Oscillator Figure 26. High-Q Notch Filter

A. These resistor values may be adjusted for a symmetrical output.

Figure 27. Audio-Distribution Amplifier Figure 28. 100-kHz Quadrature Oscillator

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

Output BOutput A

+

−

1.5 kΩ V

CC −

43 kΩ

220 pF

43 kΩ

V

CC +

30 kΩ

V

CC +

43 kΩ

V

CC −

+

−

16 kΩ

43 kΩ

Input

220 pF 220 pF

16 kΩ

+

−

V

CC −

V

CC +

30 kΩ

V

CC +

43 kΩ

220 pF

43 kΩ

V

CC −

+

−

1.5 kΩ

1/4 TL084

2 kHz/div

Second-Order Bandpass Filter

fo= 100 kHz, Q = 30, GAIN = 4

2 kHz/div

Cascaded Bandpass Filter

fo= 100 kHz, Q = 69, GAIN = 16

Output A

Outpu

t

B

1/4 TL084

www.ti.com

System Examples (continued)

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Figure 29. Positive-Feedback Bandpass Filter

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

www.ti.com

10 Power Supply Recommendations

CAUTION

Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply can permanently damage the device (see the Absolute Maximum

Ratings ).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.

– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, (SLOA089).

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Examples.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

+

RIN

RG

RF

VOUT

VIN

NC

VCC+

IN1í

IN1+

VCCí

NC

OUT

NC

RG

RIN

RF

GND

VIN

VS-GND

VS+

GND

Run the input traces as far away from the supply lines

as possible

Only needed for

dual-supply

operation

Place components close to device and to each other to

reduce parasitic errors

Use low-ESR, ceramic

bypass capacitor

(or GND for single supply) Ground (GND) plane on another layerVOUT

www.ti.com

11.2 Layout Examples

Figure 30. Operational Amplifier Board Layout for Noninverting Configuration

TL081,TL081A,TL081B,TL082,TL082A

TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

Figure 31. Operational Amplifier Schematic for Noninverting Configuration

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

TL081,TL081A,TL081B,TL082,TL082A TL082B,TL084,TL084A,TL084B

SLOS081I –FEBRUARY 1977–REVISED MAY 2015

www.ti.com

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For more information, see the following:

• Circuit Board Layout Techniques, SLOA089.

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY

TL081 Click here Click here Click here Click here Click here TL081A Click here Click here Click here Click here Click here TL081B Click here Click here Click here Click here Click here

TL082 Click here Click here Click here Click here Click here TL082A Click here Click here Click here Click here Click here TL082B Click here Click here Click here Click here Click here

TL084 Click here Click here Click here Click here Click here TL084A Click here Click here Click here Click here Click here TL084B Click here Click here Click here Click here Click here

TECHNICAL TOOLS & SUPPORT &

DOCUMENTS SOFTWARE COMMUNITY

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: TL081 TL081A TL081B TL082 TL082A TL082B TL084 TL084A TL084B

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-9851501Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

5962-9851501QPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9851501QPA

5962-9851503Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

5962-9851503QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9851503QC

TL081ACD ACTIVE SOIC D 8 75 Green (RoHS

TL081ACDR ACTIVE SOIC D 8 2500 Green (RoHS

TL081ACJG OBSOLETE CDIP JG 8 TBD Call TI Call TI 0 to 70

TL081ACP ACTIVE PDIP P 8 50 Pb-Free

TL081ACPE4 ACTIVE PDIP P 8 50 Pb-Free

TL081BCD ACTIVE SOIC D 8 75 Green (RoHS

TL081BCDR ACTIVE SOIC D 8 2500 Green (RoHS

TL081BCP ACTIVE PDIP P 8 50 Pb-Free

TL081BCPE4 ACTIVE PDIP P 8 50 Pb-Free

TL081CD ACTIVE SOIC D 8 75 Green (RoHS

TL081CDR ACTIVE SOIC D 8 2500 Green (RoHS

TL081CP ACTIVE PDIP P 8 50 Pb-Free

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

(RoHS)

& no Sb/Br)

(RoHS)

& no Sb/Br)

(RoHS)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

9851501Q2A TL082MFKB

TL082M

9851503Q2A TL084 MFKB

A TL084MJB

CU NIPDAU Level-1-260C-UNLIM 0 to 70 081AC

CU NIPDAU N / A for Pkg Type 0 to 70 TL081ACP

CU NIPDAU Level-1-260C-UNLIM 0 to 70 081BC

CU NIPDAU N / A for Pkg Type 0 to 70 TL081BCP

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL081C

CU NIPDAU N / A for Pkg Type 0 to 70 TL081CP

10-Jun-2014

Samples

(4/5)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TL081CPE4 ACTIVE PDIP P 8 50 Pb-Free

TL081CPSR ACTIVE SO PS 8 2000 Green (RoHS

TL081CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI 0 to 70

TL081ID ACTIVE SOIC D 8 75 Green (RoHS

TL081IDG4 ACTIVE SOIC D 8 75 Green (RoHS

TL081IDR ACTIVE SOIC D 8 2500 Green (RoHS

TL081IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS

TL081IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TL081IP ACTIVE PDIP P 8 50 Pb-Free

TL081MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125

TL081MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125

TL081MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125

TL082ACD ACTIVE SOIC D 8 75 Green (RoHS

TL082ACDE4 ACTIVE SOIC D 8 75 Green (RoHS

TL082ACDG4 ACTIVE SOIC D 8 75 Green (RoHS

TL082ACDR ACTIVE SOIC D 8 2500 Green (RoHS

TL082ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082ACP ACTIVE PDIP P 8 50 Pb-Free

TL082ACPE4 ACTIVE PDIP P 8 50 Pb-Free

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

(RoHS)

& no Sb/Br)

(RoHS)

& no Sb/Br)

(RoHS)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU N / A for Pkg Type 0 to 70 TL081CP

CU NIPDAU Level-1-260C-UNLIM 0 to 70 T081

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL081I

CU NIPDAU N / A for Pkg Type -40 to 85 TL081IP

CU NIPDAU Level-1-260C-UNLIM 0 to 70 082AC

CU NIPDAU N / A for Pkg Type 0 to 70 TL082ACP

10-Jun-2014

Samples

(4/5)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TL082ACPSR ACTIVE SO PS 8 2000 Green (RoHS

TL082BCD ACTIVE SOIC D 8 75 Green (RoHS

TL082BCDE4 ACTIVE SOIC D 8 75 Green (RoHS

TL082BCDG4 ACTIVE SOIC D 8 75 Green (RoHS

TL082BCDR ACTIVE SOIC D 8 2500 Green (RoHS

TL082BCDRE4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082BCP ACTIVE PDIP P 8 50 Pb-Free

TL082BCPE4 ACTIVE PDIP P 8 50 Pb-Free

TL082CD ACTIVE SOIC D 8 75 Green (RoHS

TL082CDE4 ACTIVE SOIC D 8 75 Green (RoHS

TL082CDG4 ACTIVE SOIC D 8 75 Green (RoHS

TL082CDR ACTIVE SOIC D 8 2500 Green (RoHS

TL082CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082CJG OBSOLETE CDIP JG 8 TBD Call TI Call TI 0 to 70

TL082CP ACTIVE PDIP P 8 50 Pb-Free

TL082CPE4 ACTIVE PDIP P 8 50 Pb-Free

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

(RoHS)

& no Sb/Br)

(RoHS)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082A

CU NIPDAU Level-1-260C-UNLIM 0 to 70 082BC

CU NIPDAU N / A for Pkg Type 0 to 70 TL082BCP

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL082C

CU NIPDAU N / A for Pkg Type 0 to 70 TL082CP

10-Jun-2014

Samples

(4/5)

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TL082CPSR ACTIVE SO PS 8 2000 Green (RoHS

TL082CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS

TL082CPW ACTIVE TSSOP PW 8 150 Green (RoHS

TL082CPWE4 ACTIVE TSSOP PW 8 150 Green (RoHS

TL082CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS

TL082CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI 0 to 70

TL082CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS

TL082CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS

TL082ID ACTIVE SOIC D 8 75 Green (RoHS

TL082IDG4 ACTIVE SOIC D 8 75 Green (RoHS

TL082IDR ACTIVE SOIC D 8 2500 Green (RoHS

TL082IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

TL082IJG OBSOLETE CDIP JG 8 TBD Call TI Call TI -40 to 85

TL082IP ACTIVE PDIP P 8 50 Pb-Free

TL082IPE4 ACTIVE PDIP P 8 50 Pb-Free

TL082IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS

TL082IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS

TL082MFK OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

(RoHS)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM 0 to 70 T082

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL082I

CU NIPDAU N / A for Pkg Type -40 to 85 TL082IP

CU NIPDAU Level-1-260C-UNLIM -40 to 85 Z082

10-Jun-2014

Samples

(4/5)

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TL082MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

TL082MJG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 TL082MJG

TL082MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 9851501QPA

TL084ACD ACTIVE SOIC D 14 50 Green (RoHS

TL084ACDE4 ACTIVE SOIC D 14 50 Green (RoHS

TL084ACDR ACTIVE SOIC D 14 2500 Green (RoHS

TL084ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS

TL084ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS

TL084ACN ACTIVE PDIP N 14 25 Pb-Free

TL084ACNSR ACTIVE SO NS 14 2000 Green (RoHS

TL084ACNSRG4 ACTIVE SO NS 14 2000 Green (RoHS

TL084BCD ACTIVE SOIC D 14 50 Green (RoHS

TL084BCDE4 ACTIVE SOIC D 14 50 Green (RoHS

TL084BCDR ACTIVE SOIC D 14 2500 Green (RoHS

TL084BCDRG4 ACTIVE SOIC D 14 2500 Green (RoHS

TL084BCN ACTIVE PDIP N 14 25 Pb-Free

TL084BCNE4 ACTIVE PDIP N 14 25 Pb-Free

TL084CD ACTIVE SOIC D 14 50 Green (RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

(RoHS)

& no Sb/Br)

(RoHS)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

9851501Q2A TL082MFKB

TL082M

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084AC

CU NIPDAU N / A for Pkg Type 0 to 70 TL084ACN

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084A

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084BC

CU NIPDAU N / A for Pkg Type 0 to 70 TL084BCN

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C

10-Jun-2014

Samples

(4/5)

Addendum-Page 5

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TL084CDE4 ACTIVE SOIC D 14 50 Green (RoHS

TL084CDG4 ACTIVE SOIC D 14 50 Green (RoHS

TL084CDR ACTIVE SOIC D 14 2500 Green (RoHS

TL084CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS

TL084CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS

TL084CJ OBSOLETE CDIP J 14 TBD Call TI Call TI 0 to 70 TL084CN ACTIVE PDIP N 14 25 Pb-Free

TL084CNE4 ACTIVE PDIP N 14 25 Pb-Free

TL084CNSLE OBSOLETE SO NS 14 TBD Call TI Call TI 0 to 70

TL084CNSR ACTIVE SO NS 14 2000 Green (RoHS

TL084CNSRG4 ACTIVE SO NS 14 2000 Green (RoHS

TL084CPW ACTIVE TSSOP PW 14 90 Green (RoHS

TL084CPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS

TL084CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS

TL084CPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI 0 to 70

TL084CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS

TL084ID ACTIVE SOIC D 14 50 Green (RoHS

TL084IDE4 ACTIVE SOIC D 14 50 Green (RoHS

TL084IDG4 ACTIVE SOIC D 14 50 Green (RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

(RoHS)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084C

CU NIPDAU N / A for Pkg Type 0 to 70 TL084CN

CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL084

CU NIPDAU Level-1-260C-UNLIM 0 to 70 T084

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I

10-Jun-2014

Samples

(4/5)

Addendum-Page 6

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TL084IDR ACTIVE SOIC D 14 2500 Green (RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I

& no Sb/Br)

TL084IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I

& no Sb/Br)

TL084IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL084I

& no Sb/Br)

TL084IJ OBSOLETE CDIP J 14 TBD Call TI Call TI -40 to 85

TL084IN ACTIVE PDIP N 14 25 Pb-Free

CU NIPDAU N / A for Pkg Type -40 to 85 TL084IN

(RoHS)

TL084INE4 ACTIVE PDIP N 14 25 Pb-Free

CU NIPDAU N / A for Pkg Type -40 to 85 TL084IN

(RoHS)

TL084MFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 TL084MFK

TL084MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

TL084MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TL084MJ

TL084MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9851503QC

TL084QD ACTIVE SOIC D 14 50 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q

& no Sb/Br)

TL084QDG4 ACTIVE SOIC D 14 50 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q

& no Sb/Br)

TL084QDR ACTIVE SOIC D 14 2500 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q

& no Sb/Br)

TL084QDRG4 ACTIVE SOIC D 14 2500 Green (RoHS

CU NIPDAU Level-1-260C-UNLIM -40 to 125 TL084Q

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

10-Jun-2014

Op Temp (°C) Device Marking

(4/5)

9851503Q2A TL084 MFKB

A TL084MJB

Samples

Addendum-Page 7

PACKAGE OPTION ADDENDUM

www.ti.com

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

10-Jun-2014

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL082, TL082M, TL084, TL084M :

Catalog: TL082, TL084

•

Automotive: TL082-Q1, TL082-Q1

•

Military: TL082M, TL084M

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 8

PACKAGE OPTION ADDENDUM

www.ti.com

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Military - QML certified for Military and Defense Applications

•

10-Jun-2014

Addendum-Page 9

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

TL081ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL081BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL081CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL081CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL081IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL082ACPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL082BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL082CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL082CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TL082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL082IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2016

Device Package

Type

TL084ACNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

TL084BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL084CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL084CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TL084IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL084QDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL084QDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL081ACDR SOIC D 8 2500 340.5 338.1 20.6

TL081BCDR SOIC D 8 2500 340.5 338.1 20.6

TL081CDR SOIC D 8 2500 340.5 338.1 20.6

TL081CPSR SO PS 8 2000 367.0 367.0 38.0

TL081IDR SOIC D 8 2500 340.5 338.1 20.6 TL082ACDR SOIC D 8 2500 367.0 367.0 35.0 TL082ACDR SOIC D 8 2500 340.5 338.1 20.6

TL082ACPSR SO PS 8 2000 367.0 367.0 38.0

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Mar-2016

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL082BCDR SOIC D 8 2500 340.5 338.1 20.6

TL082CDR SOIC D 8 2500 340.5 338.1 20.6

TL082CDR SOIC D 8 2500 367.0 367.0 35.0 TL082CPSR SO PS 8 2000 367.0 367.0 38.0 TL082CPWR TSSOP PW 8 2000 367.0 367.0 35.0

TL082IDR SOIC D 8 2500 367.0 367.0 35.0 TL082IDR SOIC D 8 2500 340.5 338.1 20.6

TL082IPWR TSSOP PW 8 2000 367.0 367.0 35.0 TL084ACDR SOIC D 14 2500 367.0 367.0 38.0 TL084ACDR SOIC D 14 2500 333.2 345.9 28.6

TL084ACNSR SO NS 14 2000 367.0 367.0 38.0

TL084BCDR SOIC D 14 2500 333.2 345.9 28.6

TL084CDR SOIC D 14 2500 367.0 367.0 38.0 TL084CDR SOIC D 14 2500 333.2 345.9 28.6

TL084CDRG4 SOIC D 14 2500 333.2 345.9 28.6

TL084CPWR TSSOP PW 14 2000 367.0 367.0 35.0

TL084IDR SOIC D 14 2500 333.2 345.9 28.6

TL084QDR SOIC D 14 2500 367.0 367.0 38.0

TL084QDRG4 SOIC D 14 2500 367.0 367.0 38.0

Pack Materials-Page 3

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.063 (1,60)

0.015 (0,38)

0.100 (2,54)

8

1

5

4

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.023 (0,58)

0.015 (0,38)

0.280 (7,11)

0.245 (6,22)

0.310 (7,87)

0.290 (7,37)

0.200 (5,08) MAX Seating Plane

0.130 (3,30) MIN

0°–15°

0.014 (0,36)

0.008 (0,20)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

4040107/C 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OUTLINE

A

3.1

2.9

NOTE 3

SCALE 2.800

6.6 TYP

6.2

PIN 1 ID AREA

1

4

B

4.5

4.3

NOTE 4

8

5

6X 0.65

2X

1.95

0.30

8X

0.19

0.1 C A B

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

1.2 MAX

SEE DETAIL A

(0.15) TYP

0.25

GAGE PLANE

0 - 8

0.75

0.50

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

0.15

0.05

www.ti.com

EXAMPLE BOARD LAYOUT

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

8X (0.45)

6X (0.65)

SOLDER MASK OPENING

1

4

8X (1.5)

METAL

SYMM

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER SOLDER MASK

(R ) TYP

8

SYMM

5

0.05

SOLDER MASK OPENING

0.05 MAX ALL AROUND

NON SOLDER MASK

DEFINED

0.05 MIN ALL AROUND

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

4221848/A 02/2015

EXAMPLE STENCIL DESIGN

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

8X (0.45)

6X (0.65)

1

4

8X (1.5)

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

(R ) TYP0.05

8

SYMM

5

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments TL081ACD, TL081ACP, TL081BCD, TL081BCP, TL081CD Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features 3 Description

2 Applications

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics for TL08xC, TL08xxC, and TL08xI

6.6 Electrical Characteristics for TL08xM and TL084x

6.7 Operating Characteristics

6.8 Dissipation Rating Table

6.9 Typical Characteristics

7 Parameter Measurement Information

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Total Harmonic Distortion

8.3.2 Slew Rate

8.4 Device Functional Modes

9 Applications and Implementation

9.1 Application Information

9.2 Typical Applications

9.2.1 Inverting Amplifier Application

9.2.1.1 Design Requirements

9.2.1.2 Detailed Design Procedure

9.2.1.3 Application Curve

9.3 System Examples

9.3.1 General Applications

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

11.2 Layout Examples

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

12.3 Community Resources

12.4 Trademarks

12.5 Electrostatic Discharge Caution

12.6 Glossary

13 Mechanical, Packaging, and Orderable Information