TEXAS INSTRUMENTS TIBPAL22VP10-20C, TIBPAL22VP10-25M Technical data
查询TIBPAL22VP10-20C供应商
HIGH-PERFORMANCE
IMPACT-X
TIBPAL22VP10-20C, TIBPAL22VP10-25M
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991
• Functionally Equivalent to the
TIBPAL22V10/10A, with Additional
Feedback Paths in the Output Logic
Macrocell
• Choice of Operating Speeds:
TIBPAL22VP10-20C . . . 20 ns Max
TIBPAL22VP10-25M . . . 25 ns Max
• Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
• Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
C SUFFIX . . . NT PACKAGE
M SUFFIX . . . JT PACKAGE
(TOP VIEW)
CLK/I
GND
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
I
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
• TTL-Level Preload for Improved Testability
• Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
• Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
• AC and DC Testing Done at the Factory
Utilizing Special Designed-In Test Features
• Dependable Texas Instruments Quality and
Reliability
• Package Options Include Plastic
Dual-In-Line and Chip Carrier Packages
description
The TIBPAL22VP10’ is equivalent to the
TIBPAL22V10A but offers additional flexibility in
the output structure. The improved output
macrocell uses the registered outputs as inputs
when in a high-impedance condition. This
provides two additional output configurations for a
total of six possible macrocell configurations all of
which are shown in Figure 1.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting. In addition, the data may be fed back into the array from either the register or the
I/O port. The ten potential outputs are enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
CC
I
I
3212827
426
5
I
6
I
7
I
8
NC
9
I
10
I
11
I
12 13
14 15 16 1718
I
I
NC – No internal connection
Pin assignments in operating mode
V
CLK/INCI/O/Q
NC
GND
I
I/O/Q
25
24
23
22
21
20
19
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1991, Texas Instruments Incorporated
1
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE
SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBP AL22VP10’ of fers quick design and development of custom LSI functions with complexities of 500 to 800
equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a
temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and
10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power-up with their outputs high. Registered
outputs selected as active-high power-up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
IMPACT-X
PROGRAMMABLE ARRAY LOGIC CIRCUITS
The TIBPAL22V10-20C is characterized for operation from 0°C to 75°C. The TIBPAL22V10-25M is
characterized for operation over the full military temperature range of –55°C to 125°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
HIGH-PERFORMANCE
IMPACT-X
functional block diagram (positive logic)
TIBPAL22VP10-20C, TIBPAL22VP10-25M
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991
CLK/I
C1
1S
R
Output
Logic
Macrocell
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
10
10
12
14
16
16
14
12
10
Set
Reset
8
8
1
10
10
&
44 x 132
22
11
I
10
22
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE
SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991
IMPACT-X
PROGRAMMABLE ARRAY LOGIC CIRCUITS
(to all registers)
Asynchronous Reset
32 36 40
Increments
I/O/Q
23
cell
Macro-
R = 5809
P = 5808
I/O/Q
22
cell
Macro-
R = 5811
P = 5810
I/O/Q
21
cell
Macro-
R = 5813
P = 5812
I/O/Q
20
cell
Macro-
R = 5815
P = 5814
I/O/Q
19
cell
Macro-
R = 5817
P = 5816
0 4 8 1216202428
3960440
1
CLK/I
First
Fuse
Numbers
logic symbol (positive logic)
4
880
924
2
I
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1452
1496
3
I
2112
2156
4
I
2860
5
I
18
I/O/Q
HIGH-PERFORMANCE
IMPACT-X
I/O/Q
17
TIBPAL22VP10-20C, TIBPAL22VP10-25M
PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991
Synchronous Set
(to all registers)
I
13
16
I/O/Q
15
I/O/Q
I/O/Q
14
cell
Macro-
R = 5819
P = 5818
cell
Macro-
R = 5821
P = 5820
cell
Macro-
R = 5823
P = 5822
cell
Macro-
R = 5825
P = 5824
cell
Macro-
R = 5827
P = 5826
2904
3608
3652
6
I
4268
4312
7
I
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4840
4884
8
I
5324
5368
9
I
5720
10
5764
11
I
I
Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.
Fuse number = First fuse number + Increment
5
TIBPAL22VP10-20C, TIBPAL22VP10-25M
HIGH-PERFORMANCE
SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991
output logic macrocell diagram
IMPACT-X
PROGRAMMABLE ARRAY LOGIC CIRCUITS
Output Logic Macrocell
MUX
2
S1
S0
3
0
1
0
1
G
3
0
I = 0
S2
R
1D
C1
1S
MUX
1/2/3
0
1
G
3
0
†
AR
SS
From Clock Buffer
AR = asynchronous reset
SS = synchronous set
†
This fuse is unique to the Texas Instruments TIBPAL22VP10’. It allows feedback from the I/O port using registered outputs as shown in the
macrocell fusing logic function table.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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