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TIBPAL20R6-10CNT
Datasheet
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Texas Instruments TIBPAL20L8-10CFN, TIBPAL20L8-10CNT, TIBPAL20R6-10CFN, TIBPAL20R6-10CNT, TIBPAL20R8-10CFN Datasheet

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TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
CIRCUITS
• High-Performance Operation:
f
(no feedback)
max
TIBPAL20R’ . . . 71.4 MHz
f
(internal feedback)
max
TIBPAL20R’...58.8 MHz
(external feedback)
f
max
TIBPAL20R’ . . . 55.5 MHz
Propagation Delay
TIBPAL20’ . . . 10 ns Max
• Functionally Equivalent, but Faster Than
Existing 24-Pin PLD Circuits
• Preload Capability on Output Registers
Simplifies Testing
• Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High)
• Package Options Include Plastic Chip
Carriers in Addition to Plastic and Ceramic DIPs
• Security Fuse Prevents Duplication
• Dependable Texas Instruments Quality and
Reliability
DEVICE
PAL20L8 14 2 0 6 PAL20R4 12 0 4 (3-state buffers) 4 PAL20R6 12 0 6 (3-state buffers) 2 PAL20R8 12 0 8 (3-state buffers) 0
I
INPUTS
description
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
NC
TIBPAL20L8’
JT OR NT PACKAGE
(TOP VIEW)
NC
NC
24 23 22 21 20 19 18 17 16 15 14 13
V
I
CC
V I O I/O I/O I/O I/O I/O I/O O I I
I
I
CC
O
25 24 23 22 21 20 19
O
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
I
11
GND
I I I
I I I
12
TIBPAL20L8’
FN PACKAGE
(TOP VIEW)
I
I
I
3212827
426
5 6 7 8 9
10
11
12 13
14 15 16 17 18
I
I
GND
I/O I/O I/O NC I/O I/O I/O
These programmable array logic devices feature high speed and functional equivalency when
NC
– No internal connection
Pin assignments in operating mode
compared with currently available devices. These IMP ACT -X circuits combine the latest Advanced
Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board space.
All of the register outputs are set to a low level during power up. Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state. This feature simplifies testing because the registers can be set to an initial state prior to executing the test sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C.
These devices are covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices Inc.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1992, Texas Instruments Incorporated
1
TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
CIRCUITS
TIBPAL20R4’
JT OR NT PACKAGE
(TOP VIEW)
1
CLK
I I I I I I I I I I
GND
TIBPAL20R6’
JT OR NT PACKAGE
CLK
I I I I I I I I I I
GND
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
V I
I/O I/O Q Q Q Q I/O I/O I OE
V I
I/O Q Q Q Q Q Q I/O I OE
CC
CC
TIBPAL20R4’
FN PACKAGE
(TOP VIEW)
CC
I
I
4
3 2 1 282726
5 I/O
I
6
I
7
I
8
NC
9
I
10
I
11 19
I
12 13 14 15 16 17 18
I
I
TIBPAL20R6’
FN PACKAGE
(TOP VIEW)
I
I
4
3 2 1 282726
5Q
I
6
I
7
I
8
NC
9
I
10
I
11 19
I
12 13 14 15 16 17 18
I
I
V
CLKNCI
OE
NC
GND
CC
V
CLKNCI
OE
NC
GND
I/O
25
Q
24
Q
23
NC
22
Q
21
Q
20
I/O
I
I/O
I/O
25
Q
24
Q
23
NC
22
Q
21
Q
20
Q
I
I/O
TIBPAL20R8’
JT OR NT PACKAGE
(TOP VIEW)
1
CLK
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
I
11
I
12
GND
Pin assignments in operating mode
2
24 23 22 21 20 19 18 17 16 15 14 13
V
CC
I Q Q Q Q Q Q Q Q I OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20R8’
FN PACKAGE
(TOP VIEW)
I
I
4
3 2 1 282726
5Q
I
6
I
7
I
8
NC
9
I
10
I
11
I
12 13 14 15 16 17 18
I
I
– No internal connection
NC
CC
CLKNCI
V
NC
OE
GND
Q
25
Q
24
Q
23
NC
22
Q
21
Q
20 19
Q
I
Q
functional block diagrams (positive logic)
TIBPAL20L8-10C, TIBPAL20R4-10C
HIGH-PERFORMANCE IMPACT-XPAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
TIBPAL20L8’
CIRCUITS
OE
CLK
14 20
I
20 x
&
40 X 64
206
TIBPAL20R4’
7
7
7
7
7
7
7
7
6
EN
≥1
O
O
I/O
I/O
I/O
I/O
I/O
I/O
EN 2
C1
denotes fused inputs
12 20
I
4
20 x
1D
I = 0
2
Q
Q
Q
Q
I/O
I/O
I/O
I/O
&
40 X 64
204
8
8
8
8
7
7
7
7
4
≥1
≥1
EN
4
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3
TIBPAL20R6-10C, TIBPAL20R8-10C HIGH-PERFORMANCE IMPACT-XPAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
functional block diagrams (positive logic)
CIRCUITS
TIBPAL20R6’
OE
CLK
12 20
I
6
20 x
EN 2
C1
1D
I = 0
2
Q
Q
Q
Q
Q
Q
I/O
I/O
&
40 X 64
202
8
8
8
8
8
8
7
7
2
≥1
≥1
EN
6
CLK
denotes fused inputs
OE
12 20
I
20 x
TIBPAL20R8’
EN 2
C1
1D
I = 0
2
Q
Q
Q
Q
Q
Q
Q
Q
&
40 X 64
208
8
8
8
8
8
8
8
8
8
≥1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
I
HIGH-PERFORMANCE IMPACT-XPAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
Increment
TIBPAL20L8-10C
CIRCUITS
2
I
First Fuse Numbers
120 160 200 240 280
3
I
320 360 400 440 480 520 560 600
4
I
640 680 720 760 800 840 880 920
5
I
960 1000 1040 1080 1120 1160 1200 1240
6
I
1280 1320 1360 1400 1440 1480 1520 1560
7
I
1600 1640 1680 1720 1760 1800 1840 1880
8
I
1920 1960 2000 2040 2080 2120 2160 2200
9
I
2240 2280 2320 2360 2400 2440 2480 2520
10
I
11
I
4 8 12 16 20 24 28 32
0 40 80
36 390
23
I
22
O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
O
14
I
13
I
Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL20R4-10C HIGH-PERFORMANCE IMPACT-XPAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
CIRCUITS
2
I
First Fuse Numbers
0 40 80
120 160 200 240 280
3
I
320 360 400 440 480 520 560 600
4
I
640 680 720 760 800 840 880 920
5
I
960 1000 1040 1080 1120 1160 1200 1240
6
I
1280 1320 1360 1400 1440 1480 1520 1560
7
I
1600 1640 1680 1720 1760 1800 1840 1880
8
I
1920 1960 2000 2040 2080 2120 2160 2200
9
I
2240 2280 2320 2360 2400 2440 2480 2520
10
I
11
I
Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.
4 8 12 16 20 24 28 32
36 390
23
I
22
I/O
21
I/O
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
20
19
18
17
16
15
14
13
Q
Q
Q
Q
I/O
I/O
I
OE
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
CLK
HIGH-PERFORMANCE IMPACT-XPAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
Increment
TIBPAL20R6-10C
CIRCUITS
2
I
First Fuse Numbers
0 40 80
120 160 200 240 280
3
I
320 360 400 440 480 520 560 600
4
I
640 680 720 760 800 840 880 920
5
I
960 1000 1040 1080
1120
1160 1200 1240
6
I
1280 1320 1360 1400 1440 1480 1520 1560
7
I
1600 1640 1680 1720 1760 1800 1840 1880
8
I
1920 1960 2000 2040 2080 2120 2160 2200
9
I
2240 2280 2320 2360 2400 2440 2480 2520
10
I
11
I
Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.
4 8 12 16 20 24 28 32
36 390
23
I
22
I/O
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
21
20
19
18
17
16
15
14
13
Q
Q
Q
Q
Q
Q
I/O
I
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL20R8-10C HIGH-PERFORMANCE IMPACT-XPAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
CIRCUITS
2
I
First Fuse Numbers
0 40 80
120 160 200 240 280
3
I
320 360 400 440 480 520 560 600
4
I
640 680 720 760 800 840 880 920
5
I
960 1000 1040 1080
1120
1160 1200 1240
6
I
1280 1320 1360 1400 1440 1480 1520 1560
7
I
1600 1640 1680 1720 1760 1800 1840 1880
8
I
1920 1960 2000 2040 2080 2120 2160 2200
9
I
2240 2280 2320 2360 2400 2440 2480 2520
10
I
11
I
Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.
4 8 12 16 20 24 28 32
36 390
23
I
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
I = 0
1D
C1
22
21
20
19
18
17
16
15
14
13
Q
Q
Q
Q
Q
Q
Q
Q
I
OE
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
†
w
†
t
su
†
t
h
T
A
†
f
clock
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
Supply voltage 4.75 5 5.25 V High-level input voltage 2 5.5 V Low-level input voltage 0.8 V High-level output current –3.2 mA Low-level output current 24 mA
†
Clock frequency 0 71.4 MHz Pulse duration, clock (see Note 2)t
Setup time, input or feedback before clock↑ 10 ns Hold time, input or feedback after clock↑ 0 ns
Operating free-air temperature 0 25 75 °C
, tw, tsu, and th do not apply for TIBPAL20L8’.
noise. Testing these parameters should not be attempted without suitable equipment.
High 7 Low 7
CIRCUITS
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
OH
V
OL
I
OZH
I
OZL
I
I
I
IH
I
IL
I
OS
I
CC
C
i
C
o
C
clk
O, Q outputs 20
‡
I/O ports 100 O, Q outputs –20
‡
I/O ports –100
‡
‡
§
VCC = 4.75 V, II = –18 mA –0.8 –1.5 V VCC = 4.75 V, IOH = –3.2 mA 2.4 V VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
VCC = 5.25 V,
VCC = 5.25 V,
VCC = 5.25 V, VI = 5.5 V 0.2 mA VCC = 5.25 V, VI = 2.7 V 25 µA VCC = 5.25 V, VI = 0.4 V –0.25 mA VCC = 5.25 V, VO = 0.5 V –30 –70 –130 mA
VCC = 5.25 V, Outputs open,
f = 1 MHz, VI = 2 V 7 pF f = 1 MHz, VO = 2 V 8 pF f = 1 MHz, V
CIRCUITS
VO = 2.7 V
VO = 0.4 V
VI = 0,
= V
OE
IH
= 2 V 12 pF
CLK
µA
µA
210 mA
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
f
max
t
pd
t
pd
#
t
pd
t
en
t
dis
t
en
t
dis
||
t
sk(o)
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
I/O leakage is the worst case of I
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.
See section for f
#
This parameter applies to TIBPAL20R4’ and TIBPAL20R6’ only (see Figure 4 for illustration) and is calculated from the measured f feedback in the counter configuration.
||
This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Q) observed when multiple registered outputs are switching in the same direction.
max
FROM
(INPUT)
without feedback 71.4
with internal feedback
(counter configuration) with external feedback 55.5
I, I/O O, I/O R1 = 200 Ω, 3 8 10
CLK↑ Q R2 = 390 Ω, 2 5 8 ns CLK↑ Feedback input See Figure 6 7 ns
OE↓ Q 2 6 10 ns OE↑ Q 2 6 10 ns I, I/O O, I/O 3 8 10 ns I, I/O O, I/O 2 8 10 ns
Skew between registered outputs 0.5 ns
and IIL or I
OZL
specifications. f
max
OZH
does not apply for TIBPAL20L8’.
TO
(OUTPUT)
and IIH respectively.
TEST CONDITION MIN TYP†MAX UNIT
58.8 MHz
with internal
max
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming T exas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below.
Step 1. With V
at 5 volts and Pin 1 at VIL, raise Pin 13 to V
CC
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Step 3. Pulse Pin 1, clocking in preload data. Step 4. Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the
voltage level at the output pin.
Pin 13
t
Pin 1
t
t
d
su
t
w
.
IHH
d
CIRCUITS
V
IHH
V
IL
V
IH
V
IL
Registered I/O Input Output
NOTE 3: td = tsu = th = 100 ns to 1000 ns V
Figure 1. Preload Waveforms
= 10.25 V to 10.75 v
IHH
V
IH
V
IL
V
OH
V
OL
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11
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
4 V
CIRCUITS
†
t
pd
(600 ns TYP, 1000 ns MAX)
1.5 V
1.5 V
t
w
‡
t
su
1.5 V
HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met.
V
CC
Active Low
Registered Output
CLK
5 V
V
V
V
V
OH
OL
IH
IL
†
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
f
SPECIFICATIONS
max
without feedback, see Figure 3
f
max
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback. Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t However, the minimum f
f
Thus,
without feedback
max
is determined by the minimum clock period (tw high + tw low).
max
+
(twhigh
1
)
twlow)
CLK
or
1
(tsu)
th)
.
CIRCUITS
su
+ th).
f
with internal feedback, see Figure 4
max
LOGIC
ARRAY
tsu + t
tw high + tw low
Figure 3. f
h
or
Without Feedback
max
C1
1D
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
Thus,
f
with internal feedback
max
+
(tsu)
1
tpdCLK*to*FB)
.
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
LOGIC
ARRAY
C1
1D
t
su
Figure 4. f
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
With Internal Feedback
max
tpd CLK-to-FB
13
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
with external feedback, see Figure 5
f
max
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals
+ tpd CLK-to-Q).
(t
su
f
Thus,
with external feedback
max
CIRCUITS
f
SPECIFICATIONS
max
+
(tsu)
CLK
tpdCLK*to*Q)
1
.
LOGIC
ARRAY
t
su
Figure 5. f
C1
1D
tpd CLK-to-Q t
With External Feedback
max
NEXT DEVICE
su
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output Under Test
Test Point
CIRCUITS
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
1.5 V
t
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
pd
1.5 V
t
pd
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
(see Note A)
3.5 V
0.3 V
t
h
3.5 V
0.3 V
3.5 V
0.3 V
t
pd
V
OH
1.5 V V
OL
t
pd
V
OH
V
OL
C
L
LOAD CIRCUIT FOR
3-STATE OUTPUTS
High-Level
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
R2
3.5 V
Pulse
Low-Level
Pulse
VOLTAGE WAVEFORMS
t
en
1.5 V 1.5 V
t
w
1.5 V 1.5 V
PULSE DURATIONS
1.5 V 1.5 V
t
dis
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
≈ 3.3 V
1.5 V
t
t
en
dis
1.5 V
VOL +0.5 V
V
V
VOH –0.5 V
≈ 0 V
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
OL
OH
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. W aveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf ≤ 2 ns, duty cycle = 50%. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dis
.
15
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
220
CIRCUITS
PROPAGATION DELAY TIME
SUPPLY VOLTAGE
8
vs
200
180
160
VCC = 4.75 V
140
– Supply Current – mA
CC
I
120
100
02550
TA – Free-Air T emperature – °C
VCC = 5.25 V
VCC = 5 V
Figure 7
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
8
7
t
6
(I, I/O to O, I/O)
PHL
75
7
6
5
4
3
TA = 25 °C
2
Propagation Delay Time – ns
CL = 50 pF R1 = 200 Ω
1
R2 = 390 Ω 1 Output Switching
0
4.75 5
PROPAGATION DELAY TIME
16
VCC = 5 V TA = 25 °C
14
R1 = 200 Ω R2 = 390 Ω
1 Output Switching
12
t
(I, I/O to O, I/O)
PHL
t
(I, I/O to O, I/O)
PLH
t
(CLK to Q)
PHL
t
(CLK to Q)
PLH
VCC – Supply Voltage – V
Figure 8
vs
LOAD CAPACITANCE
5.25
16
t
5
Propagation Delay Time – ns
4
3
2
1
0
t
(CLK to Q)
PHL
VCC = 5 V CL = 50 pF R1 = 200 Ω R2 = 390 Ω
1 Output Switching
02550
TA – Free-Air T emperature – °C
(I, I/O to O, I/O)
PLH
t
(CLK to Q)
PLH
Figure 9
10
8
6
4
Propagation Delay Time – ns
2
75
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0
0 600
t
PHL
t
(I, I/O to O, I/O)
PHL
t
(I, I/O to O, I/O)
PLH
100 200 300 400
CL – Load Capacitance – pF
Figure 10
t
(CLK to Q)
PLH
(CLK to Q)
500
1000
900
VCC = 5 V
TA = 0 °C
TIBPAL20L8-10C, TIBPAL20R4-10C, TIBPAL20R6-10C, TIBPAL20R8-10C
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
FREQUENCY
8-BIT COUNTER MODE
HIGH-PERFORMANCE IMPACT-X PAL
SRPS008A – D3336, OCTOBER 1989 – REVISED MARCH 1992
PROPAGATION DELAY TIME
vs
NUMBER OF OUTPUTS SWITCHING
0.8 VCC = 5 V TA = 25 °C
0.7
R1 = 200 Ω R2 = 390 Ω CL = 50 pF
0.6 8-Bit Counter
0.5
CIRCUITS
†
800
– Power Dissipation – mW
700
D
P
600
TA = 25 °C
TA = 80 °C
1 4 10 40 100
F – Frequency – MHz
Figure 11
NUMBER OF OUTPUTS SWITCHING
8
7
6
t
PLH
5
0.4
0.3
0.2
– Skew Between Outputs Switching – ns
0.1
sk(o)
t
PROPAGATION DELAY TIME
vs
t
(I, I/O to O, I/O)
PHL
(I, I/O to O, I/O)
0
23 4 56
Number of Outputs Switching
Figure 12
78
4
3
2
Propagation Delay Time – ns
1
0
†
Outputs switching in the same direction (t
t
PHL
t
(CLK to Q)
PLH
VCC = 5 V TA = 25 °C CL = 50 pF R1 = 200 Ω R2 = 390 Ω
012345
Number of Outputs Switching
Figure 13
PLH compared to
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
PLH/tPHL to
t
(CLK to Q)
678
PHL)
17
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*Not authorized for TI military products
1992 T exas Instruments Incorporated
B0892
TI North American Sales Offices
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Dallas: Anthem (214) 238-7100; Arrow/Schweber (214) 380-6464; Hall-Mark (214) 553-4300; Marshall (214) 233-5200; Wyle (214) 235-9953; Zeus (214) 783-7010;
Houston: Arrow/Schweber (713) 530-4700; Hall-Mark (713) 781-6100; Marshall (713) 467-1666; Wyle (713) 879-9953.
UTAH: Anthem (801) 973-8555; Arrow/Schweber (801) 973-6913; Marshall (801) 973-2288; Wyle (801) 974-9953.
WASHINGTON: Almac/Arrow (206) 643-9992, Anthem (206) 483-1700; Marshall (206) 486-5747; Wyle (206) 881-1150.
WISCONSIN: Arrow/Schweber (414) 792-0150; Hall-Mark (414) 797-7844; Marshall (414) 797-8400.
CANADA: Calgary: Future (403) 235-5325; Edmonton: Future (403) 438-2858; Montreal: Arrow/Schweber (514) 421-7411; Future (514)
694-7710; Marshall (514) 694-8142 Ottawa: Arrow/Schweber (613) 226-6903; Future (613) 820-8313.
Quebec: Future (418) 897-6666. Toronto: Arrow/Schweber (416) 670-7769;
Future (416) 612-9200; Marshall (416) 458-8046. Vancouver: Arrow/Schweber (604) 421-2333;
Future (604) 294-1166.
TI Die Processors
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1992 T exas Instruments Incorporated
D0892
SRPS008A
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Copyright 1998, Texas Instruments Incorporated
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