TEXAS INSTRUMENTS TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C, TIBPAL16L8-10M Technical data

查询5962-8515517RA供应商

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992



CIRCUITS

• High-Performance Operation:

f

(no feedback)

max

TIBPAL16R’-7C Series . . . 100 MHz Min
TIBPAL16R’-10M Series . . . 62.5 MHz Min

f

(internal feedback)

max

TIBPAL16R’-7C Series . . . 100 MHz Min
TIBPAL16R’-10M Series . . . 62.5 MHz Min

f

(external feedback)

max

TIBPAL16R’-7C Series . . . 74 MHz Min
TIBPAL16R’-10M Series . . . 52.5 MHz Min

Propagation Delay

TIBPAL16L’-7C Series . . . 7 ns Max
TIBPAL16L’-10M Series . . . 10 ns Max

• Functionally Equivalent, but Faster than,

Existing 20-Pin PLDs

• Preload Capability on Output Registers

Simplifies Testing

• Power-Up Clear on Registered Devices (All

Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)

• Package Options Include Both Plastic and

Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

• Security Fuse Prevents Duplication

• Dependable Texas Instruments Quality and

Reliability

DEVICE

PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0

I

INPUTS

description

3-STATE

O OUTPUTS

REGISTERED

Q OUTPUTS

I/O

PORT

S

TIBPAL16L8’

C SUFFIX . . . J OR N PACKAGE

M SUFFIX . . . J PACKAGE

(TOP VIEW)

I

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

GND

C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE

I
I
I
I
I

Pin assignments in operating mode

10

TIBPAL16L8’

(TOP VIEW)

I

I

3 2 1 20 19

4
5
6
7
8

910111213

I

GND

V

20

CC

O

19

I/O

18

I/O

17

I/O

16
15

I/O

14

I/O

13

I/O

12

O

11

I

CC

I

O

V

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I

O

I/O

These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.

All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.

The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.

These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1992, Texas Instruments Incorporated

1

TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992



CIRCUITS

TIBPAL16R4’

C SUFFIX . . . J OR N PACKAGE

M SUFFIX . . . J PACKAGE

(TOP VIEW)

CLK

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

GND

C SUFFIX . . . J OR N PACKAGE

M SUFFIX . . . J PACKAGE

GND

CLK

I
I
I
I
I
I
I
I

10

TIBPAL16R6’

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

20
19
18
17
16
15
14
13
12
11

V
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE

V
I/O
Q
Q
Q
Q
Q
Q
I/O
OE

CC

CC

TIBPAL16R4’

C SUFFIX . . . FN PACKAGE

M SUFFIX . . . FK PACKAGE

(TOP VIEW)

CC

I

CLK

I/O

V

18
17
16
15
14

3 2 1 20 19

I

4

I

5

I

6

I

7

I

8

910111213

I

I

I/O

I/O

OE

GND

TIBPAL16R6’

C SUFFIX . . . FN PACKAGE

M SUFFIX . . . FK PACKAGE

(TOP VIEW)

I

GND

CLK

OE

CC

V

I/O

I/O

18
17
16
15
14

Q

3 2 1 20 19

I

4

I

5

I

6

I

7

I

8

910111213

I

I

I/O
Q
Q
Q
Q

Q
Q
Q
Q
Q

TIBPAL16R8’

C SUFFIX . . . J OR N PACKAGE

M SUFFIX . . . J PACKAGE

(TOP VIEW)

CLK

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

GND

Pin assignments in operating mode

2

10

V

20

CC

Q

19

Q

18

Q

17

Q

16
15

Q

14

Q

13

Q

12

Q

11

OE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16R8’

C SUFFIX . . . FN PACKAGE

M SUFFIX . . . FK PACKAGE

(TOP VIEW)

I

GND

CLK

OE

CC

V

Q

Q

18
17
16
15
14

Q

3 2 1 20 19

I

4

I

5

I

6

I

7

I

8

910111213

I

I

Q
Q
Q
Q
Q

functional block diagrams (positive logic)

TIBPAL16L8-7C, TIBPAL16R4-7C

TIBPAL16L8-10M, TIBPAL16R4-10M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

TIBPAL16L8 ’



CIRCUITS

OE

CLK

10 16

I

16 x

&

32 X 64

166

TIBPAL16R4’

7

7

7

7

7

7

7

7

6

EN

≥1

O

O

I/O

I/O

I/O

I/O

I/O

I/O

EN 2

C1

denotes fused inputs

816

I

16 x

4

164

&

32 X 64

1D

I = 0

2

Q

Q

Q

Q

I/O

I/O

I/O

I/O

8

8

8

8

7

7

7

7

4

≥1

≥1

EN

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

functional block diagrams (positive logic)



CIRCUITS

TIBPAL16R6 ’

OE

CLK

816

I

16 x

6

162

&

32 X 64

EN 2

C1

1D

I = 0

2

Q

Q

Q

Q

Q

Q

I/O

I/O

8

8

8

8

8

8

7

7

2

≥1

≥1

EN

6

OE

CLK

denotes fused inputs

816

I

16 x

168

TIBPAL16R8’

&

32 X 64

EN 2

C1

1D

I = 0

2

Q

Q

Q

Q

Q

Q

Q

Q

8

8

8

8

8

8

8

8

8

≥1

4

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logic diagram (positive logic)

1

I

First
Fuse
Numbers

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

0 4 8 12 16 20 24 28 31

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

HIGH-PERFORMANCE IMPACT-X PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

Increment

TIBPAL16L8-7C

TIBPAL16L8-10M



CIRCUITS

19

O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

O

11

I

Fuse number = First fuse number + Increment

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TIBPAL16R4-7C
TIBPAL16R4-10M
HIGH-PERFORMANCE IMPACT-X PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

logic diagram (positive logic)

1

CLK

First
Fuse
Numbers

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

0 4812 16 20 24 28 31

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

Fuse number = First fuse number + Increment

Increment



CIRCUITS

I = 0

1D

I = 0

1D

I = 0

1D

I = 0

1D

C1

C1

C1

C1

19

18

17

16

15

14

13

12

11

I/O

I/O

Q

Q

Q

Q

I/O

I/O

OE

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1

CLK

First
Fuse
Numbers

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

Fuse number = First fuse number + Increment

0 4 8 12 16 20 24 28 31

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

HIGH-PERFORMANCE IMPACT-X PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

Increment

TIBPAL16R6-7C

TIBPAL16R6-10M



CIRCUITS

19

I/O

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

18

17

16

15

14

13

12

11

Q

Q

Q

Q

Q

Q

I/O

OE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TIBPAL16R8-7C
TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X PAL

SRPS006D – D31 15, MAY 1988 – REVISED MARCH 1992

logic diagram (positive logic)

1

CLK

First
Fuse
Numbers

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

0 4 8 12 16 20 24 28 31

0
32
64
96

128
160
192
224

256
288
320
352
384
416
448
480

512
544
576
608
640
672
704
736

768
800
832
864
896
928
960
992

1024
1056
1088
1120
1152
1184
1216
1248

1280
1312
1344
1376
1408
1440
1472
1504

1536
1568
1600
1632
1664
1696
1728
1760

1792
1824
1856
1888
1920
1952
1984
2016

Fuse number = First fuse number + Increment

Increment



CIRCUITS

I = 0

1D

I = 0

1D

I = 0

1D

I = 0

1D

I = 0

1D

I = 0

1D

I = 0

1D

I = 0

1D

C1

C1

C1

C1

C1

C1

C1

C1

19

18

17

16

15

14

13

12

11

Q

Q

Q

Q

Q

Q

Q

Q

OE

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

V

IH

V

IL

I

OH

I

OL

f

clock

w

t

su

t

h

T

A

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

Supply voltage 4.75 5 5.25 V
High-level input voltage (see Note 2) 2 5.5 V
Low-level input voltage (see Note 2) 0.8 V
High-level output current –3.2 mA
Low-level output current 24 mA
Clock frequency 0 100 MHz

Pulse duration, clock (see Note 2)t
Setup time, input or feedback before clock↑ 7 ns

Hold time, input or feedback after clock↑ 0 ns
Operating free-air temperature 0 25 75 °C

noise. Testing these parameters should not be attempted without suitable equipment.

High 5
Low 5



CIRCUITS

ns

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

‡

I

OZH

‡

I

OZL

I

I

‡

I

IH

‡

I

IL

§

I

OS

I

CC

C

i

C

o

C

clk

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

I/O leakage is the worst case of I

§

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.

VCC = 4.75 V, II = –18 mA –0.8 –1.5 V
VCC = 4.75 V, IOH = –3.2 mA 2.4 3.2 V
VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V
VCC = 5.25 V, VO = 2.7 V 100 µA
VCC = 5.25 V, VO = 0.4 V –100 µA
VCC = 5.25 V, VI = 5.5 V 100 µA
VCC = 5.25 V, VI = 2.7 V 25 µA
VCC = 5.25 V, VI = 0.4 V –80 –250 µA
VCC = 5.25 V, VO = 0.5 V –30 –70 –130 mA
VCC = 5.25 V, VI = 0, Outputs open 160 180 mA
f = 1 MHz, VI = 2 V 5 pF
f = 1 MHz, VO = 2 V 6 pF
f = 1 MHz, V

and IIL or I

OZL

OZH

= 2 V 6 pF

CLK

and IIH respectively.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

‡

f

max

pd

t

pd

§

t

pd

t

en

t

dis

t

en

t

dis

¶

t

sk(o)

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

See section for f

§

This parameter applies to TIBPAL16R4’ and TIBPAL16R6’ only (see Figure 4 for illustration) and is calculated from the measured f
feedback in the counter configuration.

¶

This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Q) observed when multiple registered outputs
are switching in the same direction.

max

FROM

(INPUT)

without feedback 100

with internal feedback

(counter configuration)
with external feedback 74

I, I/O

CLK↑ Q R2 = 390 Ω, 2 4 6.5 ns
CLK↑ Feedback input See Figure 6 3 ns

OE↓ Q 4 7.5 ns
OE↑ Q 4 7.5 ns
I, I/O O, I/O 6 9 ns
I, I/O O, I/O 6 9 ns

Skew between registered outputs 0.5 ns

specifications.

O, I/Ot



CIRCUITS

TO

(OUTPUT)

1 or 2 outputs switching 3 5.5 7

8 outputs switching R1 = 200 Ω, 3 6 7.5

TEST CONDITION MIN TYP†MAX UNIT

100 MHz

max

ns

with internal

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

V

IH

V

IL

I

OH

I

OL

f

clock
w

†

t

su

†

t

h

T

A

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

Supply voltage 4.5 5 5.5 V
High-level input voltage 2 5.5 V
Low-level input voltage 0.8 V
High-level output current –2 mA
Low-level output current 12 mA

†

Clock frequency 0 62.5 MHz
Pulse duration, clock (see Note 2)t
Setup time, input or feedback before clock↑ 10 ns

Hold time, input or feedback after clock↑ 0 ns
Operating free-air temperature –55 25 125 °C

noise. Testing these parameters should not be attempted without suitable equipment.

High 8
Low 8



CIRCUITS

ns

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

‡

I

OZH

0, Q outputs –0.1

‡

I

OZL

I

I

I

IH

‡

I

IL

I

OS

I

CC

C

i

C

o

C

clk/oe

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

I/O leakage is the worst case of I

§

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.

I/O ports –0.25

I/O ports 100
All others 25

§

VCC = 4.5 V, II = –18 mA –0.8 –1.5 V
VCC = 4.5 V, IOH = –2 mA 2.4 3.2 V
VCC = 4.5 V, IOL = 12 mA 0.3 0.5 V

VCC = 5.5 V, VO = 2.7 V 100 µA

VCC = 5.5 V,
VCC = 5.5 V, VI = 5.5 V 1 mA

VCC = 5.5 V,
VCC = 5.5 V, VI = 0.4 V –0.08 –0.25 mA

VCC = 5.5 V, VO = 0.5 V –30 –70 –130 mA
VCC = 5.5 V, VI = GND, Outputs open 140 200 mA
f = 1 MHz, VI = 2 V 5 pF
f = 1 MHz, VO = 2 V 6 pF
f = 1 MHz, V

and IIL or I

OZL

OZH

VO = 0.4 V

= 2 V 6 pF

CLK/OE

and IIH respectively.

mA

µAVI = 2.7 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006C – D31 15, MAY 1988 – REVISED OCTOBER 1990

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

‡

f

max

t

pd

t

pd

§

t

pd

t

en

t

dis

t

en

t

†
‡

§

dis

All typical values are at VCC = 5 V, TA = 25°C.
See section for f
section.
This parameter applies to TIBPAL16R4’ and TIBPAL16R6’ only (see Figure 4 for illustration) and is calculated from the measured f
feedback in the counter configuration.

max

FROM

(INPUT)

without feedback 62.5

with internal feedback

(counter configuration)
with external feedback 52.5

I, I/O O, I/O R1 = 390 Ω, 2 6 10 ns

CLK↑ Q R2 = 750 Ω, 1 4 9 ns
CLK↑ Feedback input See Figure 6 5 ns

OE↓ Q 1 4 10 ns
OE↑ Q 1 4 10 ns
I, I/O O, I/O 2 6 12 ns
I, I/O O, I/O 1 6 10 ns

specifications. f

with external feedback is not production tested but is calculated from the equation found in the f

max

TO

(OUTPUT)



CIRCUITS

TEST CONDITION MIN TYP†MAX UNIT

62.5 MHz

with internal

max

max

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

programming information

Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming T exas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at [phone].

preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.

Step 1. With V

at 5 volts and Pin 1 at VIL, raise Pin 11 to V

CC

Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the

voltage level at the output pin.

Pin 11

t

Pin 1

t

d

su

t

w

.

IHH

t

d



CIRCUITS

V

IHH

V

IL

V

IH

V

IL

Registered I/O Input Output

NOTE 3: td = tsu = th = 100 ns to 1000 ns V

Figure 1. Preload Waveforms

= 10.25 V to 10.75 v

IHH

V

IH

V

IL

V

OH

V

OL

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M

4 V



CIRCUITS

†

t

pd

(600 ns TYP, 1000 ns MAX)

1.5 V

1.5 V

t

w

‡

t

su

1.5 V

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

power-up reset (see Figure 2)

Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.

V

CC

Active Low

Registered Output

CLK

5 V

V

V

V

V

OH

OL

IH

IL

†

This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.

‡

This is the setup time for input or feedback.

Figure 2. Power-Up Reset Waveforms

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

f

SPECIFICATIONS

max

without feedback, see Figure 3

f

max

In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t
However, the minimum f

f

Thus,

without feedback

max

is determined by the minimum clock period (tw high + tw low).

max

+

(twhigh

1

)

twlow)

CLK

or

1

(tsu)

th)

.



CIRCUITS

su

+ th).

f

with internal feedback, see Figure 4

max

LOGIC

ARRAY

tsu + t

tw high + tw low

Figure 3. f

h

or

Without Feedback

max

C1

1D

This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.

Thus,

f

with internal feedback

max

+

(tsu)

1

tpdCLK*to*FB)

.

Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.

CLK

LOGIC

ARRAY

C1

1D

t

su

Figure 4. f

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

With Internal Feedback

max

tpd CLK-to-FB

15

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

with external feedback, see Figure 5

f

max

This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals

+ tpd CLK-to-Q).

(t

su

f

Thus,

with external feedback

max



CIRCUITS

f

SPECIFICATIONS

max

+

(tsu)

CLK

tpdCLK*to*Q)

1

.

LOGIC

ARRAY

t

su

Figure 5. f

C1

1D

tpd CLK-to-Q t

With External Feedback

max

NEXT DEVICE

su

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

PARAMETER MEASUREMENT INFORMATION

5 V

S1

R1

From Output
Under Test

Test
Point



CIRCUITS

Timing

Input

Data

Input

Input

In-Phase

Output

Out-of-Phase

Output

(see Note D)

1.5 V

t

su

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

t

pd

1.5 V

t

pd

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.5 V

(see Note A)

(3.5 V) [3 V]

(0.3 V) [0]

t

h

(3.5 V) [3 V]

(0.3 V) [0]

(3.5 V) [3 V]

(0.3 V) [0]

t

pd

V

OH

1.5 V
V

OL

t

pd

V

OH

V

OL

C

L

LOAD CIRCUIT FOR

3-STATE OUTPUTS

High-Level

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

R2

(3.5 V) [3 V]

Pulse

Low-Level

Pulse

VOLTAGE WAVEFORMS

t

en

1.5 V 1.5 V

t

w

1.5 V 1.5 V

PULSE DURATIONS

1.5 V 1.5 V

t

dis

(0.3 V) [0]

(3.5 V) [3 V]

(0.3 V) [0]

(3.5 V) [3 V]

(0.3 V) [0]

≈ 3.3 V

1.5 V

t

t

en

dis

1.5 V

VOL +0.5 V

V

V

VOH –0.5 V

≈ 0 V

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

OL

OH

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ), PRR ≤ 1 MHz,

tr = tf = 2 ns, duty cycle = 50%; For M suffix, use the voltage levels indicated in brackets [ ], PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty

cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.

Figure 6. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

dis

.

17

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C
TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

220



CIRCUITS

PROPAGATION DELAY TIME

SUPPLY VOLTAGE

8

vs

200

180

160

140

– Supply Current – mA

CC

I

120

100

–75 –50 –25 0 25 50

TA – Free-Air Temperature – °C

Figure 7

PROPAGATION DELAY TIME

FREE-AIR TEMPERATURE

8

7

6

vs

t

(I, I/O to O, I/O)

PHL

75 100 125

7

6

5

4

3

TA = 25 °C

2

Propagation Delay Time – ns

CL = 50 pF
R1 = 200 Ω

1

R2 = 390 Ω
1 Output Switching

0

4.5 4.75 5

PROPAGATION DELAY TIME

16

VCC = 5 V
TA = 25 °C

14

R1 = 200 Ω
R2 = 390 Ω

1 Output Switching

12

t

(I, I/O to O, I/O)

PHL

t

(I, I/O to O, I/O)

PLH

t

(CLK to Q)

PHL

t

(CLK to Q)

PLH

VCC – Supply Voltage – V

5.25 5.5

Figure 8

vs

LOAD CAPACITANCE

18

5

4

3

2

Propagation Delay Time – ns

1

0

–75 –50 –25 0 25 50

t

(CLK to Q)

PHL

VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω

1 Output Switching

TA – Free-Air Temperature – °C

Figure 9

t

(I, I/O to O, I/O)

PLH

t

PLH

(CLK to Q)

75 100 125

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10

8

6

t

PHL

4

Propagation Delay Time – ns

2

0

100 200 300 400

0 600

CL – Load Capacitance – pF

t

PLH

t

t

(CLK to Q)

PHL

(I, I/O to O, I/O)

(I, I/O to O, I/O)

Figure 10

(CLK to Q)

PLH

500

1000

900

VCC = 5 V

TA = 0 °C

TIBPAL16L8-7C, TIBPAL16R4-7C, TIBPAL16R6-7C, TIBPAL16R8-7C

TIBPAL16L8-10M, TIBPAL16R4-10M, TIBPAL16R6-10M, TIBPAL16R8-10M



CIRCUITS

TYPICAL CHARACTERISTICS

POWER DISSIPATION

vs

FREQUENCY

8-BIT COUNTER MODE

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS006D – D3115, MAY 1988 – REVISED MARCH 1992

PROPAGATION DELAY TIME

vs

NUMBER OF OUTPUTS SWITCHING

0.8
VCC = 5 V
TA = 25 °C

0.7

R1 = 200 Ω
R2 = 390 Ω
CL = 50 pF

0.6
8-Bit Counter

0.5

†

800

– Power Dissipation – mW

700

D

P

600

1 4 10 40 100

TA = 25 °C

TA = 80 °C

F – Frequency – MHz

Figure 11

NUMBER OF OUTPUTS SWITCHING

8

7

6

t

PLH

5

0.4

0.3

0.2

– Skew Between Outputs Switching – ns

0.1

skew

t

PROPAGATION DELAY TIME

vs

t

(I, I/O to O, I/O)

PHL

(I, I/O to O, I/O)

0

23 4 56

Number of Outputs Switching

Figure 12

78

4

3

2

Propagation Delay Time – ns

1

0

012345

†

Outputs switching in the same direction (t

t

PHL

t

(CLK to Q)

PLH

VCC = 5 V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω

Number of Outputs Switching

Figure 13

PLH compared to

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t

PLH/tPHL to

t

PHL)

(CLK to Q)

678

19

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1992 T exas Instruments Incorporated

Printed in U.S.A.

D0892

SRPS006D

PACKAGE OPTION ADDENDUM

www.ti.com

4-Mar-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

5962-85155172A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515517RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515517SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC

5962-85155182A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515518RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515518SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC

5962-85155192A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515519RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515519SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC

5962-85155202A LIFEBUY LCCC FK 20 1 None Call TI Level-NC-NC-NC
5962-8515520RA LIFEBUY CDIP J 20 1 None Call TI Level-NC-NC-NC
5962-8515520SA LIFEBUY CFP W 20 1 None Call TI Level-NC-NC-NC

TIBPAL16L8-10MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC

TIBPAL16L8-10MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC

TIBPAL16L8-10MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC

TIBPAL16L8-7CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM

TIBPAL16L8-7CN ACTIVE PDIP N 20 20 None Call TI Level-NC-NC-NC

TIBPAL16R4-10MFKB LIFEBUY LCCC FK 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R4-10MJB LIFEBUY CDIP J 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R4-10MWB LIFEBUY CFP W 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R4-7CFN OBSOLETE PLCC FN 20 None Call TI Call TI

TIBPAL16R4-7CN OBSOLETE PDIP N 20 None Call TI Call TI

TIBPAL16R6-10MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R6-10MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R6-10MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R6-7CFN ACTIVE PLCC FN 20 46 None Call TI Level-1-220-UNLIM

TIBPAL16R6-7CN NRND PDIP N 20 20 None Call TI Level-NC-NC-NC

TIBPAL16R8-10MFKB ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R8-10MJB ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R8-10MWB ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC

TIBPAL16R8-7CFN OBSOLETE PLCC FN 20 None Call TI Call TI

TIBPAL16R8-7CN OBSOLETE PDIP N 20 None Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

(3)

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

4-Mar-2005

Addendum-Page 2

IMPORTANT NOTICE

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