Texas Instruments TCM4300 User Manual



      
)

Data Manual

1996 Mixed-Signal Products

Printed in U.S.A.
10/96

SLWS010F

TCM4300

Data Manual

Advanced RF Cellular Telephone Interface Circuit

(ARCTIC

SLWS010F

October 1996



)

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify , before placing orders, that the information being relied
on is current.

TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI’s standard warranty . T esting and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.

Certain applications using semiconductor products may involve potential risks of death,
personal injury , or severe property or environmental damage (“Critical Applications”).

TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer .
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.

In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.

TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Copyright  1996, Texas Instruments Incorporated

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TCM4300 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Pin Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Electrical Specifications 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 2–1. . . .

2.2 Dissipation Rating Table 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Recommended Operating Conditions 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Electrical Characteristics Over Full Range Of Operating Conditions 2–2. . . . . . . . . . .

2.4.1 Power Consumption 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 Reference Characteristics 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.3 Terminal Impedance 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.4 RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) 2–3. . . . . . .

2.4.5 Transmit I and Q Channel Outputs 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.6 Auxiliary D/A Converters 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.7 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT) 2–5. . . . . . . . . . . .

2.4.8 Auxiliary D/A Converters Slope (LCDCONTR) 2–5. . . . . . . . . . . . . . . . . . . . . .

2.4.9 RSSI/Battery A/D Converter 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Operating Characteristics Over Full Range of Operating Conditions 2–6. . . . . . . . . .

2.5.1 Receive (RX) Channel Frequency Response

(RXI, RXQ Input in Digital Mode) 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Receive (RX) Channel Frequency Response

(FM Input in Analog Mode) 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 Transmit (TX) Channel Frequency Response (Digital Mode) 2–6. . . . . . . . . .

2.5.4 Transmit (TX) Channel Frequency Response (Analog Mode) 2–7. . . . . . . . .

3 Parameter Measurement Information 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 MCLKOUT Timing Requirements 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 TCM4300 to Microcontroller Interface Timing Requirements

(Mitsubishi Read Cycle) 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 TCM4300 to Microcontroller Interface Timing Requirements

(Mitsubishi Write Cycle) 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 TCM4300 to Microcontroller Interface Timing Requirements

(Intel Read Cycle) 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 TCM4300 to Microcontroller Interface Timing Requirements

(Intel Write Cycle)) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 16-Bit Read Cycle) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 16-Bit Write Cycle) 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 8-Bit Read Cycle) 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

3.9 TCM4300 to Microcontroller Interface Timing Requirements

(Motorola 8-Bit Write Cycle) 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) 3–10. . . . . . . . .

3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) 3–11. . . . . . . . .

4 Principles of Operation 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Data Transfer 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Receive Section 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Transmit Section 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Transmit Burst Operation (Digital Mode) 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Transmit I And Q Output Level 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Wide-Band Data Demodulator 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Wide-band Data Interrupts 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Wide-band Data Demodulator General Information 4–9. . . . . . . . . . . . . . . . . . . . . . . .

4.9 Auxiliary DACs, LCD Contrast Converter 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 RSSI, Battery Monitor 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 Timing And Clock Generation 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11.1 Clock Generation 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11.2 Speech-Codec Clock Generation 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11.3 Microcontroller Clock 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11.4 Sample Interrupt SINT 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11.5 Phase-Adjustment Strategy 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 Frequency Synthesizer Interface 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Power Control Port 4–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Microcontroller-DSP Communications 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 Microcontroller Register Map 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 Wide-Band Data/Control Register 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Microcontroller Status and Control Registers 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18 LCD Contrast 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 DSP Register Map 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.20 Wide-Band Data Registers 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.21 Base Station Offset Register 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 DSP Status and Control Registers 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 Reset 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23.1 Power-On Reset 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23.2 Internal Reset State 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.24 Microcontroller Interface 4–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.24.1 Intel Microcontroller Mode Of Operation 4–29. . . . . . . . . . . . . . . . . . . . . . . . . .

4.24.2 Mitsubishi Microcontroller Mode of Operation 4–30. . . . . . . . . . . . . . . . . . . . .

4.24.3 Motorola Microcontroller Mode of Operation 4–30. . . . . . . . . . . . . . . . . . . . . .

5 Mechanical Data 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

List of Illustrations

Figure Title Page

3–1 MCLKOUT Timing Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Microcontroller Interface Timing Requirements

(Mitsubishi Configuration Read Cycle, MTS [1:0] = 10) 3–2. . . . . . . . . . . . . . . . . . . . . .

3–3 Microcontroller Interface Timing Requirements

(Mitsubishi Configuration Write Cycle, MTS [1:0] = 10) 3–3. . . . . . . . . . . . . . . . . . . . . .

3–4 Microcontroller Interface Timing Requirements

(Intel Configuration Read Cycle, MTS [1:0] = 00) 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Microcontroller Interface Timing Requirements

(Intel Configuration Write Cycle, MTS [1:0] = 00) 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Microcontroller Interface Timing Requirements

(Motorola 16-Bit Read Cycle, MTS [1:0] = 10) 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Microcontroller Interface Timing Requirements

(Motorola 16-Bit Write Cycle, MTS [1:0] = 10) 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 Microcontroller Interface Timing Requirements

(Motorola 8-Bit Read Cycle, MTS [1:0] = 01) 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Microcontroller Interface Timing Requirements

(Motorola 8-Bit Write Cycle, MTS [1:0] = 01) 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 TCM4300 to DSP Interface (Read Cycle) 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 TCM4300 to DSP Interface (W rite Cycle) 3–1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Power Ramp-Up/Ramp-Down TIming Diagram 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Transmit Power Ramp-Up/Ramp-Down Functional Diagram 4–7. . . . . . . . . . . . . . . . .

4–3 WBD Manchester-Coded Data Stream 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Codec Master and Sample Clock Timing 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Timing and Clock Generation for 38.88-MHz Clock 4–14. . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Synthesizer Interface Circuit Block Diagram 4–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Contents of SynData Registers 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Example Synthesizer Output 4–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 Internal and External Power Control Logic 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Microcontroller-DSP Data Buffers 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 DSP Interface 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–12 Power-On Reset Timing 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Tables

Table Title Page

4–1 TCM4300 Receive Channel Control Signals 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 RXIP, RXIN, RXQP, and RXQN Inputs (AV

4–3 Receive (RX) Channel Frequency Response (FM Input in Analog Mode) 4–3. . . . . .

4–4 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) 4–3.

4–5 Transmit (TX) I and Q Channel Outputs 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Transmit (TX) Channel Frequency Response (Digital Mode) 4–5. . . . . . . . . . . . . . . . .

4–7 Transmit (TX) Channel Frequency Response (Analog Mode) 4–5. . . . . . . . . . . . . . . .

4–8 Typical Bit-Error-Rate Performance (WBD_BW = 000) 4–8. . . . . . . . . . . . . . . . . . . . . .

4–9 Bits in Control Register WBDCtrl 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Auxiliary D/A Converters 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT) 4–10. . . . . . . . . . . . . . . . . . .

4–12 Auxiliary D/A Converters Slope (LCDCONTR) 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–13 RSSI/Battery A/D Converter 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–14 Synthesizer Control Fields 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–15 External Power Control Signals 4–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–16 Microcontroller Register Map 4–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–17 Microcontroller Register Definitions 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–18 WBDCtrl Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–19 MStatCtrl Register Bits 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–20 DSP Register Map 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–21 DSP Register Definitions 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–22 DStatCtrl Register Bits 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–23 Power-On Reset Register Initialization 4–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–24 Microcontroller Interface Configuration 4–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–25 Microcontroller Interface Connections for Intel Mode 4–29. . . . . . . . . . . . . . . . . . . . . . . .

4–26 Microcontroller Interface Connections for Mitsubishi Mode 4–30. . . . . . . . . . . . . . . . . . .

4–27 Microcontroller Interface Connections for Motorola Mode (8 bits) 4–30. . . . . . . . . . . . .

4–28 Microcontroller Interface Connections for Motorola Mode (16 bits) 4–31. . . . . . . . . . . .

= 3 V, 4.5 V, 5 V) 4–2. . . . . . . . . . . . . .

DD

vi

1 Introduction

Texas Instruments (TI) TCM4300 IS-54B advanced RF cellular telephone interface circuit (ARCTIC)
provides a baseband interface between the digital signal processor (DSP), the microcontroller, and the RF
modulator/demodulator in a dual-mode IS-54B cellular telephone. See the TCM4300 functional block
diagram.

In the analog mode, the TCM4300 provides all required baseband filtering as well as transmit D/A
conversion and receive A/D conversion using dual 10-bit sigma-delta converters. In addition, a WBD
wide-band data (WBD) –10 kb/s Manchester frequency shift key (FSK) demodulator is provided to allow
reduced DSP processing load during subscriber standby mode.

In the digital mode, the TCM4300 accepts I and Q baseband data and performs A/D and D/A conversion
and square-root raised-cosine filtering using dual 10-bit sigma-delta converters. The TCM4300 also has a
π/4-DQPSK modulation encoder for dibit-to-symbol conversion in the digital transmit mode.

The microcontroller interface is compatible with a wide range of microcontrollers. A microcontroller can be
used to communicate with the user interface (keyboard, display , etc.) and to program up to three frequency
synthesizers by using the on-chip synthesizer interface circuit.

The TCM4300 provides advanced power control to minimize the power consumption of many dual-mode
telephone functional blocks such as the speech codec, FM receiver, I and Q demodulator , transmitter signal
processor, and RF power amplifier. In addition, the TCM4300 is designed to reduce system power
consumption through low-voltage operation and standby mode.

The TCM4300 is offered in the 100-pin PZ package and is characterized for free-air operation from
–40°C to 85°C.

1.1 Features

• Compliance With TIA IS-54B Dual-Mode Cellular Standard

• Baseband Transmit Digital-to-Analog (D/A) Conversion and Receive Analog-to-Digital (A/D)

Conversion in Analog Transmit Mode Using Dual 10-Bit Sigma-Delta Converters

• Square Root Raised Cosine (SQRC) Filtering in the Digital Mode Using Dual 10-Bit Sigma-Delta
Converters

• π/4-Differential Quadrature Phase-Shift Key (DQPSK) Modulation Encoder in Digital Transmit
Mode

• Power Control Supervision for Radio Frequency (RF) Power Amplifier, Automatic Frequency
Control (AFC), Automatic Gain Control (AGC), and Synthesizer

• Received Signal Strength Indicator (RSSI) and Battery-Level A/D Conversion Circuitry

• Internal Clock Generation

• Wide-Band Data Clock Recovery and Manchester Decoding

• General-Purpose Digital Signal Processor (DSP) and Microcontroller Interface

• 3.3-V and 5-V Operation

• Low Power Consumption

TI and ARCTIC are trademarks of Texas Instruments Incorporated.

1–1

1.2 TCM4300 Functional Block Diagram

TXIP

TXIN

TXQP
TXQN

RXIP
RXIN

RXQN

RXQP

FM

AGC

AFC

PWRCONT

PAEN

OUT1

FMRXEN

IQRXEN

TXEN
SCEN

SYNOL

TXONIND

SYNCLK

SYNDTA

SYNLE

[2:0]

RSSI

BAT

LCDCONTR

Low­Pass
Filter

Low­Pass
Filter

0Fh
10h

Anti-

aliasing

Filter

Anti-

aliasing

Filter

Low­Pass
Filter

D/A

D/A

D/A

Power

Control

Synthesizer

Interface

3

03h – 09h

TX

Offset

8

8

8

D/A

D/A

A/D

A/D

Wide-band

Demodulator

D/As

09h(D)

0Ah(D)

Control

Registers

0Bh(D)

A/D

D/A

AUX

Data

DStatCtrl

Register

MStatCtrl

Register

Digital Filter

Analog

Mode (LPF)

Digital

Mode (SQRC)

Digital Filter

Analog

Mode (LPF)

Digital

Mode (SQRC)

Internal

Clocks

7

8

0Ch

0Eh

Microcontroller

to DSP FIFO

4

6

RXI 02h

RXQ 03h

WBD

Register

WBD

Control

Clock

Generation

and

Timing

Adjustment

Logic

10

8

8

RSSI

0Bh
BAT

0Ch

LCD

0Dh

I

Q

Sample

Register

00h

01h
00h

06h
01h

A
D

A

D

ModeSel

8

8

4

8

10

8
8

5

5

8

π/4 Shifted

DQPSK

Modulation

10

38.88MHz

10

8

TXI (04b)

TX Data

Registers

TXQ (05b)

DSP

Interface

Control

Data

Address

Internal
RESET

Clock

Oscillator

TX

Common Mode Input

Bias

Control

Vref

8

06h

8

01h

Micro-

controller

Interface
Control

Data

Address

Power On

RESET

Ref

Gen

DSP to

Microcontroller

FIFO

6
8
5

10

3

CONTROL

10

DATA

4

ADDRESS

RSINL

RSOUTH
RSOUTL

SINT
MCCLK
CSCLK
CMCLK

XTAL
MCLKIN
MCLKOUT

VCM

RBIAS

VHR

REFCAP
MWBDFINT

DWBDINT
CINT

DINT

CONTROL
DATA

ADDRESS

1–2

1.3 Pin Assignments

PZ PACKAGE

(TOP VIEW)

BAT

RSSI

AV

REF

DD

FM

RXQN
RXQP

AVDDRX

RXIN
RXIP

AGC

AFC

RX

AV

SS

V

SS

VHR

VCM

PWRCONT

TXIP
TXIN

AV

TX

DD

TXQP
TXQN

AV

TX

SS

TXEN

TXONIND

PAEN

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

SS

AV REF

REFCAP

RBIAS

98

99

100

28

27

26

SS

IQRXEN

V

96

97

30

29

FMRXEN

SCEN

CSCLK

CMCLK

93

94

95

33

32

31

92

34

SS

DVDDDV

90

91

36

35

DSPD9

DSPD8

88

89

38

37

DSPD6

DSPD7

85

86

87

41

40

39

DSPD5

DSPD4

DSPD3

83

84

43

42

DSPD2

DSPD1

DSPD0

80

81

82

46

45

44

SINT

DWBDINT

CINT

77

78

79

49

48

47

SS

DV

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

DV

DD

DSPA0
DSPA1
DSPA2
DSPA3
DSPCSL
DSPRW
DSPSTRBL
MCLKOUT
XTAL

DV

SS

MCLKIN
DV

DD

MCCLK
RSOUTL
RSOUTH
RSINL
MCD7
MCD6
MCD5
MCD4
MCD3
MCD2
MCD1
MCD0

OUT1

SYNOL

SYNLE0

SYNLE1

SYNLE2

SYNDTA

SYNCLK

SS

DD

MTS1

MTS0

DV

DV

LCDCONTR

MCA0

MCCSL

MCCSH

MCA1

MCA2

MCA3

MCA4

DD

DV

SS

DV

MCRW

MCDS

DINT

MWBDFINT

1–3

1.4 Terminal Functions

I/O

DESCRIPTION

pgp

pgp

TERMINAL

NAME NO.

AFC 11 O Automatic frequency control. The AFC DAC output provides the means to adjust

AGC 10 O Automatic gain control. The AGC digital-to-analog converter (DAC) output can be

AVDDREF 3 — Analog supply voltage for FM receive path. Power applied to A VDDREF powers the

AVDDRX 7 — Analog supply voltage for receive path. Power applied to AVDDRX powers the receive

AVDDTX 19 — Analog supply voltage for transmit path. Power applied to AVDDTX powers the

AVSSREF 98 — Analog ground for REFCAP
AVSSRX 12 — Analog ground for receive path
AVSSTX 22 — Analog ground for transmit path
BAT 1 I Battery strength monitor. A sample of the battery voltage is applied to BA T, and this

CINT 77 O Controller data interrupt. CINT is the microcontroller data interrupt (active low) signal

CMCLK 92 O Codec master clock. CMCLK provides a 2.048-MHz clock that is used as the master

CSCLK 93 O Codec sample clock. CSCLK provides an 8-kHz frame synchronization pulse for the

DINT 49 O Microcontroller interrupt request. DINT is output when the DSP writes to the SEND

DSPA0 74
DSPA1 73
DSPA2 72
DSPA3 71
DSPCSL 70 I DSP chip select (active low). A low signal at DSPCSL enables the specific DSP

DSPD0 80
DSPD1 81
DSPD2 82
DSPD3 83
DSPD4 84
DSPD5 85
DSPD6 86
DSPD7 87
DSPD8 88
DSPD9 89

†

Z = high impedance

system temperature-compensated reference oscillator (TCXO).

used to control the gain of system receiver circuits.

FM receive path circuitry.

path circuitry.

transmit path circuitry .

sample monitors the battery strength.

that is sent to the DSP. CINT is caused by a microcontroller write to the Send-C
interrupt register location.

clock and bit clock for the speech codec.

speech codec. CSCLK is also connected to the DSP for speech sample interrupts.

DINT register location. DINT can be active high or low according to the levels of the
MTS0 and MTS1 signals.

I DSP 4-bit parallel address bus. DSP A0 through DSP A3 provides the address bus for

the DSP interface. DSPA3 is the MSB, and DSPA0 is the LSB.

addressed.

I/O/Z DSP 10-bit parallel data bus. DSPD0 through DSPD9 provide a 10-bit data bus for the

DSP. DSPD9 is the MSB, and DSPD0 is the LSB.

1–4

1.4 Terminal Functions (Continued)

I/O

DESCRIPTION

pgp

pgp

MSB

MCD0 is the LSB

TERMINAL

NAME NO.

DSPRW 69 I DSP read/write. A high on DSPRW enables a read operation and a low enables

DSPSTRBL 68 I DSP strobe low . The DSPSTRL (active low) is used in conjunction with DSPCSL

DV

DD

DV

SS

DWBDINT 78 O DSP wide-band data interrupt (active low). The DWBDINT output goes low to

FM 4 I Frequency modulation. FM terminal is connected to the output of the FM

FMRXEN 95 O FM receive path enable. A high output from FMRXEN can be used to enable the

IQRXEN 96 O In-phase and quadrature receive path enable. A high output on IQRXEN can be

LCDCONTR 33 O Liquid-crystal display (LCD) contrast. This LCDCONTR control DAC can be

MCLKOUT 67 O Master clock out. MCLKOUT is a buffered version of MCLKIN.
MCA0 40
MCA1 41
MCA2 42
MCA3 43
MCA4 44
MCCLK 62 O Microcontroller clock. MCCLK provides an adjustable frequency with 1.215 MHz

MCCSH 39 I Microcontroller interface chip-select. A high at MCCSH in conjunction with a low

MCCSL 38 I Microcontroller interface chip-select. A low at MCCSL in conjunction with a high

MCD0 51
MCD1 52
MCD2 53
MCD3 54
MCD4 55
MCD5 56
MCD6 57
MCD7 58

†

Z = high impedance

35, 45, 63,

75, 90

34, 46, 65,

76, 91

a write operation to the DSP.

to enable read/write operations to the DSP.

— Digital power supply. All supply terminals must be connected together.

— Digital ground. All supply terminals must be connected together.

indicate that the wide-band data (WBD) demodulation circuits have traffic on
them.

discriminator.

power for the receiver FM path.

used to enable the power for receiver I/Q path.

used to control the amount of drive to the liquid crystal display.

I Microcontroller 5-bit parallel address bus. MCA0 through MCA4 provide a 5-bit

bus to address the microcontroller. MCA4 is the MSB, and MCA0 is the LSB.

at powerup.

at MCCSL allows the microcontroller to read from or write to the TCM4300.

at the MCCSH allows the microcontroller to read from or write to the TCM4300.

I/O/Z Microcontroller 8-bit parallel data bus. MCD0 through MCD7 provides an 8-bit

parallel data bus to send/receive data to/from the microcontroller. MCD7 is the

, and

.

1–5

1.4 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

MCDS 48 I Microcontroller data strobe. MCDS is configured by the signals present on MTS0 and

MCLKIN 64 I Master clock input. The MCLKIN frequency input requirement is 38.88 MHz ±100 ppm.

MCRW 47 I Microcontroller read/write. Microcontroller read/write operations are selected in

MTS0 36 I

MTS1 37 I

MWBDFINT 50 O Microcontroller interrupt request. A wide-band data-ready interrupt is output when the

OUT1 26 O Output number 1. OUT1 provides a user-defined general purpose data or control signal.
PAEN 25 O Power amplifier enable. P AEN can be used to enable the transmit power amplifier . This

PWRCONT 16 O Power amplifier (PA) power control. The PWRCONT DAC output can be used to control

RBIAS 99 I Input for bias current-setting resistor. To achieve correct bias voltage, a 100-kΩ, 1%

REFCAP 100 I Reference decoupling capacitor. For proper decoupling, It is recommended that a

RSINL 59 I Reset input low. An active low applied to RSINL resets the TCM4300.
RSSI 2 I Received signal strength indicator. RSSI samples received signal strength.
RSOUTH 60 O Reset out high. An active high is output from RSOUTH for 10 ms after the TCM4300 is

RSOUTL 61 O Reset out low. An active low is output from RSOUTL for 10 ms after the TCM4300 is

RXIN 8 I Negative receive input. The in-phase differential negative baseband received signal is

RXIP 9 I Positive receive input. The in-phase differential positive baseband received signal is

RXQN 5 I Negative receive input. The quadrature negative baseband received signal is applied

RXQP 6 I Positive receive input. The quadrature differential positive baseband received signal is

MTS1.

A crystal can be connected between MCLKIN and XTAL to provide an oscillator circuit.
As an alternative, XTAL can be left open and an external TTL/CMOS-level clock signal
can be connected to MCLKIN.

accordance with the signals present on MTS0 and MTS1.
Microcontroller type select configuration-control inputs. The interface is controlled by

MTS (1:0) as follows:
00 – Intel microcontroller interface characteristics
10 – Mitsubishi and Motorola microcontroller 16-bit bus interface characteristics
01 – Motorola microcontroller 8-bit bus characteristics
11 – Reserved

WBD demodulator is in analog mode or when a frame interrupt is sent by the DSP in
digital mode. MWDBFINT can be active high or low according to the levels of the MTS0
and MTS1 signals.

signal is active high.

the amount of power output from the PA.

tolerance resistor connected between RBIAS and A VSS is recommended.

3.3 µF capacitor in parallel with a 470-pF capacitor be connected between REFCAP and
ground.

powered up.

powered up.

applied to RXIN.

applied to RXIP.

to RXQN.

applied to RXQP.

Intel is a trademark of Intel Corporation.
Mitsubishi is a trademark of Mitsubishi Inc.
Motorola is a trademark of Motorola, Inc.

1–6

1.4 Terminal Functions (Continued)

I/O

DESCRIPTION

yg

TERMINAL

NAME NO.

SCEN 94 O Speech CODEC enable. A high out from SCEN can enable the speech CODEC.
SINT 79 O Sample interrupt. SINT is active low. In the analog mode, SINT occurs at 40 kHz; in the

SYNCLK 32 O Synthesizer clock. SYNCLK clocks the serial data stream.
SYNDTA 31 O Synthesizer serial-data. SYNDTA provides the serial bit stream output.
SYNLE0 28 O
SYNLE1 29 O
SYNLE2 30 O
SYNOL 27 I Synthesizer out-of-lock. An active high at SYNOL indicates a synthesizer is not locked.
TXEN 23 O Transmit power enable. An active high output from TXEN can be used to enable various

TXIN 18 O In-phase differential negative baseband transmit. The negative component of the

TXIP 17 O In-phase differential positive baseband transmit. The positive component of the

TXONIND 24 I Transmit on indicator. A signal is applied to TXONIND to indicate that power is applied

TXQN 21 O Quadrature differential negative baseband transmit. The negative component of the

TXQP 20 O Quadrature differential positive baseband transmit. The positive component of the

VCM 15 I Voltage common mode. VCM establishes the dc operating point for transmit outputs and

VHR 14 O Voltage half-rail. The voltage level at VHR is approximately 0.5 × AVDD. VHR

V

SS

XTAL 66 I Crystal input. A crystal connected between XTAL and MCLIN forms an oscillator circuit.

13, 97 — Substrate ground

digital mode, SINT occurs at 48.6 kHz.

Synthesizer 0, 1, and 2 latch enables. An active high on SYNLE0, SYNLE1, and
SYNLE2 indicates that the latch is enabled.

system transmitter-circuit devices.

differential baseband transmit signal is output from TXIN.

differential baseband transmit signal is output from TXIP.

to the power amplifier.

quadrature differential transmit signal is output from TXQN.

quadrature differential transmit signal is output from TXQP.

can be tied to VHR.

establishes the dc operating point for receive inputs.

1–7

2 Electrical Specifications

This section lists the electrical specifications, the absolute maximum ratings, the recommended operating
conditions and operating characteristics for the TCM4300 Advanced RF Cellular Telephone Interface
Circuit.

2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(unless otherwise noted)

Supply voltage range:

DV

(see Notes 1 and 2) VSS –0.3 V to AVDD +0.3 V. . . . . . . . . . . . . . . . . . . . . .

DD

AV

(see Notes 2 and 3) VSS –0.3 V to DVDD +0.3 V. . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V
Output voltage range, V

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect DVSS.

DD

2. Maximum supplied voltage should not exceed 6 V .

3. Voltage values are with respect to AVSS.

: Digital signals VSS –0.3 V to DVDD +0.3 V. . . . . . . . . . . . . . . . .

I

†

Analog signals V

: Digital signals VSS to DV

O

Analog signals V

–65°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

. . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . .

A

SS

–0.3 V to AVDD +0.3 V. . . . . . . . . . . . . . . .

to AV

SS

DD
DD

2.2 Dissipation Rating Table

PACKAGE

PZ 1530 mW 15.25 mW/°C 615 mW

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 85°C

POWER RATING

2–1

2.3 Recommended Operating Conditions

Anal

itti

W

Digital

W

Digital t

itti

W

Idle mode

mW

g, g g

W

Output

MIN NOM MAX UNIT

Supply voltage, DV
High-level input voltage, V
Low-level input voltage, V
High-level output voltage, V
Low-level output voltage, V
High-level output current at 3 V , I
Low-level output current at 3 V , I
High-level output current at 5 V , I
Low-level output current at 5 V , I
Load capacitance, transmit I and Q channel outputs 50 pF
VCM input voltage range, transmit I and Q channel outputs 1.3 AVDD–1.3 V

Load resistance, auxiliary DACs 10 kΩ
Load capacitance, auxiliary DACs 50 pF
Operating free-air temperature, T

DD

IH

IL

OH

OL

OH

OL

OH

OL

A

Digital 0.7 DV
Digital 0 0.3 DV
Digital 0.7 DV
Digital 0 0.5 V
Digital 2 mA
Digital 2 mA
Digital 2 mA
Digital 2 mA

3 5.5 V

DD

DD

–40 85 °C

DVDD+0.3 V

DD

DV

DD

V
V

2.4 Electrical Characteristics Over Full Range Of Operating Conditions (Unless
Otherwise Noted)

2.4.1 Power Consumption

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

og transm

receiving

ransm

Digital mode, 1/3 transmitting +1/3 receiving
+ 1/3 standby

†

All typical values are at TA = 25°C.

ng and receiving

ng

MCLKOUT enabled DVDD = 3 V, AVDD = 3 V 33 40
MCLKOUT disabled DVDD = 3 V, AVDD = 3 V 14 17

MCLKOUT enabled DVDD = 5.5 V, AVDD = 5.5 V 150 160
MCLKOUT disabled DVDD = 5.5 V, AVDD = 5.5 V 80 90

DVDD = 3 V, AVDD = 3 V 65 75
DVDD = 5.5 V, AVDD = 5.5 V 250 275
DVDD = 3 V, AVDD = 3 V 55 60
DVDD = 5.5 V, AVDD = 5.5 V 225 250
DVDD = 3 V, AVDD = 3 V 55 70
DVDD = 5.5 V, AVDD = 5.5 V 210 250

DVDD = 3 V, AVDD = 3 V 50 60
DVDD = 5.5 V, AVDD = 5.5 V 205 220

m

m

m

m

2.4.2 Reference Characteristics

PARAMETER TEST CONDITIONS MIN TYP

V

OH(VHR)

r

O

‡

All typical values are at DVDD = 5 V, AVDD = 5 V, and TA = 25°C

2–2

High-level output voltage 0.5 A VDD–0.2 0.5 AVDD+0.2 V

resistance

FMVOX or IQRXEN
or TXEN = high

FMVOX or IQRXEN
or TXEN = low

‡

MAX UNIT

80 100 Ω

15 40 kΩ

2.4.3 T erminal Impedance

MCLKOUT i

Ω

Input voltage for full

V

Nominal operating

‡

FUNCTION MIN TYP†MAX UNIT

Receive channel input impedance (single ended), RXIP/N and RXQP/N 40 70 kΩ
Transmit channel output impedance (single ended), TXIP/N and TXQP/N 40 50 100 Ω
FM input impedance, WBD 25 200 kΩ

mpedance

†

All typical values are at DVDD = 5 V, AVDD = 5 V, and TA = 25°C, unless otherwise specified.

MCLKOUT at 3.3 V 240
MCLKOUT at 5 V 180

2.4.4 RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage range 0.3 AVDD–0.3 V
Input voltage for full-

scale digital output
Nominal operating

level
Input CMRR (RXI, RXQ) 45 dB

Sampling frequency , SINT (digital
mode)

Sampling frequency , SINT (analog
mode)

Receive error vector magnitude (EVM) 5% 6%
I/Q sample timing skew Input signal 0 – 15 kHz 50 ns
A/D resolution 10 bits
Signal to noise-plus distortion Input at full scale – 1 dB 54 58 dB
Integral nonlinearity 0 dB to –60 dB input 1 LSB
Gain error (I or Q channel) ±7%
Gain mismatch between I and Q ±0.3 dB
Differential dc offset voltage ±30 mV
FM input sensitivity, full scale

( 14 kHz deviation)
FM input dc offset (relative to VHR) ±80 mV
FM input idle channel noise, below

full-scale input
FM gain error ±6%
Power supply rejection f = 0 kHz to 15 kHz 40 dB

‡

Provides 12 dB headroom for AGC fading conditions.

Differential 0.5
Single ended
Differential 0.125
Single ended 0.125

0.5

48.6 kHz

40 kHz

2.5 Vp-p

–50 dB

p-p

Vp-p

2–3

2.4.5 Transmit I and Q Channel Outputs

Peak

VCM

V

Nominal output level (constellation radius) centered

V

pg

PARAMETER MIN TYP MAX UNIT

output voltage full scale, centered at

Nominal output-level (constellation radius) centered
at VCM

Low-level drift ±200 PPM/°C
Transmit error vector magnitude (EVM) 3% 4%
Resolution 8 bits
S/(N+D) ratio at differential outputs 48 52 dB
Gain error (I or Q channel) ±8% ±12%
Gain mismatch between I and Q ±0.3 dB
Gain sampling mismatch between I and Q 20 ns
Zero code error differential ±80 mV
Zero code error, each output, with respect to VCM ±80 mV
Zero code error, I to Q, with respect to other channel (differential or

single ended)
Load impedance, between P and N terminals 10 kΩ
Transmit offset DACs I and Q resolution 6 bits
Transmit offset DACs I and Q average step size 2.9 3.4 3.9 mV
Transmit offset DACs I and Q full-scale positive output 105.4 mV
Transmit offset DACs I and Q full-scale negative output –108.8 mV
Transmit offset DACs differential nonlinearity ±1.1 LSB
Transmit offset DACs integral nonlinearity ±1.1 LSB

Differential 2.24
Single ended 1.12
Differential 1.5
Single ended 0.75

±10 mV

p

2.4.6 Auxiliary D/A Converters

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AVDD > 3 V†, AUXFS [1:0] = 00 0.2 2.5

Output range

Resolution AGC, AFC, PWRCONT
DACs

Resolution LCDCONTR DAC 4 bits
Gain + offset error (full scale) AGC,

AFC, PWRCONT DAC
Gain + offset error (full scale)

LCDCONTR DAC
Differential nonlinearity ±0.75 ±1 LSB
Integral nonlinearity ±0.75 ±1 LSB

†

Range settings depends only on AUXFS [1:0]. The supply voltage is not detected.

2–4

AVDD > 4.5 V†, AUXFS [1:0] = 10 0.2 4
AVDD > 5 V†, AUXFS [1:0] = 11 0.2 4.5

8 bits

±3%

±7%

V

2.4.7 Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT)

AUXFS[1:0]

SETTING

00 2.5/256 0.0098 1.25 2.5
01 Do not use Do not use Do not use Do not use
10 4/256 0.0156 2 4
11 4.5/256 0.0176 2.25 4.5

†

The maximum input code is 255. The value shown for 256 is extrapolated.

SLOPE

NOMINAL LSB

VALUE

(V)

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 128

(MIDRANGE)

(V)

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 256†

(MAX VALUE)

(V)

2.4.8 Auxiliary D/A Converters Slope (LCDCONTR)

AUXFS[1:0]

SETTING

00 2.5/16 0.1563 1.25 2.5
01 Do not use Do not use Do not use Do not use
10 4/16 0.2500 2 4
11 4.5/16 0.2813 2.25 4.5

‡

The maximum input code is 15. The value shown for 16 is extrapolated.

SLOPE

NOMINAL LSB

VALUE

(V)

NOMINAL OUTPUT VOLT-

AGE FOR DIGITAL CODE = 8

(MIDRANGE)

(V)

NOMINAL OUTPUT VOLTAGE

FOR DIGITAL CODE = 16

(MAX VALUE)

(V)

2.4.9 RSSI/Battery A/D Converter

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input range AVDD = 3 V, 4.5 V, 5 V 0.2 2 V
Resolution 8 bits
Conversion time AVDD = 3 V, 4.5 V, 5 V 20 µs
Gain + offset error (full scale) ±3% ±4%
Differential nonlinearity ±0.75 ±1 LSB
Integral nonlinearity ±0.75 ±1 LSB
Input resistance 1 2 MΩ

§

2–5

2.5 Operating Characteristics Over Full Range of Operating Conditions

qy

dB

qyp

F

dB

(Unless Otherwise Noted)

2.5.1 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0.125 V peak-to-peak, 0 kHz to 8 kHz (see Note 4) ±0.5 ±0.75

0.125 V peak-to-peak, 8 kHz to 15 kHz (see Note 5) ±1

Frequency
response

Peak-to-peak
group delay
distortion

Absolute channel
delay, RXI, Q IN to
digital OUT

NOTES: 4. Deviation from ideal 0.35 square-root raised-cosine (SQRC) response

5. Stopband

2.5.2 Receive (RX) Channel Frequency Response (FM Input in Analog Mode)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Frequency response

Peak-to-peak group
delay distortion

Absolute channel delay 2.5 V peak-to-peak, 0 kHz to 6 kHz 400 µs

NOTES: 5. Stopband

6. Ripple magnitude

7. Stopband and multiples of stopband

2.5.3 Transmit (TX) Channel Frequency Response (Digital Mode)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

requency response

Peak-to-peak group
delay distortion

Absolute channel delay 0 kHz to 15 kHz 320 µs

NOTES: 4. Deviation from ideal 0.35 square-root raised-cosine (SQRC) response

5. Stopband

0.125 V peak-to-peak, 16.2 kHz to 18 kHz (see Note 5) –26

0.125 V peak-to-peak, 18 kHz to 45 kHz (see Note 5) –30

0.125 V peak-to-peak, 45 kHz to 75 kHz (see Note 5) –46

0.125 V peak-to-peak, > 75 kHz –60

0.125 V peak-to-peak, 0 kHz to 15 kHz 2 µs

0.125 V peak-to-peak, 0 kHz to 15 kHz 325 µs

2.5 V peak-to-peak, 0 kHz to 6 kHz (see Note 6) ±0.5

2.5 V peak-to-peak, 20 kHz to 30 kHz (see Note 5) –18

2.5 V peak-to-peak, 34 kHz to 46 kHz (see Note 7) –48

2.5 V peak-to-peak, 0 kHz to 6 kHz 2 µs

0 kHz to 8 kHz (see Note 4) ±0.3
8 kHz to 15 kHz (see Note 4) ±0.5
20 kHz to 45 kHz (see Note 5) –29

45 kHz to 75 kHz (see Note 5) –55
> 75 kHz (see Note 5) –60
Any 30 kHz band centered at > 90 kHz (see Note 5) –60

0 kHz to 15 kHz 3 µs

dB

2–6