Texas Instruments TCM38C17IDL Datasheet

TCM38C17IDL

QCombo FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

Single 5-V Supply

Replaces Four TCM29C13-Type Combos (CODEC and Filters)

Meets CCITT/(D3/D4) G.711 and G.714 Channel Bank Specifications

Advanced Switched-Capacitor Filters and Sigma-Delta A/D and D/A Converter Technology With DSP Filtering

µ-Law or A-Law Companding — Pin-Selectable

2.048 MHz Operation

8 Vpp Full-Signal Differential Receiver Output

Differential Signal Processing Architecture

Low Crosstalk (< –100 dB), Low Idle-Channel Noise, and Good Power Supply Rejection

Single PCM I/O for Simplified PCM Interface

Reliable Submicron Silicon-Gate CMOS Technology

description

The TCM38C17IDL QCombo is a 4-channel single-chip PCM combo (pulse-code-modulated

RBIAS

AREF

A VSS

0GSX

0ANLGIN–

0ANLGIN+

0PWRO+

0GSR

0PWRO–

1GSX

1ANLGIN–

1ANLGIN+

1PWRO+

1GSR

1PWRO–

0PDN 1PDN

VSS

DVSS

DVDD

DVDDPLL

MCLK

DVSSPLL

ASEL

CODEC with a voice-band filtering) device. It performs the transmit encoding (A/D conversion) and receive decoding (D/A conversion), as well as the transmit and receive filtering functions required to meet CCITT G.71 1 and G.714 specifications in a PCM system. Each channel provides all the functions required to interface a full-duplex, 4-line voice telephone circuit with a TDM (time-division-multiplexed) system. The TCM38C17IDL is specifically designed for fixed-data-rate applications and is intended to replace four TCM29C13-type devices.

DL PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

REFLTR1 REFLTR2 A VDD 2GSX 2ANLGIN– 2ANLGIN+ 2PWRO+ 2GSR 2PWRO– 3GSX 3ANLGIN– 3ANLGIN+ 3PWRO+ 3GSR 3PWRO– 3PDN 2PDN 0FS 1FS 2FS 3FS PCMOUT RESET PCMIN

Primary applications include digital transmission and switching of E1 carrier, PABX (private automatic branch exchange), and central office telephone systems and subscriber line concentrators. The device serves as the analog termination of a PCM line or trunk to the POTS (plain old telephone system) local-loop line.

Other applications include any PCM digital-audio interface such as voice-band data storage systems and many digital signal processing applications that can benefit from the reduced footprint of a quad codec configuration and single-rail operation. Dynamic range and excellent idle-channel noise performance are maintained using the TI advanced 4Vt process technologies.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI and QCombo are registered trademarks of Texas Instruments, Inc.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TCM38C17IDL QCombo FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

description (continued)

The TCM38C17IDL is available in a 48-pin plastic DL SSOP (shrink small-outline package) and is characterized for operation from –40°C to 85°C.

functional block diagram

Analog

Input ANGLIN– ANGLIN+

GSX

GSR

PWRO+

Analog

Output

PWRO–

–

Output

Amplifier

Inverting Amplifier

Antialias

Filter

SwitchedCapacitor

Smoothing

Filter

NOTE A: One of four identical channels is depicted.

Σ∆ ADC

Σ∆ DAC

Transmit Section

Digital

Filter

Clock

Buffer

Digital

Filter

Receive Section

Compressor

Expander

Output

Frame

Control

Input

Digital Output

PCMOUT

MCLK (2.048 MHz)

PCMIN Digital

Input

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I/O

DESCRIPTION

TCM38C17IDL

QCombo FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

Terminal Functions

TERMINAL

NAME NO.

AREF 2 Analog reference point (mid-supply). This voltage is generated internally at a nominal 2.375 V. An

0ANLGIN+ 6 I Noninverting analog input to uncommitted transmit operational amplifier for channel 0 0ANLGIN– 5 I Inverting analog input to uncommitted transmit operational amplifier for channel 0 1ANLGIN+ 12 I Noninverting analog input to uncommitted transmit operational amplifier for channel 1 1ANLGIN– 11 I Inverting analog input to uncommitted transmit operational amplifier for channel 1 2ANLGIN+ 43 I Noninverting analog input to uncommitted transmit operational amplifier for channel 2 2ANLGIN– 44 I Inverting analog input to uncommitted transmit operational amplifier for channel 2 3ANLGIN+ 37 I Noninverting analog input to uncommitted transmit operational amplifier for channel 3 3ANLGIN– 38 I Inverting analog input to uncommitted transmit operational amplifier for channel 3 ASEL 24 I A-law and µ-law operation select. When ASEL is connected to ground, A-law is selected. When ASEL is

AVDD 46 Analog supply voltage, 5 V , ±5% AVSS 3 Analog ground return for AVDD supply DVDD 20 Digital supply voltage, 5 V, ±5% DVDDPLL 21 Phase-locked loop supply voltage, 5 V, ±5% DVSSPLL 23 Phase-locked loop ground return for DVDDPLL supply DVSS 19 Digital ground return for DVDD supply 0FS 31 I Frame synchronization clock input/time slot enable for channel 0 TX and RX (digital) 1FS 30 I Frame synchronization clock input/time slot enable for channel 1 TX and RX (digital) 2FS 29 I Frame synchronization clock input/time slot enable for channel 2 TX and RX (digital) 3FS 28 I Frame synchronization clock input/time slot enable for channel 3 TX and RX (digital) 0GSR 8 I Receive amplifier gain-set input (channel 0). The ratio of an external voltage divider network connected to

1GSR 14 I Receive amplifier gain-set input (channel 1). The ratio of an external voltage divider network connected to

2GSR 41 I Receive amplifier gain-set input (channel 2). The ratio of an external voltage divider network connected to

3GSR 35 I Receive amplifier gain-set input (channel 3). The ratio of an external voltage divider network connected to

0GSX 4 O Output terminal of internal uncommitted transmit operational amplifier for channel 0 (analog) 1GSX 10 O Output terminal of internal uncommitted transmit operational amplifier for channel 1 (analog) 2GSX 45 O Output terminal of internal uncommitted transmit operational amplifier for channel 2 (analog) 3GSX 39 O Output terminal of internal uncommitted transmit operational amplifier for channel 3 (analog) MCLK 22 I Master clock input (2.048 MHz) (digital) PCMIN 25 I Transmit PCM input (digital) PCMOUT 27 O Transmit PCM output (digital) 0PDN 16 I Power-down select for channel 0. This channel of the device is inactive with a CMOS low-level input to

1PDN 17 I Power-down select for channel 1. This channel of the device is inactive with a CMOS low-level input to

2PDN 32 I Power-down select for channel 2. This channel of the device is inactive with a CMOS low-level input to

external decoupling capacitor (0.1 µF) should be connected from AREF to AVSS for filtering purposes.

connected to VDD, µ-law is selected (digital).

0PWRO– and 0PWRO+ determines the receive amplifier gain. Maximum gain occurs when 0GSR is connected to 0PWRO–, and minimum gain occurs when it is connected to 0PWRO+ (analog).

1PWRO– and 1PWRO+ determines the receive amplifier gain. Maximum gain occurs when 1GSR is connected to 1PWRO–, and minimum gain occurs when it is connected to 1PWRO+ (analog).

2PWRO– and 2PWRO+ determines the receive amplifier gain. Maximum gain occurs when 2GSR is connected to 2PWRO–, and minimum gain occurs when it is connected to 2PWRO+ (analog).

3PWRO– and 3PWRO+ determines the receive amplifier gain. Maximum gain occurs when 3GSR is connected to 3PWRO–, and minimum gain occurs when it is connected to 3PWRO+ (analog).

0PDN

and active with a CMOS high-level input to the terminal (digital).

1PDN

and active with a CMOS high-level input to the terminal (digital).

2PDN

and active with a CMOS high-level input to the terminal (digital).

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TCM38C17IDL

I/O

DESCRIPTION

QCombo FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

3PDN 33 I Power-down select for channel 3. This channel of the device is inactive with a CMOS low-level input to 3PDN

and active with a CMOS high-level input to the terminal (digital).

0PWRO+ 7 O Noninverting output of channel 0 power amplifier. 0PWRO+can drive a 600 Ω || 100 pF load differentially

(analog). 0PWRO – 9 O Inverting output of channel 0 power amplifier . 0PWRO– can drive a 600 Ω || 100 pF load differentially (analog). 1PWRO+ 13 O Noninverting output of channel 1 power amplifier. 1PWRO+ can drive a 600 Ω || 100 pF load differentially

(analog). 1PWRO– 15 O Inverting output of channel 1 power amplifier . 1PWRO– can drive a 600 Ω || 100 pF load differentially (analog). 2PWRO+ 42 O Noninverting output of channel 2 power amplifier. 2PWRO+ can drive a 600 Ω || 100 pF load differentially

(analog). 2PWRO– 40 O Inverting output of channel 2 power amplifier . 2PWRO– can drive a 600 Ω || 100 pF load differentially (analog). 3PWRO+ 36 O Noninverting output of channel 3 power amplifier. 3PWRO+ can drive a 600 Ω || 100 pF load differentially

(analog). 3PWRO– 34 O Inverting output of channel 3 power amplifier , 3PWRO– can drive a 600 Ω || 100 pF load differentially (analog). RBIAS 1 Bias current setting resistor. A 100 kΩ, ± 5% resistor should be connected between terminals RBIAS and AVSS

to set the bias current of the device. REFLTR1 48 Voltage reference. A 1-µF external decoupling capacitor should be connected from REFLTR1 to AVSS for

filtering purposes. REFLTR2 47 Voltage reference. A 1-µF external decoupling capacitor should be connected from REFLTR2 to AVSS for

filtering purposes. RESET 26 I Reset. Reset for all internal registers is initiated when RESET is brought high (digital). VSS 18 Substrate bias. VSS should be externally connected to AVSS.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VDD (see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

Digital ground voltage range, V

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Voltage values are with respect to AVSS.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Notes 2 and 3)

MIN NOM MAX UNIT

Supply voltage, V High-level input voltage, V Low-level input voltage, V Load resistance between PWRO+ and PWRO– (differential), R Load capacitance between PWRO+ and PWRO– (differential), C Operating free-air temperature, T

NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device

power-up sequence paragraphs later in this document should be followed.

3. Voltages at analog inputs, outputs and the AVDD terminal are with respect to the AREF terminal. All other voltages are referenced to the DVSS terminal unless otherwise noted.

4.75 5 5.25 V

0.8 × V

0.2 × V

600 Ω

–40 85 °C

100 pF

V V

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IDDSupply current from V

TCM38C17IDL

QCombo FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

supply current, total device, MCLK = 2.048 MHz, outputs not loaded, VDD = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

†

With 8 Vpp output

Operating All channels 50 Power down PDN (all channels) 11 mA

digital interface

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage PCMOUT IOH = –3.2 mA 4.6 5 V

Low-level output voltage PCMOUT IOL = 3.2 mA 0 0.4 V

High-level input current, any digital input VI = 0.8 × V

Low-level input current, any digital input VI = 0.2 × V

Input capacitance 5 pF

Output capacitance 5 pF

DD DD

transmit amplifier input

PARAMETER MIN TYP MAX UNIT

Input current at ANLGIN+ and ANLGIN– ±100 nA Input offset voltage at ANLGIN+ and ANLGIN– ±5 mV Common-mode rejection at ANLGIN+ and ANLGIN– 55 dB Open-loop voltage amplification at ANLGIN+ and ANLGIN– 60 dB Open-loop unity-gain bandwidth at ANLGIN+ and ANLGIN– 900 kHz Input resistance at ANLGIN+ and ANLGIN– 10 MΩ

†

10 µA 10 µA

receive filter output

PARAMETER TEST CONDITION MIN TYP‡MAX UNIT

Output offset voltage at PWRO+/PWRO – Relative to AREF ±80 mV Output resistance at PWRO+/PWRO – DC output 1 Ω

‡

All typical values are at VDD = 5 V, and TA = 25_C.

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TCM38C17IDL

(),

Vrms

(),

600 Ω at maximum gain

Vrms

QCombo FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

transmit and receive gain and dynamic range, V

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Encoder milliwatt response (transmit gain tolerance) Signal input = 0 dBm0 ±0.1 ±0.18 dBm0 Encoder milliwatt response variation with temperature and

power supplies Digital milliwatt response (receive tolerance gain) relative to

zero-transmission-level point Digital milliwatt response variation with temperature and power

supplies Zero-transmission–level point (0 dBm0), transmit

channel Transmit overload signal level, peak-to-peak centered at AREF 3 Vpp Zero-transmission–level point (0 dBm0), receive

channel Receive overload signal level, fully differential

NOTES: 4. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point of

the channel under test.

5. The input amplifier is set for noninverting unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave through an ideal encoder.

6. Receive output is measured single ended in the maximum-gain (unity) configuration. To set the output amplifier for maximum gain, GSR is connected to PWRO– and the output is taken at PWRO+. All output levels are (sin x)/x corrected.

µ-law 0.747 A-law

µ-law A-law

= 5 V, TA = 25°C (see Notes 4, 5, and 6)

TA = –40°C to 85°C, Supplies = ±5% ±0.08 dB

Signal input per CCITT G.711 ±0.1 ±0.18 dBm0 TA = –40°C to 85°C,

Supplies = ±5%

Input buffer configured for unity gain

= (Load is connected between PWRO+ and PWRO–)

7.8 8 Vpp

±0.08 dB

0.75

1.99 2

transmit and receive gain tracking over recommended ranges of supply voltage and operating free-air temperature, reference level = –10 dBm0

PARAMETER TEST CONDITION MIN TYP MAX UNIT

3 > input level ≥ – 40 dBm0 ±0.25

Transmit gain tracking error , sinusoidal input

Receive gain tracking error, sinusoidal input

–40 > input level > –50 dBm0 ±0.5

–50 ≥ input level ≥ – 55 dBm0 ±1.2

3 > input level ≥ – 40 dBm0 ±0.25

–40 > input level > –50dBm0 ±0.5 –50 ≥ input level ≥ – 55 dBm0 ±1.2

noise over recommended ranges of supply voltage and operating free-air temperature

Transmit noise, C-message weighted (µ-law), PCMOUT ANLGIN+ = 0 V 10 12 dBrnC0 Transmit noise, psophometrically weighted (A-law), PCMOUT ANLGIN+ = 0 V –80 –75 dBm0p Receive noise, C-message-weighted quiet code at PWRO+ (µ-law) PCMIN = 11111111 5 12 dBrnC0 Receive noise, psophometrically weighted at PWRO+ (A-law) PCMIN = 11010101 –85 –79 dBm0p

PARAMETER TEST CONDITION MIN TYP MAX UNIT

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suppl

oltage rejection, transmit channel

Supply signal

200 mVpp

ygj ,

Su ly signal 200 mV ,

Crosstalk (between channels) attenuation

0 dBm0

300 H

3400 H

Method 2)

dBm0

TCM38C17IDL

QCombo FOUR-CHANNEL (QUAD) PCM COMBO

SLWS040C – JUNE 1996 – REVISED OCTOBER 1999

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and operating free-air temperature

PARAMETER TEST CONDITION MIN TYP†MAX UNIT

y v

supply voltage rejection, receive channel

(single-ended)

Crosstalk (same channel) attenuation, transmit-to-receive (single-ended)

Crosstalk (same channel) attenuation, receive-to-transmit (single-ended)

†

All typical values are at VDD = 5 V, and TA = 25°C

‡

Actual levels were beneath the test equipment measurement floor.

0 < f < 30 kHz 30 < f < 50 kHz

0 < f < 30 kHz

30 < f< 50 kHz

Transmit to transmit ≤100 Transmit to receive Receive to transmit Receive to receive ≤100

Idle channel,

f measured at PCMOUT Idle channel,

Suppl narrow-band, f measured at PWRO+

ANLGIN+ = 0 dBm0, f = 1.02 kHz, unity gain, PCMIN = lowest decode level, measured at PWRO+

PCMIN = 0 dBm0, f = 1.02 kHz, measured at PCMOUT

signal = 200 mVpp,

z –

–40 –45

–40

–45

‡

≤100

≤100 ≤100

‡

‡ ‡ ‡ ‡

–75 dB

–76 –78 –76 –78

distortion over recommended ranges of supply voltage and operating free-air temperature

PARAMETER TEST CONDITIONS MIN MAX UNIT

Transmit signal to distortion ratio, sinusoidal input (CCITT G.712 -

Receive signal to distortion ratio, sinusoidal input (CCITT G.712 -

Transmit single-frequency distortion products Input signal = 0 dBm0 –46 dBm0 Receive single-frequency distortion products Input signal = 0 dBm0 –46 dBm0

Intermodulation distortion, end-to-end Spurious out-of-band signals, end-to-end

0 > ANLGIN > –30 dBm0 36 –30 > ANLGIN > –40 dBm0 30 –40 > ANLGIN > –45 dBm0 25 0 > ANLGIN > –30 dBm0 36 –30 > ANLGIN > –40 dBm0 30 –40 > ANLGIN > –45 dBm0 25

CCITT G.712 (7.1) –35 CCITT G.712 (7.2) –49 CCITT G.712 (6.1) –25 CCITT G.712 (9) –40

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