Texas Instruments SN74ACT7802-25FN, SN74ACT7802-25PN, SN74ACT7802-40FN, SN74ACT7802-40PN, SN74ACT7802-60FN Datasheet

SN74ACT7802

1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS187D – AUGUST 1990 – REVISED APRIL 1998

D

Member of the Texas Instruments
Widebus Family

D

Low-Power Advanced CMOS Technology

D

Load and Unload Clocks Can Be
Asynchronous or Coincident

D

1024 Words × 18 Bits

D

Programmable Almost-Full/Almost-Empty
Flag

D

Empty, Full, and Half-Full Flags

FN PACKAGE

(TOP VIEW)

D

Fast Access Times of 30 ns With a 50-pF
Load

D

Fall-Through Time Is 20 ns Typical

D

Data Rates up to 40 MHz

D

High-Output Drive for Direct Bus Interface

D

3-State Outputs

D

Package Options Include 68-Pin (FN) and
80-Pin Thin Quad Flat (PN) Packages

D17

D15

D16

D14
D13
D12

D1 1

D10

D9

V

CC

D8

GND

D7
D6
D5
D4
D3
D2
D1
D0

NC – No internal connection

87 65493

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

28 29

27

DAF

GND

LDCK

30

GND

UNCKNCNCOERESET

168672

31 32 33 34

CC

NC

NC

V

35 36 37 38 39

GND

AF/AE

V

HF

FULL

CC

GND

66 65

CC

V

CC

EMPTY

V

64 63 62 61

40 41 42 43

Q0

Q1

Q17

GND

Q16

Q2

GND

Q15

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

Q3

V

CC

V

CC

Q14
Q13
GND
Q12
Q11
V

CC

Q10
Q9
GND
Q8
Q7
V

CC

Q6
Q5
GND
Q4

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN74ACT7802
1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS187D – AUGUST 1990 – REVISED APRIL 1998

PN PACKAGE

(TOP VIEW)

NC
GND
GND

Q16
Q17
V

CC

EMPTY

GND

V

CC

RESET

OE

NC

NC

UNCK

GND

D17
D16
D15

NC

NC

CC

Q15

V

79 78 77 76 7580 74

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

22 23

21

Q14

Q13

25 26 27 28

24

GND

GND

Q12

CC

Q11

V

72 71 7073

30 31 32 33

29

Q10

Q9

69 68

Q8

GND

67 66 65 64

34 35 36 37

Q7

V

CC

Q6

Q5

GND

63 62 61

38 39 40

GND

Q4

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

V

CC

V

CC

NC
Q3
Q2
GND
Q1
Q0
V

CC

HF
FULL
GND
GND
AF/AE
V

CC

NC
NC
LDCK
GND
NC

NC

D14

D13

NC – No internal connection

D12

D4D3D2

D6

D7

D9

D8

D10

V

CC

GND

D1 1

D5

D1

D0

DAF

NC

description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ACT7802 is a 1024-word by 18-bit FIFO for high-speed applications. It processes data
in a bit-parallel format at rates up to 40 MHz and access times of 30 ns.

Data is written into the FIFO memory on a low-to-high transition on the load-clock (LDCK) input and is read out
on a low-to-high transition on the unload-clock (UNCK) input. The memory is full when the number of words
clocked in exceeds by 1024 the number of words clocked out. When the memory is full, LDCK has no effect on
the data in the memory; when the memory is empty, UNCK has no effect.

A low level on the reset (RESET
almost full/almost empty (AF/AE) high, half full (HF) low, and empty (EMPTY
to any specific logic level. The FIFO must be reset upon power up. The Q outputs are noninverting and are in
the high-impedance state when the output-enable (OE) input is low.

When writing to the FIFO after a reset pulse or when the FIFO is empty , the first active transition on LDCK drives
EMPTY

high and causes the first word written to the FIFO to appear on the Q outputs. An active transition on
UNCK is not required to read the first word written to the FIFO. Each subsequent read from the FIFO requires
an active transition on UNCK.

The SN74ACT7802 can be cascaded in the word-width direction but not in the word-depth direction.
The SN74ACT7802 is characterized for operation from 0°C to 70°C.

) input resets the FIFO internal clock stack pointers and sets full (FULL) high,

) low. The Q outputs are not reset

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ACT7802

1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS187D – AUGUST 1990 – REVISED APRIL 1998

logic symbol

†

Φ

FIFO 1024 × 18

SN74ACT7802

OE

DAF

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16
D17

14
13
12
11
10
9
8
7

1
29
5

2
27

26
25
24
23
22
21
20
19
17
15

RESET

LDCK
UNCK

EN1

DEF ALMOST FULL

0

17

ALMOST FULL/EMPTY

Data

HALF FULL

Data

FULL

EMPTY

1

17

35

FULL

36

HF

33

AF/AE

66

EMPTY

38

0

39
41
42
44
46
47
49
50
52
53
55
56
58
59
61
63
64

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17

RESET

LDCK

UNCK

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the FN package.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74ACT7802

I/O

DESCRIPTION

1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

SCAS187D – AUGUST 1990 – REVISED APRIL 1998

functional block diagram

OE

D0–D17

LDCK

UNCK

RESET

DAF

Write

Control

Read

Control

Reset
Logic

Read

Pointer

Write

Pointer

Status-

Flag

Logic

Location 1
Location 2

1024 × 18 RAM

Location 1023

Location 1024

Q0–Q17

EMPTY
FULL
HF

AF/AE

Terminal Functions

TERMINAL

NAME NO.

AF/AE 33 O

DAF

D0–D17
EMPTY 66 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.

FULL 35 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 36 O Half-full flag. HF is high when the FIFO memory contains 512 or more words. HF is low after reset.
LDCK 29 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE 2 I Output enable. When OE is low, the data outputs are in the high-impedance state.

38–39, 41–42,

Q0–Q17

RESET
UNCK 5 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

†

Terminal numbers listed are for the FN package.

49–50, 52–53,
55–56, 58–59,

†

Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value
of 256 can be used for the almost-empty almost-full offset (X). AF/AE is high when memory contains X
or fewer words or (1024 – X) or more words. AF/AE is high after reset.

27 I

7–15, 17,

19–26

44, 46–47,

61, 63–64

1 I Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low.

Define almost-full flag. The high-to-low transition of DAF stores the binary value of data inputs as the
AF/AE offset value (X). With DAF held low , a low pulse on RESET defines AF/AE using X.

I 18-bit data input port

O 18-bit data-output port

4

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