Texas Instruments SN74ACT574DBLE, SN74ACT574DBR, SN74ACT574DW, SN74ACT574DWR, SN74ACT574N Datasheet
...
SN54ACT574, SN74ACT574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS537C – OCTOBER 1995 – REVISED JANUARY 2000
D
Inputs Are TTL-Voltage Compatible
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’ACT574 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in a bus-organized system without need
for interface or pullup components.
) input can be used
SN54ACT574 ...J OR W PACKAGE
SN74ACT574 . . . DB, DW, N, OR PW PACKAGE
SN54ACT574 . . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
1
OE
2
1D
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
GND
10
(TOP VIEW)
2D1DOE
3212019
4
5
6
7
8
910111213
8D
GND
20
19
18
17
16
15
14
13
12
11
CLK
V
8Q
CC
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
1Q
18
17
16
15
14
7Q
2Q
3Q
4Q
5Q
6Q
OE
does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54ACT574 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ACT574 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
Copyright 2000, Texas Instruments Incorporated
1
SN54ACT574, SN74ACT574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS537C – OCTOBER 1995 – REVISED JANUARY 2000
logic symbol
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
†
1
11
2
3
4
5
6
7
8
9
EN
1D
C1
19
18
17
16
15
14
13
12
logic diagram (positive logic)
1
OE
11
CLK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2
To Seven Other Channels
1D
C1
19
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, IIK (VI < 0 or VI > V
Output clamp current, I
Continuous output current, I
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VO < 0 or VO > V
OK
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC)
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC)
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
I
50 µA
V
I
mA
V
I
A
V
I
mA
V
UNIT
SN54ACT574, SN74ACT574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS537C – OCTOBER 1995 – REVISED JANUARY 2000
recommended operating conditions (see Note 3)
SN54ACT574 SN74ACT574
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
= –
OH
OH
OL
I
OZ
I
I
I
CC
∆ICC‡
C
i
= –24
OH
IOH = –50 mA
IOH = –75 mA
= 50 µ
OL
= 24
OL
IOL = 50 mA
IOL = 75 mA
VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
One input at 3.4 V ,
Other inputs at GND or V
VI = VCC or GND 5 V 4.5 pF
†
†
†
†
, literature number SCBA004.
CC
4.5 V 4.4 4.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
5.5 V 3.85
5.5 V 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V 1.65
5.5 V 1.65
CC
5.5 V 0.6 1.5 1.5 mA
TA = 25°C SN54ACT574 SN74ACT574
MIN TYP MAX MIN MAX MIN MAX
CC
CC
0 V
0 V
CC
CC
V
V
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
t
w
t
su
t
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
TA = 25°C SN54ACT574 SN74ACT574
MIN MAX MIN MAX MIN MAX
Pulse duration, CLK high or low 3 5 4 ns
Setup time, data before CLK↑ 2.5 3.5 2.5 ns
Hold time, data after CLK↑ 1 2 1 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ACT574, SN74ACT574
PARAMETER
UNIT
CLK
Q
ns
OE
Q
ns
OE
Q
ns
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS537C – OCTOBER 1995 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5V (unless otherwise noted) (see Figure 1)
CC
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF
pd
TA = 25°C SN54ACT574 SN74ACT574
MIN TYP MAX MIN MAX MIN MAX
100 110 70 85 MHz
2.5 7 11 1.5 13.5 2 12
2 6.5 10 1.5 12.5 1.5 11
2 6.4 9.5 1.5 11 1.5 10
2 6 9 1.5 11 1.5 10
2 7 10.5 1.5 12 1.5 11.5
2 5.5 8.5 1.5 10 1.5 9
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
SCAS537C – OCTOBER 1995 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
500 Ω
500 Ω
S1
SN54ACT574, SN74ACT574
WITH 3-STATE OUTPUTS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
Open
CC
LOAD CIRCUIT
t
w
Input
Input
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
t
PLH
50% V
VOLTAGE WAVEFORMS
CC
t
50% V
PHL
3 V
0 V
V
CC
V
3 V
0 V
OH
OL
Timing Input
Data Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
CC
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V 1.5 V
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
CC
CC
t
h
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
3 V
0 V
3 V
0 V
3 V
0 V
≈V
V
OL
V
OH
≈0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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Copyright 2000, Texas Instruments Incorporated
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