Texas Instruments SN74ACT563DBLE, SN74ACT563DBR, SN74ACT563DW, SN74ACT563DWR, SN74ACT563N Datasheet
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SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550A – NOVEMBER 1995 – REVISED 1996
D
Inputs Are TTL-Voltage Compatible
D
3-State Inverted Outputs Drive Bus Lines
Directly
D
Flow-Through Architecture to Optimize
PCB Layout
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’ACT563 are octal D-type transparent latches
with 3-state outputs. When the latch-enable (LE)
input is high, the Q
complements of the data (D) inputs. When LE is
taken low, the Q outputs are latched at the inverse
logic levels set up at the D inputs.
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In
the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance state and increased high logic
level provide the capability to drive bus lines
without interface or pullup components.
outputs are set to the
SN54ACT563 ...J OR W PACKAGE
SN74ACT563 . . . DB, DW, N, OR PW P ACKAGE
SN54ACT563 . . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
OE
1
1D
2
2D
3
3D
4
4D
5
5D
6
6D
7
7D
8
9
8D
GND
10
(TOP VIEW)
2D1DOE
3 2 1 20 19
4
5
6
7
8
910111213
8D
GND
20
19
18
17
16
15
14
13
12
11
CLK
V
8Q
CC
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
1Q
18
17
16
15
14
7Q
CC
2Q
3Q
4Q
5Q
6Q
OE
does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54ACT563 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ACT563 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
INPUTS
OE LE D
L H H L
L HL H
L LX Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550A – NOVEMBER 1995 – REVISED 1996
logic symbol
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
†
1
11
2
3
4
5
6
7
8
9
EN
C1
1D
1
19
18
17
16
15
14
13
12
logic diagram (positive logic)
1
OE
11
LE
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2
C1
1D
To Seven Other Channels
19
1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
DW package 1.6 W. . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
V
I
24 mA
V
I
A
V
I
mA
V
UNIT
SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550A – NOVEMBER 1995 – REVISED 1996
recommended operating conditions (see Note 3)
SN54ACT563 SN74ACT563
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 8 8 ns/V
T
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
Output voltage 0 V
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
TA = 25°C SN54ACT563 SN74ACT563
MIN TYP MAX MIN MAX MIN MAX
I
I
I
∆I
C
OH
OL
OZ
I
CC
i
CC
CC
= –50 µ
OH
= –
OH
IOH = –50 mA
IOH = –75 mA
= 50 µ
OL
= 24
OL
IOL = 50 mA
IOL = 75 mA
VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
‡
One input at 3.4 V ,
Other inputs at GND or V
VI = VCC or GND 5 V 4.5 pF
†
†
†
†
CC
4.5 V 4.4 4.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
5.5 V 3.85
5.5 V 3.85
4.5 V 0.001 0.1 0.1 0.1
5.5 V 0.001 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
5.5 V 1.65
5.5 V 1.65
5.5 V 0.6 1.6 1.5 mA
CC
CC
0 V
0 V
CC
CC
V
V
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
t
Pulse duration, LE high 3 5 3 ns
w
t
Setup time, data before LE↓ 4 4.5 4.5 ns
su
t
Hold time, data after LE↓ 0 1.5 0 ns
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
TA = 25°C SN54ACT563 SN74ACT563
MIN MAX MIN MAX MIN MAX
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ACT563, SN74ACT563
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550A – NOVEMBER 1995 – REVISED 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO
(INPUT) (OUTPUT)
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance CL = 50 pF, f = 1 MHz 50 pF
pd
TA = 25°C SN54ACT563 SN74ACT563
MIN TYP MAX MIN MAX MIN MAX
3 7 11.5 1 14.5 2.5 12.5
3 6 10 1 12 2.5 11
3 6.5 10.5 1 12.5 2.5 11.5
2.5 5.5 9.5 1 11.5 2 10.5
2.5 5.5 9 1 11.5 2 10
2 5.5 8.5 1 11 2 9.5
3.5 6.5 10.5 1 12 2.5 11.5
2 4.5 8 1 9.5 1 8.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
Input
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
LOAD CIRCUIT
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
S1
2 × V
3 V
0 V
CC
Open
SN54ACT563, SN74ACT563
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS550A – NOVEMBER 1995 – REVISED 1996
TEST S1
Timing Input
Data Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V
Open
2 × V
Open
CC
t
3 V
0 V
h
3 V
0 V
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
t
PHL
50% V
CC
3 V
0 V
V
V
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
CC
t
PZL
t
PZH
1.5 V 1.5 V
t
PLZ
50% V
CC
t
PHZ
50% V
CC
VOLTAGE WAVEFORMS
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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Copyright 1998, Texas Instruments Incorporated
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