Texas Instruments SN74ACT00D, SN74ACT00DBLE, SN74ACT00DBR, SN74ACT00DR, SN74ACT00N Datasheet

SN54ACT00, SN74ACT00

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCAS523B – AUGUST 1995 – REVISED AUGUST 1999

D

Inputs Are TTL-Voltage Compatible

D

EPIC

(Enhanced-Performance Implanted

CMOS) 1-µm Process

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), DIP
(N) Packages, Ceramic Chip Carriers (FK),
Flat (W), and DIP (J) Packages

description

The ‘ACT00 devices contain four independent 2-input
NAND gates. Each gate performs the Boolean
function of Y = A

The SN54ACT00 is characterized for operation over
the full military temperature range of –55°C to 125°C.
The SN74ACT00 is characterized for operation from
–40°C to 85°C.

S

B or Y = A + B in positive logic.

FUNCTION TABLE

(each gate)

INPUTS

A B

H H L

L XH

X L H

OUTPUT

Y

SN54ACT00 ...J OR W PACKAGE

SN74ACT00 . . . D, DB, N, OR PW PACKAGE

SN54ACT00 . . . FK PACKAGE

1Y

NC

2A

NC

2B

NC – No internal connection

(TOP VIEW)

1A

1

1B

2

1Y

3

2A

4

2B

5

2Y

6

GND

7

(TOP VIEW)

1B1ANC

3212019

4
5
6
7
8

910111213

2Y

GND

14
13
12
11
10

NC

V

CC

4B
4A
4Y
3B
3A

9

3Y

8

CC

V

4B

4A

18

NC

17

4Y

16

NC

15

3B

14

3Y

3A

logic symbol

1A
1B
2A
2B
3A
3B
4A
4B

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

†

1
2
4
5
9
10
12
13

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

&

3

1Y

6

2Y

8

3Y

11

4Y

logic diagram, each gate (positive logic)

A
B

Copyright  1999, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

Y

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54ACT00, SN74ACT00

UNIT

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCAS523B – AUGUST 1995 – REVISED AUGUST 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, IOK (V
Continuous output current, I
Continuous current through V

(see Note 1) –0.5 V to V

I

(see Note 1) –0.5 V to V

O

IK

(V

< 0 or V

I

O

O

> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

< 0 or V

(V

O

or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC
CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54ACT00 SN74ACT00

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

V

O

I

OH

I

OL

∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T

A

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
Output voltage 0 V
High-level output current –24 –24 mA
Low-level output current 24 24 mA

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

CC
CC

0 V
0 V

CC
CC

V
V

2

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PARAMETER

TEST CONDITIONS

V

UNIT

I

50 µA

V

V

I

50 µA

VOLI

24 mA

V

PARAMETER

UNIT

A or B

Y

ns

SN54ACT00, SN74ACT00

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCAS523B – AUGUST 1995 – REVISED AUGUST 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

CC

= –

OH

OH

I

I

I

CC

∆I

CC

C

i

†

Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.

‡

This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

IOH = – 24 mA
IOH = – 50 mA

IOH = –75 mA

=

OL

=

OL

IOL = 50 mA
IOL = 75 mA
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA
One input at 3.4 V ,

‡

Other inputs at GND or V
VI = VCC or GND 5 V 2.6 pF

†

†

†
†

CC

4.5 V 4.4 4.49 4.4 4.4

5.5 V 5.4 5.49 5.4 5.4

4.5 V 3.86 3.7 3.76

5.5 V 4.86 4.7 4.76

5.5 V 3.85

5.5 V 3.85

4.5 V 0.001 0.1 0.1 0.1

5.5 V 0.001 0.1 0.1 0.1

4.5 V 0.36 0.5 0.44

5.5 V 0.36 0.5 0.44

5.5 V 1.65

5.5 V 1.65

5.5 V 0.6 1.6 1.5 mA

TA = 25°C SN54ACT00 SN74ACT00

MIN TYP MAX MIN MAX MIN MAX

switching characteristics over recommended operating free-air temperature range,
V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

CC

TA = 25°C SN54ACT00 SN74ACT00

MIN TYP MAX MIN MAX MIN MAX

1.5 5.5 9 1 9.5 1 9.5

1.5 4 7 1 8 1 8

t

PLH

t

PHL

FROM TO

(INPUT) (OUTPUT)

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

pd

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3

SN54ACT00, SN74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SCAS523B – AUGUST 1995 – REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

TEST S1

t

PLH/tPHL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

NOTES: A. CL includes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.

Open

500 Ω

500 Ω

Figure 1. Load Circuit and Voltage Waveforms

S1

2 × V

Open

CC

Input

In-Phase

Output

Out-of-Phase

Output

1.5 V 1.5 V

t

PLH

50% V

t

PHL

50% V

VOLTAGE WAVEFORMS

CC

CC

t

PHL

50% V

t

PLH

50% V

CC

CC

3 V

0 V

V

V

V

V

OH

OL

OH

OL

4

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Copyright  1999, Texas Instruments Incorporated