Texas Instruments SN74AC74D, SN74AC74DBLE, SN74AC74DBR, SN74AC74DR, SN74AC74N Datasheet
...
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), Flat
(W), and DIP (J,N) Packages
description
The ’AC74 are dual positive-edge-triggered
D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
at D can be changed without affecting the levels
at the outputs.
The SN54AC74 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AC74 is characterized for
operation from –40°C to 85°C.
and CLR are
SN54AC74 ...J OR W PACKAGE
SN74AC74 . . . D, DB, N, OR PW PACKAGE
SN54AC74 . . . FK PACKAGE
1CLK
NC
1PRE
NC
1Q
NC – No internal connection
(TOP VIEW)
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
(TOP VIEW)
1D
3 2 1 20 19
4
5
6
7
8
910111213
1Q
1
2
3
4
5
6
7
1CLR
GND
NC
NC
14
13
12
11
10
9
8
V
2Q
CC
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
2CLR
18
17
16
15
14
2Q
2D
NC
2CLK
NC
2PRE
PRE
L H X X H L
H LXXLH
L LXXH†H
H H ↑ HHL
H H ↑ LLH
H H L X Q
†
This configuration is unstable; that is, it does not
persist when either PRE
inactive (high) level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
INPUTS
CLR
CLK D Q Q
or CLR returns to its
OUTPUTS
Q
0
†
0
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
†
1PRE
1CLK
1D
1CLR
2PRE
2CLK
2D
2CLR
4
3
2
1
10
11
12
13
S
C1
1D
R
logic diagram, each flip-flop (positive logic)
PRE
CLK
C
C
C
TG
5
1Q
6
1Q
9
2Q
8
2Q
Q
CLR
C
D
TG
C
TG
C
C
C
C
TG
Q
C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):D package 1.25 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
DB package 0.5 W. . . . . . . . . . . . . . . . . . .
N package 1.1 W. . . . . . . . . . . . . . . . . . . .
PW package 0.5 W. . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54AC74 SN74AC74
MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
Supply voltage 2 6 2 6 V
CC
VCC = 3 V 2.1 2.1
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 5.5 V 3.85 3.85
VCC = 3 V 0.9 0.9
VCC = 4.5 V
VCC = 5.5 V 1.65 1.65
VCC = 3 V –12 –12
VCC = 4.5 V
VCC = 5.5 V –24 –24
VCC = 3 V 12 12
VCC = 4.5 V
VCC = 5.5 V 24 24
3.15 3.15
1.35 1.35
CC
CC
–24 –24
24 24
0 V
0 V
CC
CC
V
V
V
V
mA
mA
†
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3
SN54AC74, SN74AC74
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
I
mA
V
V
I
24 mA
I
V
V
GND
5.5 V
A
UNIT
twPulse duration
ns
t
S
CLK↑
ns
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
3 V 2.9 4.49 2.9 2.9
IOH = –50 µA
OH
OL
Data pins
I
Control pins
I
CC
C
i
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
IOH = –12 mA 3 V 2.56 2.4 2.46
= –24
OH
CC
†
†
†
†
or
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA 3 V 0.36 0.5 0.44
=
OL
IOL = 50 mA
IOL = 75 mA
=
I
VI = VCC or GND, IO = 0 5.5 V 2 40 20 µA
VI = VCC or GND 5 V 3 pF
4.5 V 4.4 5.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
5.5 V 3.85
5.5 V 3.85
3 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
5.5 V 0.001 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
5.5 V 1.65
5.5 V 1.65
TA = 25°C SN54AC74 SN74AC74
MIN TYP MAX MIN MAX MIN MAX
±0.1 ±1 ±1
±0.1 ±1 ±1
µ
timing requirements over recommended operating free-air temperature range,
V
= 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C SN54AC74 SN74AC74
MIN MAX MIN MAX MIN MAX
f
clock
su
t
h
Clock frequency 0 100 0 100 0 100 MHz
PRE or CLR low 5.5 8 7
CLK 5.5 8 7
etup time, data before
Hold time, data after CLK↑ 0.5 0.5 0.5 ns
Data 4 5 4.5
PRE or CLR inactive 0 0.5 0
4
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UNIT
twPulse duration
ns
t
S
CLK↑
ns
PARAMETER
UNIT
PRE
CLR
Q
Q
ns
CLK
Q
Q
ns
PARAMETER
UNIT
PRE
CLR
Q
Q
ns
CLK
Q
Q
ns
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
timing requirements over recommended operating free-air temperature range,
= 5 V"0.5 V (unless otherwise noted) (see Figure 1)
V
CC
TA = 25°C SN54AC74 SN74AC74
MIN MAX MIN MAX MIN MAX
f
clock
su
t
h
switching characteristics over recommended operating free-air temperature range,
V
CC
Clock frequency 0 140 0 140 0 140 MHz
PRE or CLR low 4.5 5.5 5
CLK 4.5 5.5 5
etup time, data before
Hold time, data after CLK↑ 0.5 0.5 0.5 ns
Data 3 4 3
PRE or CLR inactive 0 0.5 0
= 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C SN54AC74 SN74AC74
MIN TYP MAX MIN MAX MIN MAX
100 125 70 95 MHz
3.5 8 12 1 13 2.5 13
4 10.5 12 1 14 3.5 13.5
4.5 8 13.5 1 17.5 4 16
3.5 8 14 1 13.5 3.5 14.5
f
max
t
PLH
t
PHL
t
PLH
t
PHL
FROM TO
(INPUT) (OUTPUT)
or
or
or
switching characteristics over recommended operating free-air temperature range,
V
= 5 V " 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PLH
t
PHL
or
operating characteristics, V
C
Power dissipation capacitance CL = 50 pF, f = 1 MHz 45 pF
pd
= 3.3 V, TA = 25°C
CC
PARAMETER
or
or
TA = 25°C SN54AC74 SN74AC74
MIN TYP MAX MIN MAX MIN MAX
140 160 95 125 MHz
2.5 6 9 1 9.5 2 10
3 8 9.5 1 10.5 2.5 10.5
3.5 6 10 1 12 3 10.5
2.5 6 10 1 10 2.5 10.5
TEST CONDITIONS TYP UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54AC74, SN74AC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
CC
CC
S1
50% V
CC
t
PHL
50% V
t
PLH
50% V
Open
V
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
CC
Input
Timing Input
Data Input
500 Ω
50% V
500 Ω
CC
50% V
50% V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr v2.5 ns, tf v 2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
TEST S1
t
PLH/tPHL
t
w
50% V
CC
VOLTAGE WAVEFORMS
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
Open
CC
50% V
t
h
50% V
CC
CC
V
0 V
V
0 V
V
0 V
CC
CC
CC
Figure 1. Load Circuit and Voltage Waveforms
6
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