Texas Instruments SN74ABT5403DW, SN74ABT5403DWR Datasheet

SN54ABT5403, SN74ABT5403

12-BIT LINE/MEMORY DRIVERS

WITH 3-STATE OUTPUTS

SCBS236B – JUNE 1992 – REVISED JANUARY 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

T ypical V

OLP

(Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

D

T ypical V

OL V

(Output Undershoot) < 0.5 V at

VCC = 5 V, TA = 25°C

D

Package Options Include Plastic
Small-Outline (DW) Package, Ceramic Chip
Carriers (FK), and DIPs (JT)

description

These 12-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.

The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1

or OE2) input is high, all 12 outputs are in the
high-impedance state. These devices provide
inverted data.

The outputs, which are designed to source or sink
up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.

T o ensure the high-impedance state during power
up or power down, OE

should be tied to V

CC

through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.

The SN54ABT5403 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT5403 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUT

OE1 OE2 D

Y

L L L H
L LH L
H XX Z
X H X Z

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Y1
Y2
Y3
Y4
Y5
Y6

GND

Y7
Y8

Y9
Y10
Y11
Y12

OE1

D1
D2
D3
D4
D5
D6
D7
V

CC

D8
D9
D10
D11
D12
OE2

SN54ABT5403 . . . JT PACKAGE

SN74ABT5403 . . . DW PACKAGE

(TOP VIEW)

Y5

Y6

GND

Y7Y8Y9

Y10

D4D5D6D7VD8D9

3212827

12 13 14 15 16 17 18

5
6
7
8
9

10

11

25
24
23
22
21
20
19

D10
D11
D12
OE2
OE1
Y12
Y11

D3
D2
D1
Y1
Y2
Y3
Y4

426

SN54ABT5403 . . . FK PACKAGE

(TOP VIEW)

CC

Copyright  1997, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS

SCBS236B – JUNE 1992 – REVISED JANUARY 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

28

D1

27

D2

26

D3

25

D4

24

D5

Y1

1

Y2

2

Y3

3

Y4

4

Y5

5

Y6

6

Y7

8

Y8

9

23

D6

22

D7

20

D8

15

14

OE1
OE2

EN

&

Y9

10

Y10

11

19

D9

18

D10

1

17

D11 Y11

12

16

D12

Y12

13

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

Pin numbers shown are for the DW and JT packages.

logic diagram (positive logic)

Y1

To 11 Other Channels

OE1
OE2

D1

28

1

15

14

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2): DW package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.