SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
D
T ypical V
OL V
(Output Undershoot) < 0.5 V at
VCC = 5 V, TA = 25°C
D
Package Options Include Plastic
Small-Outline (DW) Package, Ceramic Chip
Carriers (FK), and DIPs (JT)
description
These 12-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1
or OE2) input is high, all 12 outputs are in the
high-impedance state. These devices provide
inverted data.
The outputs, which are designed to source or sink
up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.
T o ensure the high-impedance state during power
up or power down, OE
should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN54ABT5403 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT5403 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
OE1 OE2 D
Y
L L L H
L LH L
H XX Z
X H X Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Y1
Y2
Y3
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
OE1
D1
D2
D3
D4
D5
D6
D7
V
CC
D8
D9
D10
D11
D12
OE2
SN54ABT5403 . . . JT PACKAGE
SN74ABT5403 . . . DW PACKAGE
(TOP VIEW)
Y5
Y6
GND
Y7Y8Y9
Y10
D4D5D6D7VD8D9
3212827
12 13 14 15 16 17 18
5
6
7
8
9
10
11
25
24
23
22
21
20
19
D10
D11
D12
OE2
OE1
Y12
Y11
D3
D2
D1
Y1
Y2
Y3
Y4
426
SN54ABT5403 . . . FK PACKAGE
(TOP VIEW)
CC
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
28
D1
27
D2
26
D3
25
D4
24
D5
Y1
1
Y2
2
Y3
3
Y4
4
Y5
5
Y6
6
Y7
8
Y8
9
23
D6
22
D7
20
D8
15
14
OE1
OE2
EN
&
Y9
10
Y10
11
19
D9
18
D10
1
17
D11 Y11
12
16
D12
Y12
13
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the DW and JT packages.
logic diagram (positive logic)
Y1
To 11 Other Channels
OE1
OE2
D1
28
1
15
14
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DW package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ABT5403 SN74ABT5403
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –12 –12 mA
I
OL
Low-level output current 12 12 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT5403 SN74ABT5403
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –1 mA 3.35 3.7 3.3 3.35
VCC = 5 V, IOH = –1 mA 3.85 4.2 3.8 3.85
V
OH
IOH = –3 mA 3 3.1
V
V
CC
= 4.5
V
IOH = –12 mA 2.6 2.6
IOL = 8 mA 0.8 0.65
VOLV
CC
= 4.5
V
IOL = 12 mA 0.8
V
V
hys
100 mV
I
I
VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µA
I
OZH
VCC = 5.5 V, VO = 2.7 V 50 50 50 µA
I
OZL
VCC = 5.5 V, VO = 0.5 V –50 –50 –50 µA
I
off
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
I
CEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high 50 50 50 µA
I
O
VCC = 5.5 V, VO = 2.5 V –25 –45 –100 –25 –100 –25 –100 mA
I
OS
‡
VCC = 5.5 V, VO = 0 –50 –200 –50 –200 –50 –200 mA
=
Outputs high 5 50 50 50 µA
I
CC
V
CC
= 5.5 V,
IO = 0,
Outputs low 36 45 45 45 mA
VI = VCC or GND
Outputs disabled 1 50 50 50 µA
p
VCC = 5.5 V,
One input at 3.4 V ,
Outputs enabled 1.5 1.5 1.5
∆I
CC
§
Data inputs
,
Other inputs at
VCC or GND
Outputs disabled 0.05 0.05 0.05
mA
Control inputs
VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND
1.5 1.5 1.5
C
i
VI = 2.5 V or 0.5 V 3 pF
C
o
VO = 2.5 V or 0.5 V 8 pF
†
All typical values are at VCC = 5 V.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
§
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
SN54ABT5403 SN74ABT5403
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
t
PLH
2 4.5 6.1 2 7 2 6.9
t
PHL
D
Y
1.5 4.4 5.2 1.5 5.9 1.5 5.7
ns
t
PZH
2.5 5.7 6.6 2.5 8.6 2.5 8.5
t
PZL
OE
Y
2 4.4 5.5 2 6.9 2 6.8
ns
t
PHZ
1.5 3.6 4.4 1.5 5.5 1.5 5.2
t
PLZ
OE
Y
1.5 4.2 5.4 1.5 7.4 1.5 6.9
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABT5403, SN74ABT5403
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS236B – JUNE 1992 – REVISED JANUARY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V 1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V
1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
Output
Control
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5
n
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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