Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
Low Supply-Current Requirements . . .
30 mA Max
D
Wide Positive and Negative Input/Output
Bus-Voltage Ranges
D
Thermal Shutdown Protection
D
Driver Positive and Negative Current
Limiting
D
Receiver Input Hysteresis
D
Glitch-Free Power-Up and Power-Down
Protection
D
Receiver Open-Circuit Fail-Safe Design
description
D OR P PACKAGE
(TOP VIEW)
RE
DE
1
R
2
3
4
D
8
7
6
5
V
CC
B
A
GND
The SN65ALS176 and SN75ALS176 series differential bus transceivers are designed for bidirectional data
communication on multipoint bus transmission lines. They are designed for balanced transmission lines and
meet TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendations V.1 1 and X.27.
The SN65ALS176 and SN75ALS176 series combine a 3-state, differential line driver and a differential input line
receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, that can be connected together externally to function as a direction control.
The driver differential outputs and the receiver differential inputs are connected internally to form a differential
input/output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or
V
= 0. This port features wide positive and negative common-mode voltage ranges, making the device
CC
suitable for party-line applications.
The SN65ALS176 is characterized for operation from –40°C to 85°C, and the SN75ALS176 series is
characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
†
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
0°C to 70°C
–40°C to 85°C15SN65ALS176DSN65ALS176P
†
t
This is the maximum range that the driver or receiver delay times vary
sk(lim)
over temperature, VCC, and process (device to device).
‡
The D package is available taped and reeled. Add the suffix R to the device type
(e.g., SN75ALS176DR).
t
sk(lim)
10
7.5
5
SMALL OUTLINE
SN75ALS176D
SN75ALS176AD
SN75ALS176BD
(D)
‡
Function Tables
DRIVER
INPUT
DDE
HHHL
LHLH
XLZZ
H = high level, L = low level, X = irrelevant,
Z = high impedance
ENABLE
OUTPUTS
AB
PLASTIC DIP
(P)
SN75ALS176P
SN75ALS176AP
SN75ALS176BP
DIFFERENTIAL INPUTS
VID ≥ 0.2 VLH
–0.2 V < VID < 0.2 VL?
VID ≤ –0.2 VLL
Inputs openLH
H = high level, L = low level, X = irrelevant,
Z = high impedance
logic symbol
3
DE
2
RE
4
D
1
R
§
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
§
EN1
EN2
1
1
2
RECEIVER
A–BRER
XHZ
ENABLEOUTPUT
logic diagram (positive logic)
3
DE
4
RE
D
2
1
R
6
A
7
B
6
A
7
Bus
B
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
EQUIVALENT OF EACH INPUT
V
CC
R
(eq)
Input
Driver Input: R
Enable Inputs: R
R
= equivalent resistor
(eq)
= 3 kΩ NOM
(eq)
= 8 kΩ
(eq)
NOM
TYPICAL OF A AND B I/O PORTSTYPICAL OF RECEIVER OUTPUT
V
CC
180 kΩ
NOM
Connected
on A Port
A or B
18 kΩ
NOM
180 kΩ
NOM
Connected
on B Port
3 kΩ
NOM
1.1 kΩ
NOM
85 Ω
NOM
V
CC
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONS
V
IK
V
O
| V
OD1
| V
OD2
V
OD3
∆| VOD |
∆| VOC |
I
IH
I
IL
I
OS
†
The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡
All typical values are at VCC = 5 V and TA = 25°C.
§
The minimum V
¶
∆ | VOD | and ∆ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from one logic state
to the other.
#
Duration of the short circuit should not exceed one second for this test.
NOTE 4: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a
VO = –4 VSN65ALS176
VO = –6 VSN75ALS176
VO = 0–150
VO = V
CC
VO = 8 V
or 2 V, whichever is greater.
OD1
,
†
VO = 12 V1
VO = –7 V–0.8
Outputs enabled2330
Outputs disabled1926
MINTYP
1/2V
OD1
§
or 2
‡
MAXUNIT
V
±0.2V
3
–1
±0.2V
–
mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
R
C
See Figure 3
ns
()
§
()
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
SN65ALS176
PARAMETERTEST CONDITIONSMINTYP†MAXUNIT
t
d(OD)
t
sk(p)
t
sk(lim)
t
t(OD)
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Pulse skew is defined as the |t
§
Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
SN75ALS176, SN75ALS176A, SN75ALS176B
t
d(OD)
t
sk(p)
t
sk(lim)
t
t(OD)
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Pulse skew is defined as the |t
§
Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
Differential output delay timeRL = 54 Ω, CL = 50 pF, See Figure 315ns
Pulse skew
Pulse skew
Differential output transition timeRL = 54 Ω, CL = 50 pF, See Figure 38ns
Output enable time to high levelRL = 110 Ω,CL = 50 pF, See Figure 480ns
Output enable time to low levelRL = 110 Ω,CL = 50 pF, See Figure 530ns
Output disable time from high levelRL = 110 Ω,CL = 50 pF, See Figure 450ns
Output disable time from low levelRL = 110 Ω, CL = 50 pF, See Figure 530ns
Differential output delay time
Pulse skew
Pulse skew
Differential output transition timeRL = 54 Ω, CL = 50 pF, See Figure 38ns
Output enable time to high levelRL = 110 Ω, CL = 50 pF, See Figure 42350ns
Output enable time to low levelRL = 110 Ω, CL = 50 pF, See Figure 51420ns
Output disable time from high levelRL = 110 Ω, CL = 50 pF, See Figure 42035ns
Output disable time from low levelRL = 110 Ω, CL = 50 pF, See Figure 5817ns
‡
§
– t
PLH
PARAMETERTEST CONDITIONSMINTYP†MAXUNIT
‡
PLH
| of each channel of the same device.
PHL
’ALS1763813
’ALS176A
’ALS176B5810
’ALS17610
’ALS176A
’ALS176B5
– t
| of each channel of the same device.
PHL
= 54 Ω,
L
RL = 54 Ω, CL = 50 pF, See Figure 3
RL = 54 Ω, CL = 50 pF, See Figure 302ns
RL = 54 Ω, CL = 50 pF, See Figure 3
= 50 pF,
L
p
02
15
4711.5
7.5
ns
ns
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER
V
O
| V
|V
OD1
| V
|Vt (RL = 100 Ω)Vt (RL = 54 Ω)
OD2
| V
|None
OD3
∆ | VOD ||| Vt | – | Vt |||| Vt | – | Vt ||
V
OC
∆ | VOC || Vos – Vos || Vos – Vos |
I
OS
I
O
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIA/EIA-422-BTIA/EIA-485-A
Voa, V
ob
o
| Vos || Vos |
| Isa |, | Isb |None
| Ixa |, | Ixb |Iia, I
Voa, V
ob
V
o
Vt (test termination
measurement 2)
ib
VOHHigh-level output voltage
ID
,
OH
µ,
2.7
V
VOLLow-level output voltage
ID
,
OL
,
0.45
V
VILine input current
,
mA
ICCSupply current
No load
mA
ID
,
L
,
C
See Figure 8
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMIN
V
IT+
V
IT–
V
hys
V
IK
I
OZ
I
IH
I
IL
r
I
I
OS
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only .
NOTE 5: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
SN65ALS176
PARAMETERTEST CONDITIONSMINTYP†MAXUNIT
t
pd
t
sk(p)
t
sk(lim)
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 5 V, TA = 25°C.
§
Pulse skew is defined as the |t
¶
Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
Propagation time
Pulse skew
Pulse skew
Output enable time to high level1118ns
Output enable time to low level
Output disable time from high level
Output disable time from low level30ns
§
¶
– t
PLH
| of each channel of the same device.
PHL
V
= –1.5 V to 1.5 V,C
See Figure 7
RL = 54 Ω,
See Figure 3
p
= 15 pF,
L
= 15 pF,
CL = 50 pF,
25ns
02ns
15ns
1118ns
50ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
ID
,
L
,
§
()
See Figure 3
C
See Figure 8
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) (continued)
SN75ALS176, SN75ALS176A, SN75ALS176B
PARAMETERTEST CONDITIONSMIN
’ALS17691419
t
pd
t
sk(p)
t
sk(lim)
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Pulse skew is defined as the |t
§
Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
Propagation time
Pulse skew
Pulse skew
Output enable time to high level714ns
Output enable time to low level
Output disable time from high level
Output disable time from low level817ns
‡
’ALS176A
’ALS176B
’ALS17610
’ALS176A
’ALS176B
– t
PLH
| of each channel of the same device.
PHL
V
= –1.5 V to 1.5 V,C
See Figure 7
RL = 54 Ω,
p
= 15 pF,
L
= 15 pF,
CL = 50 pF,
10.5
11.51316.5
†
TYP
MAXUNIT
1418
02ns
7.5
2035ns
2035ns
ns
ns
5
PARAMETER MEASUREMENT INFORMATION
R
L
V
Figure 1. Driver V
V
OD3
Figure 2. Driver V
OD2
OD2
375 Ω
60 Ω
375 Ω
2
R
2
and V
OD3
L
V
OC
OC
V
test
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
C. t
d(OD)
50 Ω
= t
3 V
TEST CIRCUITVOLTAGE WAVEFORMS
or t
d(ODH)
d(ODL)
Figure 3. Driver Test Circuit and Voltage Waveforms
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
3 V
1.5 V
0 V
t
d(ODL)
(see Note C)
50%
10%
≈2.5 V
≈ – 2.5 V
t
t(OD)
90%90%
RL = 54 Ω
CL = 50 pF
(see Note A)
Output
Input
t
d(ODH)
(see Note C)
Output
t
t(OD)
50%
10%
1.5 V
0 V or 3 V
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
50 Ω
TEST CIRCUITVOLTAGE WAVEFORMS
CL = 50 pF
(see Note A)
Figure 4. Driver Test Circuit and Voltage Waeforms
S1
Output
RL = 110 Ω
Input
Output
1.5 V
t
2.3 V
t
PHZ
1.5 V
PZH
3 V
0 V
V
V
off
OH
≈0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
0 V or 3 V
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
50 Ω
TEST CIRCUITVOLTAGE WAVEFORMS
(see Note A)
Figure 5. Driver Test Circuit and Voltage Waveforms
V
ID
S1
CL = 50 pF
5 V
RL = 110 Ω
Output
V
OL
+I
Input
Output
V
OH
OL
t
PZL
–I
OH
2.3 V
3 V
1.5 V1.5 V
0 V
t
PLZ
5 V
0.5 V
V
OL
Figure 6. Receiver VOH and VOL Test Circuit
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO=50Ω.
C. tpd = t
PLH
51 Ω
1.5 V
0 V
TEST CIRCUITVOLTAGE WAVEFORMS
or t
PHL
Figure 7. Receiver Test Circuit and Voltage Waveforms
Output
CL = 15 pF
(see Note A)
Input
t
PLH
(see Note C)
Output
1.5 V
1.3 V
1.5 V
(see Note C)
1.3 V
t
PHL
3 V
0 V
V
V
OH
OL
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
5 V
S2
Input
Output
Input
Output
1.5 V
– 1.5 V
Generator
(see Note B)
t
PHZ
0.5 V
1.5 V
S1
t
PZH
50 Ω
1.5 V
3 V
S1 to 1.5 V
S2 Open
S3 Closed
0 V
V
OH
1.5 V
0 V
3 V
S1 to 1.5 V
S2 Closed
S3 Closed
0 V
V
OH
≈ 1.3 V
CL = 15 pF
(see Note A)
TEST CIRCUIT
Input
Output
Input
Output
t
PLZ
1.5 V
2 kΩ
t
PZL
0.5 V
Output
1N916 or Equivalent5 kΩ
S3
1.5 V
3 V
1.5 V
S1 to – 1.5 V
0 V
S2 Closed
S3 Open
≈4.5 V
V
OL
3 V
S1 to – 1.5 V
S2 Closed
S3 Closed
0 V
≈1.3 V
V
OL
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO=50Ω.
Figure 8. Receiver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOLTAGE WAVEFORMS
11
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
5
4.5
4
3.5
3
2.5
2
1.5
– High-Level Output Voltage – V
1
OH
V
0.5
0
0– 20– 40– 60
IOH – High-Level Output Current – mA
DRIVER
vs
Figure 9
TYPICAL CHARACTERISTICS
5
VCC = 5 V
TA = 25°C
– 80– 100– 120
4.5
4
3.5
3
2.5
2
1.5
– Low-Level Output Voltage – V
1
OL
V
0.5
0
0204060
†
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VCC = 5 V
TA = 25°C
80100120
IOL – Low-Level Output Current – mA
Figure 10
DIFFERENTIAL OUTPUT VOLTAGE
OUTPUT CURRENT
4
3.5
3
2.5
2
1.5
– Differential Output Voltage – V
1
OD
V
0.5
0
0102030405060
IO – Output Current – mA
Figure 11
DRIVER
vs
VCC = 5 V
TA = 25°C
708090 100
†
Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
5
VID = 0.3 V
4.5
TA = 25°C
4
3.5
3
2.5
2
1.5
– High-Level Output Voltage – V
OH
V
0.5
VCC = 4.75 V
1
0
0– 10– 20– 30
– 5
– 15
IOH – High-Level Output Current – mA
TYPICAL CHARACTERISTICS
RECEIVER
vs
VCC = 5.25 V
VCC = 5 V
– 25– 35– 45
– 40– 50
†
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
VCC = 5 V
4.5
VID = 300 mV
IOH = – 440 µA
4
3.5
3
2.5
2
1.5
– High-Level Output Voltage – V
1
OH
V
0.5
0
– 40 – 20020406080
TA – Free-Air Temperature – °C
100 120
LOW-LEVEL OUTPUT CURRENT
0.6
VCC = 5 V
TA = 25°C
0.5
VID = – 300 mV
0.4
0.3
0.2
– Low-Level Output Voltage – V
OL
V
0.1
0
0510
IOL – Low-Level Output Current – mA
Figure 12
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
152025
Figure 14
30
Figure 13
LOW-LEVEL OUTPUT VOLTAGE
FREE-AIR TEMPERATURE
0.6
VCC = 5 V
VID = – 300 mA
IOL = 8 mA
0.5
0.4
0.3
0.2
– Low-Level Output Voltage – VV
OL
0.1
0
– 40 – 200204060
TA – Free-Air Temperature – °C
Figure 15
RECEIVER
vs
80100 120
†
Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
4
3
2
– Output Voltage – V
O
V
1
0
VCC = 5.25 V
VCC = 4.75 V
00.511.5
V
– Enable Voltage – V
I(en)
VID = 0.3 V
Load = 8 kΩ to GND
TA = 25°C
VCC = 5 V
22.53
Figure 16
†
Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
6
5
4
3
– Output Voltage – V
2
O
V
1
0
00.51
†
OUTPUT VOLTAGE
ENABLE VOLTAGE
VID = 0.3 V
Load = 1 kΩ to V
TA = 25°C
VCC = 5 V
V
I(en)
RECEIVER
vs
VCC = 5.25 V
CC
VCC = 4.75 V
1.522.5
– Enable Voltage – V
Figure 17
3
APPLICATION INFORMATION
R
T
Up to 53
Transceivers
•••
NOTE A: The line should terminate at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short
as possible.
Figure 18. Typical Application Circuit
R
T
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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