Texas Instruments SN65ALS1176D, SN65ALS1176DR, SN65ALS1176P Datasheet

SN65ALS1176

DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Meets or Exceeds the Requirements of
TIA/EIA-422-B, TIA/EIA-485-A, and ITU
Recommendations V.11 and X.27

D

Recommended for PROFIBUS Applications

D

Operates at Data Rates up to 35 MBaud

D

Operating Temperature Range

...–25°C to 85°C

D

Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments

D

Low Supply-Current Requirement

. . . 30 mA Max

D

Wide Positive and Negative Input/Output
Bus-Voltage Ranges

D

Thermal-Shutdown Protection

D

Driver Positive- and Negative-Current
Limiting

D

Receiver Input Hysteresis

D

Glitch-Free Power-Up and Power-Down
Protection

D

Receiver Open-Circuit Fail-Safe Design

D

Package Options Include Plastic
Small-Outline (D) Package and (P) DIPs

description

The SN65ALS1 176 dif ferential bus transceiver is designed for bidirectional data communication on multipoint
bus transmission lines. It is designed for balanced transmission lines and meets TIA/EIA-422-B, TIA/EIA-485-A,
and ITU Recommendations V.11 and X.27.

The SN65ALS1 176 combines a 3-state differential line driver and a differential input line receiver , both of which
operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,
respectively , that can be connected together externally to function as a direction control. The driver differential
outputs and the receiver differential inputs are connected internally to form a differential input/output (I/O) bus
port that is designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. This port features
wide positive and negative common-mode voltage ranges, making the device suitable for party-line
applications.

The SN65ALS1176 is characterized for operation from –25°C to 85°C.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4

8
7
6
5

R
RE
DE

D

V

CC

B
A
GND

D† OR P PACKAGE

(TOP VIEW)

†

The D package is available taped and
reeled. Add the suffix R to the device
type (e.g., SN65ALS1176DR).

SN65ALS1176
DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables

DRIVERS

INPUT

ENABLE

OUTPUTS

D DE

A B

H H H L
L H L H
X L Z Z

RECEIVER

DIFFERENTIAL INPUTS ENABLE OUTPUT

A–B RE R

VID ≥ 0.2 V L H

–0.2 V < VID < 0.2 V L ?

VID ≤ –0.2 V L L

X H Z

Inputs open L H

H = high level, L = low level, X = irrelevant,
? = Indeterminate, Z = high impedance (off)

logic symbol

†

R

D

RE

DE

1

4

2

3

EN2

EN1

B

A

7

6

2

1
1

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

logic diagram (positive logic)

Bus

B

7

A

6

1

R

2

RE

3

DE

4

D

SN65ALS1176

DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematics of inputs and outputs

EQUIVALENT OF EACH INPUT

Driver Input: R

(eq)

= 3 kΩ NOM

Enable Inputs: R

(eq)

= 8 kΩ

NOM

R

(eq)

= equivalent resistor

TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT

Output

85 Ω
NOM

V

CC

180 kΩ
NOM
Connected
on B Port

1.1 kΩ
NOM

3 kΩ
NOM

18 kΩ

NOM

Connected
on A Port

180 kΩ
NOM

A or B

R

(eq)

V

CC

Input

V

CC

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any bus terminal –7 V to 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Enable input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): D package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

p

p

12

Input voltage at any bus terminal (separately or common mode), V

I

or V

IC

–7

V

High-level input voltage, V

IH

D, DE, and RE 2 V

Low-level input voltage, V

IL

D, DE, and RE 0.8 V

Differential input voltage, VID (see Note 3) ±12 V

p

Driver –60 mA

High-level output current, I

OH

Receiver –400 µA

p

Driver 60

Low-level output current, I

OL

Receiver 8

mA

Operating free-air temperature, T

A

–25 85 °C

NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

SN65ALS1176
DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

†

MIN TYP

‡

MAX UNIT

V

IK

Input clamp voltage II = –18 mA –1.5 V

V

O

Output voltage IO = 0 0 6 V

|V

OD1

| Differential output voltage IO = 0 1.5 6 V

p

RL = 100 Ω, See Figure 1

1/2VOD 1 or 2

§

V

|V

OD2

|

Differential output voltage

RL = 54 Ω, See Figure 1 2.1 2.5 5 V

V

OD3

Differential output voltage V

test

= –7 V to 12 V, See Figure 2 1.5 5 V

∆ |VOD|

Change in magnitude of differential
output voltage

¶

±0.2 V

p

3

VOCCommon-mode output voltage

R

L

= 54 Ω or

100 Ω

,

See Figure 1

–1

V

∆ |VOC|

Change in magnitude of common-mode
output voltage

¶

±0.2 V

p

Outputs disabled,

VO = 12 V 1

IOOutput current

,

See Note 4

VO = –7 V –0.8

mA

I

IH

High-level input current VI = 2.4 V 20 µA

I

IL

Low-level input current VI = 0.4 V –400 µA

VO = –4 V –250

p

VO = 0 –150

IOSShort-circuit output current

#

VO = V

CC

250

mA

VO = 8 V 250

pp

Outputs enabled 23 30

ICCSupply current

No load

Outputs disabled 19 26

mA

†

The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.

‡

All typical values are at VCC = 5 V and TA = 25°C.

§

The minimum V

OD2

with a 100-Ω load is either 1/2 V

OD1

or 2 V, whichever is greater.

¶

∆ |VOD| and ∆ |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from one logic state to
the other.

#

Duration of the short circuit should not exceed one second for this test.

NOTE 4: This applies for both power on and power off; refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for

a combined driver and receiver terminal.

SN65ALS1176

DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

d(OD)

Differential output delay time

15 ns

t

sk(p)

Pulse skew

‡

RL = 54 Ω,

CL = 50 pF,

0 2 ns

t

t(OD)

Differential output transition time

See Figure 3

8 ns

t

PZH

Output enable time to high level

RL = 110 Ω,
See Figure 4

CL = 50 pF,

80 ns

t

PZL

Output enable time to low level

RL = 110 Ω,
See Figure 5

CL = 50 pF,

30 ns

t

PHZ

Output disable time from high level

RL = 110 Ω,
See Figure 4

CL = 50 pF,

50 ns

t

PLZ

Output disable time from low level

RL = 110 Ω,
See Figure 5

CL = 50 pF,

30 ns

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Pulse skew is defined as the |t

PLH

– t

PHL

| of each channel of the same device.

SYMBOL EQUIVALENTS

DATA-SHEET PARAMETER

TIA/EIA-422-B TIA/EIA-485-A

V

O

Voa, V

ob

Voa, V

ob

|V

OD1

| V

o

V

o

|V

OD2

| Vt (RL = 100 Ω) Vt (RL = 54 Ω)

|V

OD3

| None

Vt (test termination

measurement 2)

∆ |VOD| ||Vt| – |Vt|| ||Vt| – |Vt||

V

OC

|Vos| |Vos|

∆ |VOC| |Vos – Vos| |Vos – Vos|

I

OS

|Isa|, |Isb| None

I

O

|Ixa|, |Ixb| Iia, I

ib

SN65ALS1176
DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RECEIVER SECTION

electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN

TYP

†

MAX UNIT

V

IT+

Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V

V

IT–

Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2

‡

V

V

hys

Hysteresis voltage (V

IT+

– V

IT–

) 60 mV

V

IK

Enable-input clamp voltage II = –18 mA –1.5 V

p

V

= 200 mV , I

= –400 µA,

VOHHigh-level output voltage

ID

,

See Figure 6

OH

µ ,

2.7

V

p

V

= –200 mV, I

= 8 mA,

VOLLow-level output voltage

ID

,

See Figure 6

OL

,

0.45

V

I

OZ

High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA

p

Other input = 0 V ,

VI = 12 V 1

VILine input current

,

See Note 5

VI = –7 V –0.8

mA

I

IH

High-level-enable input current VIH = 2.7 V 20 µA

I

IL

Low-level-enable input current VIL = 0.4 V –100 µA

r

I

Input resistance 12 20 kΩ

I

OS

Short-circuit output current VID = 200 mV , VO = 0 –15 –85 mA

pp

Outputs enabled 23 30

ICCSupply current

No load

Outputs disabled 19 26

mA

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.

NOTE 5: This applies for both power on and power off. Refer to TIA/EIA-485-A for exact conditions.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

pd

Propagation time

V

= –1.5 V to 1.5 V, C

= 15 pF,

25 ns

t

sk(p)

Pulse skew

§

ID

,

See Figure 7

L

,

0 2 ns

t

PZH

Output enable time to high level 11 18 ns

t

PZL

Output enable time to low level

p

11 18 ns

t

PHZ

Output disable time from high level

C

L

= 15 pF,

See Figure 8

50 ns

t

PLZ

Output disable time from low level 30 ns

†

All typical values are at VCC = 5 V, TA = 25°C.

§

Pulse skew is defined as the |t

PLH

– t

PHL

| of each channel of the same device.

SN65ALS1176

DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

OD2

V

OC

R

L

2

R

L

2

Figure 1. Driver V

OD2

and VOC Test Circuit

V

OD3

V

test

375 Ω

375 Ω

60 Ω

Figure 2. Driver V

OD3

Test Circuit

TEST CIRCUIT VOLTAGE WAVEFORMS

3 V

0 V

≈ –2.5 V

50%

10%

t

t(OD)

t

t(OD)

t

d(ODL)

50%

10%

90%90%

1.5 V

t

d(ODH)

Output

Input

Output

3 V

50 Ω

RL = 54 Ω

≈2.5 V

Generator

(see Note B)

CL = 50 pF
(see Note A)

1.5 V

(see Note C)

(see Note C)

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

C. t

d(OD)

= t

d(ODH)

or t

d(ODL)

Figure 3. Driver Differential-Output Delay and Transition Times

SN65ALS1176
DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

TEST CIRCUIT VOLTAGE WAVEFORMS

1.5 V

V

OH

t

PHZ

t

PZH

0 V

3 V

1.5 V

2.3 V

Output

Input

Output

S1

0 V or 3 V

RL = 110 Ω

50 Ω

V

off

≈ 0 V

Generator

(see Note B)

CL = 50 pF

(see Note A)

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

0.5 V

Figure 4. Driver Enable and Disable Times

TEST CIRCUIT VOLTAGE WAVEFORMS

V

OL

t

PLZ

t

PZL

5 V

0.5 V

2.3 V

0 V

3 V

1.5 V1.5 V

5 V

Output

Input

Output

S1

RL = 110 Ω

CL = 50 pF

(see Note A)

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

0 V or 3 V

50 Ω

Generator

(see Note B)

Figure 5. Driver Enable and Disable Times

SN65ALS1176

DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

–I

OH

V

OH

+I

OL

V

OL

V

ID

Figure 6. Receiver VOH and VOL Test Circuit

TEST CIRCUIT VOLTAGE WAVEFORMS

V

OL

V

OH

3 V

0 V

t

PHL

t

PLH

Output

Input

1.5 V

1.3 V

51 Ω

Output

0 V

1.5 V
(see Note C)

(see Note C)

Generator

(see Note B)

CL = 15 pF

(see Note A)

1.5 V

1.3 V

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

C. tpd = t

PLH

or t

PHL

Figure 7. Receiver Propagation-Delay Times

SN65ALS1176
DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

TEST CIRCUIT

VOLTAGE WAVEFORMS

S3

1N916 or Equivalent5 kΩ

50 Ω

S1

1.5 V

–1.5 V

t

PZL

1.5 V

1.5 V

3 V

0 V

V

OL

S1 to – 1.5 V
S2 Closed
S3 Open

t

PZH

1.5 V

1.5 V
S3 Closed

S2 Open

S1 to 1.5 V

Input

0 V

3 V

Output

0 V

V

OH

V

OL

0.5 V

1.5 V

0 V

3 V

S1 to – 1.5 V
S2 Closed
S3 Closed

t

PLZ

V

OH

t

PHZ

S3 Closed

S2 Closed

S1 to 1.5 V

3 V

0 V

0.5 V

Input

Output

≈1.3 V

Input

Output

Input

Output

≈4.5 V

≈1.3 V

2 kΩ

Generator

(see Note B)

1.5 V

NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,

ZO=50Ω.

S2

5 V

Output

Figure 8. Receiver Output Enable and Disable Times

SN65ALS1176

DIFFERENTIAL BUS TRANSCEIVER

SLLS295A – APRIL 1998 – REVISED DECEMBER 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Transceivers

Up to 53

• • •

R

T

R

T

NOTE A: The line should terminate at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short

as possible.

Figure 9. Typical Application Circuit

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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated