Texas Instruments SN54CDC586WD, SNJ54CDC586WD Datasheet

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low Output Skew for Clock-Distribution
and Clock-Generation Applications

D

Operates at 3.3-V V

CC

D

Distributes One Clock Input to Twelve
Outputs

D

Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency

D

No External RC Network Required

D

External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input

D

Application for Synchronous DRAM,
High-Speed Microprocessor

D

TTL-Compatible Inputs and Outputs

D

Outputs Drive Parallel 50-Ω Terminated
Transmission Lines

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Distributed VCC and Ground Pins Reduce
Switching Noise

D

Packaged in 56-Pin Ceramic Flat Package

description

The SN54CDC586 is a high-performance,
low-skew, low-jitter clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the clock output signals to
the clock input (CLKIN) signal. It is specifically
designed for use with popular microprocessors
operating at speeds from 50 MHz to 100 MHz, or
down to 25 MHz on outputs configured as
half-frequency outputs. The SN54CDC586
operates at 3.3-V V

CC

and is designed to drive a

properly terminated 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN. One of

the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input
and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input.

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs
(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN
frequency , depending on which pin is fed back to FBIN (see Tables 1 and 2). All output-signal duty cycles are
adjusted to 50%, independent of the duty cycle at CLKIN.

NC

AV

CC

AGND

FBIN

AGND

SEL0
SEL1

GND
GND

1Y1

V

CC

GND

1Y2

V

CC

GND

1Y3

V

CC

GND
GND

2Y1

V

CC

GND

2Y2

V

CC

GND

2Y3

V

CC

NC

NC
CLKIN
NC
AV

CC

OE
TEST
CLR
V

CC

4Y3
GND
V

CC

4Y2
GND
V

CC

4Y1
GND
GND
V

CC

3Y3
GND
V

CC

3Y2
GND
V

CC

3Y1
GND
GND
NC

WD PACKAGE

(TOP VIEW)

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56
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48
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NC – No internal connection

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.
When OE

is low, the outputs are active. CLR is negative-edge triggered and can be used to reset the outputs
operating at half frequency . TEST is used for factory testing of the device and can be used to bypass the PLL.
TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the SN54CDC586 does not require external RC networks. The loop filter
for the PLL is included on chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the SN54CDC586 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon change of the select inputs, enabling of the PLL via TEST , and upon
enable of all outputs via OE

.

The SN54CDC586 is characterized for operation over the full military temperature range of –55°C to 125°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the SN54CDC586 PLL has a frequency range of 100 MHz to
200 MHz, twice the operating frequency range of the SN54CDC586 outputs. The output of the VCO is divided
by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO
frequency. SEL0 and SEL1 select which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency and phase of this output match that of CLKIN. In the case in which a VCO/2 output is wired to FBIN,
the VCO must operate at twice the CLKIN frequency , resulting in device outputs that operate at either the same
or one-half the CLKIN frequency . If a VCO/4 output is wired to FBIN, the device outputs operate at twice or the
same frequency as the CLKIN frequency.

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

output configuration A

Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2x outputs operate at one-half the CLKIN frequency, while outputs configured as 1x outputs
operate at the same frequency as CLKIN.

Table 1. Output Configuration A

INPUTS

OUTPUTS

SEL1 SEL0

1/2X

FREQUENCY1XFREQUENCY

L L None All
L H 1Yn 2Yn, 3Yn, 4Yn
H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

output configuration B

Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.

Table 2. Output Configuration B

INPUTS

OUTPUTS

SEL1 SEL0

1X

FREQUENCY2XFREQUENCY

L L All None
L H 1Yn 2Yn, 3Yn, 4Yn

H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

SN54CDC586

3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS

SGBS311 – FEBRUAR Y 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Phase-Lock Loop

One of Three Identical

Outputs – 1Yn

One of Three Identical

Outputs – 2Yn

One of Three Identical

Outputs – 3Yn

One of Three Identical

Outputs – 4Yn

CLR

CLKIN

TEST

SEL1

SEL0

FBIN

OE

Select

Logic

1Y1–1Y3

2Y1–2Y3

3Y1–3Y3

4Y1–4Y3

CLR

B

2

52

50

4

55

51

6

7

B

2

10, 13, 16

20, 23, 26

32, 35, 38

42, 45, 48