Texas Instruments SN54AS825AJT, SN74AS825ANT, SN74AS825ADW, SN74AS825ADWR, SNJ54AS825AFK Datasheet
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SN54AS825A . . . JT PACKAGE
SN74AS825A . . . DW OR NT PACKAGE
(TOP VIEW)
SN54AS825A . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE1
OE2
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
V
CC
OE3
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLKEN
CLK
NC – No internal connection
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
2Q
3Q
4Q
NC
5Q
6Q
7Q
2D
3D
4D
NC
5D
6D
7D
426
14 15 16 17 18
8D
CLR
GND
NC
CLK
CLKEN
8Q
1D
OE2
OE1NCOE3
1Q
V
CC
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Functionally Equivalent to AMD’s AM29825
• Improved I
OH
Specifications
• Multiple Output Enables Allow Multiuser
Control of the Interface
• Outputs Have Undershoot-Protection
Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce dc
Loading Effects
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. These devices
are particularly suitable for implementing
multiuser registers, I/O ports, bidirectional bus
drivers, and working registers.
With the clock-enable (CLKEN
) input low, the
eight D-type edge-triggered flip-flops enter data
on the low-to-high transitions of the clock (CLK)
input. Taking CLKEN
high disables the clock
buffer, latching the outputs. These devices have
noninverting data (D) inputs. Taking the clear
(CLR
) input low causes the eight Q outputs to go
low independently of the clock.
Multiuser buffered output-enable (OE1
, OE2, and
OE3
) inputs can be used to place the eight outputs
in either a normal logic state (high or low logic
level) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The highimpedance state and increased drive provide the
capability to drive bus lines without interface or
pullup components.
The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
The SN54AS825A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AS825A is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE†CLR CLKEN CLK D
Q
L L X X X L
L HL↑HH
LHL↑LL
LHHXX Q
0
HXXXX Z
†
OE
= H if any of OE1, OE2, or OE3 are high.
OE
= L if all of OE1, OE2, or OE3 are low.
logic symbol
‡
23
8
6D
9
7D
10
8D
2D
3
1D
6Q
17
7Q
16
8Q
15
1Q
22
4
2D
5
3D
6
4D
7
5D
2Q
21
3Q
20
4Q
19
5Q
18
OE3
13
CLK
1C2
R
11
CLR
G1
14
CLKEN
2
OE2
1
OE1
EN
&
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
SN54AS825A, SN74AS825A
8-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SDAS020B – JUNE 1984 – REVISED AUGUST 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
To Seven Other Channels
22
3
1
1D
1Q
R
C1
1D
CLKEN
CLK
11
14
13
OE1
CLR
OE2
OE3
2
23
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54AS825A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74AS825A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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