Texas Instruments SN54ALS569AJ, SN74ALS568AN, SN74ALS569ADW, SN74ALS569ADWR, SN74ALS569AN Datasheet
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SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
• 3-State Q Outputs Drive Bus Lines Directly
• Counter Operation Independent of 3-State
Output
• Fully Synchronous Clear, Count, and Load
• Asynchronous Clear Is Also Provided
• Fully Cascadable
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
The SN74ALS568A decade counter and
′ALS569A binary counters are programmable,
count up or down, and offer both synchronous and
asynchronous clearing. All synchronous functions
are executed on the positive-going edge of the
clock (CLK) input.
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR
synchronous clear (SCLR
clearing overrides all other functions of the device,
while synchronous clearing overrides only the
other synchronous functions. Data is loaded from
the A, B, C, and D inputs by holding load (LOAD
low during a positive-going clock transition. The
counting function is enabled only when enable P
(ENP
) and enable T (ENT) are low and ACLR,
SCLR
, and LOAD are high. The up/down (U/D)
input controls the direction of the count. These
counters count up when U/D
down when U/D
is low.
). Asynchronous (direct)
is high and count
) or
SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE
SN54ALS569A ...J PACKAGE
(TOP VIEW)
U/D
1
CLK
2
A
3
B
4
C
5
D
6
ENP
7
ACLR
SCLR
GND
SN54ALS569A . . . FK PACKAGE
B
C
D
ENP
ACLR
8
9
10
(TOP VIEW)
A
CLK
3212019
4
5
6
7
8
910111213
U/D
20
19
18
17
16
15
14
13
12
11
V
V
RCO
CCO
OE
Q
Q
Q
Q
ENT
LOAD
CC
18
17
16
15
14
CC
A
B
C
D
CCO
OE
Q
A
Q
B
Q
C
)
D
Q RCO
ENT
GND
SCLR
LOAD
A high level at the output-enable (OE
enables those outputs. Counting is independent of OE
(RCO
) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum
(9 or 15) when counting up. The clocked carry output (CCO
that of the low level of the clock when RCO
otherwise, CCO
is high. CCO does not have the glitches commonly associated with a ripple-carry output.
Cascading is normally accomplished by connecting RCO
However, for very high-speed counting, RCO
) input forces the Q outputs into the high-impedance state, and a low level
. ENT is fed forward to enable the ripple-carry output
) produces a low-level pulse for a duration equal to
is low and the counter is enabled (both ENP and ENT are low);
or CCO of the first counter to ENT of the next counter.
should be used for cascading since CCO does not become active
until the clock returns to the low level.
The SN54ALS569A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN54ALS569A, SN74ALS568A, SN74ALS569A
OPERATION
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
FUNCTION TABLE
INPUTS
OE ACLR SCLR LOAD ENT ENP U/D CLK
H X X X X X X X Q outputs disabled
L L X X X X X X Asynchronous clear
L HLXXXX↑Synchronous clear
L HHLXXX↑ Load
L HHHLLH↑ Count up
L HHHLLL↑ Count down
L H H H H X X X Inhibit count
L H H H X H X X Inhibit count
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
logic symbols
†
SN74ALS568A
CTRDIV10
EN10
M1 [UP]
M2 [DOWN]
C5/1,4,7,8,+/2,4,7,8–
Z6
G7
G8
5CT=0
M3 [LOAD]
M4 [COUNT]
CT=0
3,5D
1,7 (CT=9) G9
2,7 (CT=0) G9
′ALS569A
6,7,8,9
10
18
19
16
15
14
13
CCO
RCO
Q
A
Q
B
Q
C
Q
D
OE
U/D
CLK
ENT
ENP
SCLR
LOAD
ACLR
17
1
2
12
7
9
11
8
3
A
4
B
5
C
6
D
17
OE
1
U/D
2
CLK
12
ENT
7
ENP
SCLR
LOAD
ACLR
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
9
11
8
3
A
4
B
5
C
6
D
CTRDIV16
EN10
M1 [UP]
M2 [DOWN]
C5/1,4,7,8,+/2,4,7,8–
Z6
G7
G8
5CT=0
M3 [LOAD]
M4 [COUNT]
CT=0
3,5D
1,7 (CT=15) G9
2,7 (CT=0) G9
6,7,8,9
10
18
19
16
15
14
13
CCO
RCO
Q
A
Q
B
Q
C
Q
D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ALS569A, SN74ALS568A, SN74ALS569A
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
WITH 3-STATE OUTPUTS
SDAS229A – APRIL 1982 – REVISED JANUARY 1995
logic diagrams (positive logic)
SN74ALS568A
17
OE
1
U/D
2
CLK
12
ENT
7
ENP
SCLR
9
18
19
CCO
RCO
LOAD
ACLR
11
8
3
A
C1
1D
R
4
B
C1
1D
R
5
C
C1
1D
R
16
15
14
Q
A
Q
B
Q
C
6
D
C1
1D
R
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
Q
D
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