TEXAS INSTRUMENTS SN54ALS541 Technical data

SN54ALS541, SN74ALS540, SN74ALS541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

D

3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers

D

pnp Inputs Reduce dc Loading

D

Data Flowthrough Pinout (All Inputs on
Opposite Side From Outputs)

description

These octal buffers and line drivers are designed
to have the performance of the popular
SN54ALS240A/SN74ALS240A series and, at
the same time, offer a pinout with inputs and
outputs on opposite sides of the package. This
arrangement greatly facilitates printed circuit
board layout.

The 3-state control gate is a 2-input NOR gate
such that, if either output-enable (OE1
input is high, all eight outputs are in the
high-impedance state.

The SN74ALS540 provides inverted data. The
’ALS541 provide true data at the outputs.

The -1 versions of SN74ALS540 and
SN74ALS541 are identical to the standard
versions, except that the recommended
maximum I

-1 version of the SN54ALS541.

is increased to 48 mA. There is no

OL

or OE2)

SN54ALS541 ...J PACKAGE

SN74ALS540 ...DW, N, OR NS PACKAGE

SN74ALS541 . . . DB, DW, N, OR NS PACKAGE

SN54ALS541 . . . FK PACKAGE

A3
A4
A5
A6
A7

(TOP VIEW)

OE1

1

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

GND

10

(TOP VIEW)

A2A1OE1

3212019

4
5
6
7
8

910111213

A8

Y8

20
19
18
17
16
15
14
13
12
11

V

CC

Y7

V

CC

OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8

OE2

18
17
16
15
14

Y6

Y1
Y2
Y3
Y4
Y5

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54ALS541, SN74ALS540, SN74ALS541

PDIP

N

Tube

ALS540

ALS541

ALS541-1

SOP

NS

SSOP

DB

Tape and reel

55°C to 125°C

OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

ORDERING INFORMATION

T

A

SOIC – DW

0°C to 70°C

°

–

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.

CDIP – J Tube SNJ54ALS541J SNJ54ALS541J

°

LCCC – FK Tube SNJ54ALS541FK SNJ54ALS541FK

–

–

–

PACKAGE

Tube SN74ALS540DW
Tape and reel SN74ALS540DWR
Tube SN74ALS540-1DW ALS540-1
Tube SN74ALS541DW
Tape and reel SN74ALS541DWR
Tube SN74ALS541-1DW
Tape and reel SN74ALS541-1DWR
Tape and reel SN74ALS540NSR ALS540

Tape and reel

†

p

ORDERABLE

PART NUMBER

SN74ALS540N SN74ALS540N
SN74ALS540-1N SN74ALS540-1N
SN74ALS541N SN74ALS541N
SN74ALS541-1N SN74ALS541-1N

SN74ALS540-1NSR ALS540-1
SN74ALS541NSR ALS541
SN74ALS541-1NSR ALS541-1
SN74ALS541DBR G541
SN74ALS541-1DBR G541-1

TOP-SIDE

MARKING

logic diagrams (positive logic)

SN74ALS540 ′ALS541

1

OE1

19

OE2

2

A1

To Seven Other Channels

18

Y1

OE1
OE2

A1

1
19

2

18

Y1

To Seven Other Channels

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IOLLow-level output current

mA

SN54ALS541, SN74ALS540, SN74ALS541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V
Input voltage, V

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 1): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

SN74ALS540
SN74ALS541

48

UNIT

†

V

CC

V

IH

V

IL

I

OH

T

A

†

Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V

Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.7 0.8 V
High-level output current –12 –15 mA

p

Operating free-air temperature –55 125 0 70 °C

SN54ALS541

MIN NOM MAX MIN NOM MAX

12 24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ALS541, SN74ALS540, SN74ALS541

V

V

I

mA

A

Y

ns

OE

Y

ns

OE

Y

ns

OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS

V

IK

OH

V

OL

I

OZH

I

OZL

I

I

I

IH

I

IL

§

I

O

SN74ALS540 VCC = 5.5 V

CC

’ALS541 VCC = 5.5 V

†

Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2

IOH = –3 mA 2.4 3.2 2.4 3.2

VCC = 4.5 V

VCC = 4.5 V

VCC = 5.5 V, VO = 2.7 V 20 20 µA
VCC = 5.5 V, VO = 0.4 V –20 –20 µA
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.4 V –0.2 –0.1 mA
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA

IOH = –12 mA 2
IOH = –15 mA 2
IOL = 12 mA 0.25 0.4 0.25 0.4
IOL = 24 mA 0.35 0.5
IOL = 48 mA

Outputs high 5 10
Outputs low 13 22
Outputs disabled 11 19
Outputs high 6 14 6 14
Outputs low 15 25 15 25
Outputs disabled 13.5 32 13.5 22

†

SN54ALS541

MIN TYP‡MAX MIN TYP‡MAX

SN74ALS540
SN74ALS541

0.35 0.5

UNIT

V

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

¶

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

PLZ

FROM

(INPUT)

TO

(OUTPUT)

SN54ALS541 SN74ALS540 SN74ALS541

MIN MAX MIN MAX MIN MAX

R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX

4 17 2 12 4 14
2 14 2 9 2 10
5 18 5 15 5 15
8 28 8 20 8 20
1 12 1 10 1 10
2 14 2 12 2 12

¶

UNIT

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

SN54ALS541, SN74ALS540, SN74ALS541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7 V

V

CC

S1

R

L

Test
Point

C

L

R

L

From Output

Under Test

C

(see Note A)

Test
Point

L

From Output

Under Test

(see Note A)

R1

C

L

RL = R1 = R2

Test
Point

R2

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

Timing

Input

t

su

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

t

PZL

t

PZH

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

1.3 V

t

PHZ

1.3 V

1.3 V

t

1.3 V1.3 V

1.3 V1.3 V

FOR OPEN-COLLECTOR OUTPUTS

h

t

PLZ

LOAD CIRCUIT

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

≈3.5 V

V

OL

0.3 V

V

OH

0.3 V

≈0 V

High-Level

Low-Level

Out-of-Phase

(see Note C)

Pulse

Pulse

Input

In-Phase

Output

Output

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

t

PLH

t

PHL

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.3 V1.3 V

t

PHL

t

PLH

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

V

V

V

V

OH

OL

OH

OL

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5