TEXAS INSTRUMENTS SN54ALS541 Technical data

SN54ALS541, SN74ALS540, SN74ALS541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

D

3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

D

pnp Inputs Reduce dc Loading

D

Data Flowthrough Pinout (All Inputs on Opposite Side From Outputs)

description

These octal buffers and line drivers are designed to have the performance of the popular SN54ALS240A/SN74ALS240A series and, at the same time, offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.

The 3-state control gate is a 2-input NOR gate such that, if either output-enable (OE1 input is high, all eight outputs are in the high-impedance state.

The SN74ALS540 provides inverted data. The ’ALS541 provide true data at the outputs.

The -1 versions of SN74ALS540 and SN74ALS541 are identical to the standard versions, except that the recommended maximum I

-1 version of the SN54ALS541.

is increased to 48 mA. There is no

OL

or OE2)

SN54ALS541 ...J PACKAGE

SN74ALS540 ...DW, N, OR NS PACKAGE

SN74ALS541 . . . DB, DW, N, OR NS PACKAGE

SN54ALS541 . . . FK PACKAGE

A3 A4 A5 A6 A7

(TOP VIEW)

OE1

1

A1

2

A2

3

A3

4

A4

5

A5

6

A6

7

A7

8

A8

9

GND

10

(TOP VIEW)

A2A1OE1

3212019

4 5 6 7 8

910111213

A8

Y8

20 19 18 17 16 15 14 13 12 11

V

CC

Y7

V

CC

OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

OE2

18 17 16 15 14

Y6

Y1 Y2 Y3 Y4 Y5

GND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

1

SN54ALS541, SN74ALS540, SN74ALS541

PDIP

N

Tube

ALS540

ALS541

ALS541-1

SOP

NS

SSOP

DB

Tape and reel

55°C to 125°C

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

ORDERING INFORMATION

T

A

SOIC – DW

0°C to 70°C

°

–

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.

CDIP – J Tube SNJ54ALS541J SNJ54ALS541J

°

LCCC – FK Tube SNJ54ALS541FK SNJ54ALS541FK

–

PACKAGE

Tube SN74ALS540DW Tape and reel SN74ALS540DWR Tube SN74ALS540-1DW ALS540-1 Tube SN74ALS541DW Tape and reel SN74ALS541DWR Tube SN74ALS541-1DW Tape and reel SN74ALS541-1DWR Tape and reel SN74ALS540NSR ALS540

Tape and reel

†

p

ORDERABLE

PART NUMBER

SN74ALS540N SN74ALS540N SN74ALS540-1N SN74ALS540-1N SN74ALS541N SN74ALS541N SN74ALS541-1N SN74ALS541-1N

SN74ALS540-1NSR ALS540-1 SN74ALS541NSR ALS541 SN74ALS541-1NSR ALS541-1 SN74ALS541DBR G541 SN74ALS541-1DBR G541-1

TOP-SIDE

MARKING

logic diagrams (positive logic)

SN74ALS540 ′ALS541

1

OE1

19

OE2

2

A1

To Seven Other Channels

18

Y1

OE1 OE2

A1

1 19

2

18

Y1

To Seven Other Channels

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IOLLow-level output current

mA

SN54ALS541, SN74ALS540, SN74ALS541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V Input voltage, V

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 1): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

SN74ALS540 SN74ALS541

48

UNIT

†

V

CC

V

IH

V

IL

I

OH

T

A

†

Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V

Supply voltage 4.5 5 5.5 4.5 5 5.5 V High-level input voltage 2 2 V Low-level input voltage 0.7 0.8 V High-level output current –12 –15 mA

p

Operating free-air temperature –55 125 0 70 °C

SN54ALS541

MIN NOM MAX MIN NOM MAX

12 24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ALS541, SN74ALS540, SN74ALS541

V

I

mA

A

Y

ns

OE

Y

ns

OE

Y

ns

OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

V

IK

OH

V

OL

I

OZH

I

OZL

I

IH

I

IL

§

I

O

SN74ALS540 VCC = 5.5 V

CC

’ALS541 VCC = 5.5 V

†

Applies only to the -1 version and only if VCC is between 4.75 V and 5.25 V

‡

All typical values are at VCC = 5 V, TA = 25°C.

§

The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2

IOH = –3 mA 2.4 3.2 2.4 3.2

VCC = 4.5 V

VCC = 5.5 V, VO = 2.7 V 20 20 µA VCC = 5.5 V, VO = 0.4 V –20 –20 µA VCC = 5.5 V, VI = 7 V 0.1 0.1 mA VCC = 5.5 V, VI = 2.7 V 20 20 µA VCC = 5.5 V, VI = 0.4 V –0.2 –0.1 mA VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA

IOH = –12 mA 2 IOH = –15 mA 2 IOL = 12 mA 0.25 0.4 0.25 0.4 IOL = 24 mA 0.35 0.5 IOL = 48 mA

Outputs high 5 10 Outputs low 13 22 Outputs disabled 11 19 Outputs high 6 14 6 14 Outputs low 15 25 15 25 Outputs disabled 13.5 32 13.5 22

†

SN54ALS541

MIN TYP‡MAX MIN TYP‡MAX

SN74ALS540 SN74ALS541

0.35 0.5

UNIT

V

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V, CL = 50 pF,

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

¶

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

PLZ

FROM

(INPUT)

TO

(OUTPUT)

SN54ALS541 SN74ALS540 SN74ALS541

MIN MAX MIN MAX MIN MAX

R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX

4 17 2 12 4 14 2 14 2 9 2 10 5 18 5 15 5 15 8 28 8 20 8 20 1 12 1 10 1 10 2 14 2 12 2 12

¶

UNIT

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

(see Note A)

SN54ALS541, SN74ALS540, SN74ALS541

OCTAL BUFFERS AND LINE DRIVERS

WITH 3-STATE OUTPUTS

SDAS025D – APRIL 1982 – REVISED MARCH 2002

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7 V

V

CC

S1

R

L

Test Point

C

L

R

L

From Output

Under Test

C

(see Note A)

Test Point

L

From Output

Under Test

(see Note A)

R1

C

L

RL = R1 = R2

Test Point

R2

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

Timing

Input

t

su

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

t

PZL

t

PZH

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

1.3 V

t

PHZ

1.3 V

t

1.3 V1.3 V

FOR OPEN-COLLECTOR OUTPUTS

h

t

PLZ

LOAD CIRCUIT

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

≈3.5 V

V

OL

0.3 V

V

OH

0.3 V

≈0 V

High-Level

Low-Level

Out-of-Phase

(see Note C)

Pulse

Input

In-Phase

Output

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

t

PLH

t

PHL

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.3 V1.3 V

t

PHL

t

PLH

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

V

OH

OL

OH

OL

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-89602012A ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC 5962-8960201RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC 5962-8960201SA OBSOLETE CFP W 20 TBD Call TI Call TI

SN54ALS541J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

SN74ALS540-1DW ACTIVE SOIC DW 20 25 Pb-Free

SN74ALS540-1DWE4 ACTIVE SOIC DW 20 25 Pb-Free

SN74ALS540-1DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI

SN74ALS540-1N ACTIVE PDIP N 20 20 Pb-Free

SN74ALS540-1NE4 ACTIVE PDIP N 20 20 Pb-Free

SN74ALS540-1NSR ACTIVE SO NS 20 2000 Pb-Free

SN74ALS540-1NSRE4 ACTIVE SO NS 20 2000 Pb-Free

SN74ALS540DW ACTIVE SOIC DW 20 25 Pb-Free

SN74ALS540DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &

SN74ALS540DWR ACTIVE SOIC DW 20 2000 Pb-Free

SN74ALS540DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &

SN74ALS540N ACTIVE PDIP N 20 20 Pb-Free

SN74ALS540N3 OBSOLETE PDIP N 20 TBD Call TI Call TI

SN74ALS540NE4 ACTIVE PDIP N 20 20 Pb-Free

SN74ALS540NSR ACTIVE SO NS 20 2000 Pb-Free

SN74ALS540NSRE4 ACTIVE SO NS 20 2000 Pb-Free

SN74ALS541-1DBR ACTIVE SSOP DB 20 2000 Pb-Free

SN74ALS541-1DBRE4 ACTIVE SSOP DB 20 2000 Pb-Free

SN74ALS541-1DW ACTIVE SOIC DW 20 25 Pb-Free

SN74ALS541-1DWE4 ACTIVE SOIC DW 20 25 Pb-Free

SN74ALS541-1DWR ACTIVE SOIC DW 20 2000 Pb-Free

SN74ALS541-1DWRE4 ACTIVE SOIC DW 20 2000 Pb-Free

SN74ALS541-1N ACTIVE PDIP N 20 20 Pb-Free

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-260C-1 YEAR/

CU NIPDAU Level-2-250C-1 YEAR/

CU NIPDAU Level-NC-NC-NC

Level-1-235C-UNLIM

8-Jun-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

SN74ALS541-1NE4 ACTIVE PDIP N 20 20 Pb-Free

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

8-Jun-2005

(3)

(RoHS)

SN74ALS541-1NSR ACTIVE SO NS 20 2000 Pb-Free

(RoHS)

SN74ALS541-1NSRE4 ACTIVE SO NS 20 2000 Pb-Free

(RoHS)

SN74ALS541DBR ACTIVE SSOP DB 20 2000 Pb-Free

(RoHS)

SN74ALS541DBRE4 ACTIVE SSOP DB 20 2000 Pb-Free

(RoHS)

SN74ALS541DW ACTIVE SOIC DW 20 25 Pb-Free

(RoHS)

SN74ALS541DWR ACTIVE SOIC DW 20 2000 Pb-Free

(RoHS)

SN74ALS541DWRE4 ACTIVE SOIC DW 20 2000 Pb-Free

(RoHS)

SN74ALS541N ACTIVE PDIP N 20 20 Pb-Free

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-NC-NC-NC

(RoHS)

SN74ALS541N3 OBSOLETE PDIP N 20 TBD Call TI Call TI

SN74ALS541NE4 ACTIVE PDIP N 20 20 Pb-Free

CU NIPDAU Level-NC-NC-NC

(RoHS)

SN74ALS541NSR ACTIVE SO NS 20 2000 Pb-Free

(RoHS)

SN74ALS541NSRE4 ACTIVE SO NS 20 2000 Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

SNJ54ALS541FK ACTIVE LCCC FK 20 1 TBD Call TI Level-NC-NC-NC

SNJ54ALS541J ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

8-Jun-2005

Addendum-Page 3

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

19

20

22

23

24

25

21

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342 (8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358

(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307 (7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850 (21,6)

1.047 (26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358 (9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858 (21,8)

1.063 (27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

28

1

2,00 MAX

0,38 0,22

15

14

A

0,05 MIN

0,15

5,60 5,00

M

8,20 7,40

Seating Plane

0,10

0,25 0,09

0°–ā8°

Gage Plane

0,25

0,95 0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

14

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TEXAS INSTRUMENTS SN54ALS541 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual