Texas Instruments SN54ALS352J, SNJ54ALS352FK, SNJ54ALS352J Datasheet
SN54ALS352, SN74ALS352
DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SDAS221A – APRIL 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Inverting Versions of the ′ALS153
• Permit Multiplexing From n Lines to
One Line
• Perform Parallel-to-Serial Conversion
• Strobe (Enable) Line Provided for
Cascading (n Lines to n Lines)
• T ypical Power Per Multiplexer Is 16 mW
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These data selectors/multiplexers contain
inverters and drivers to supply fully
complementary binary decoding data selection to
the AND-OR-invert gates. Separate strobe (G
)
inputs are provided for each of the two 4-line
sections.
The SN54ALS352 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS352 is characterized for
operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
SELECT DATA
STROBE
OUTPUT
B A C0 C1 C2 C3
G
Y
X X X X X X H H
L LLXXX L H
LLHXXX L L
LHXLXX L H
LHXHXX L L
HLXXLX L H
HLXXHX L L
HHXXXL L H
HHXXXH L L
Select inputs A and B are common to both sections.
SN54ALS352 ...J PACKAGE
SN74ALS352 ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
A
2C3
NC
2C2
2C1
1C3
1C2
NC
1C1
1C0
SN54ALS352 . . . FK PACKAGE
(TOP VIEW)
B1GNC
2Y
2C0
2G
1Y
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1G
B
1C3
1C2
1C1
1C0
1Y
GND
V
CC
2G
A
2C3
2C2
2C1
2C0
2Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS352, SN74ALS352
DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
SDAS221A – APRIL 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
G
MUX
0
3
0
14
A
1
2
B
EN
1
15
1Y
7
0
6
1C0
1
5
1C1
2
4
1C2
3
3
1C3
10
2C0
11
2C1
12
2C2
13
2C3
2Y
9
1G
2G
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
Data 2
Select
Data 1
2G
2C3
2C2
2C1
2C0
A
B
1C3
1C2
1C1
1C0
1G
1Y
1
6
5
4
3
2
14
10
11
12
13
15
7
2Y
9
Pin numbers shown are for the D, J, and N packages.
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