Texas Instruments SN10KHT5541DW, SN10KHT5541DWR, SN10KHT5541NT Datasheet

SN10KHT5541

OCTAL ECL-TO-TTL TRANSLATOR

WITH 3-STATE OUTPUTS

SDZS003A – OCTOBER 1989 – REVISED OCTOBER 1990

Copyright  1990, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• 10KH Compatible

• ECL and TTL Control Inputs

• Noninverting Outputs

• Flow-Through Architecture Optimizes PCB

Layout

• Center Pin V

CC

, VEE, and GND
Configurations Minimize High-Speed
Switching Noise

• Package Options Include “Small Outline”

Packages and Standard Plastic 300-mil
DIPs

description

This octal ECL-to-TTL translator is designed to
provide a efficient translation between a 10KH
ECL signal environment and a TTL signal
environment. This device is designed specifically
to improve the performance and density of
ECL-to-TTL CPU/bus-oriented functions such as
memory-address drivers, clock drivers, and
bus-oriented receivers and transmitters.

Two output-enable pins, OE

1 and OE2, are
provided. These control inputs are ANDed
together with OE

1 being ECL compatible and OE2
being TTL compatible. This offers the choice of
controlling the outputs of the device from either a
TTL or ECL signal environment.

The SN10KHT5541 is characterized for operation
from 0°C to 75°C.

FUNCTION TABLE

OUTPUT

DATA OUTPUT

ENABLE INPUT (TTL)

OE1 OE2 A Y

X H X Z
H X X Z
L L L L
L L H H

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

Y1
Y2
Y3
Y4

V

CC

GND
GND
GND

Y5
Y6
Y7
Y8

A1
A2
A3
A4
OE

2 (TTL)

V

EE

GND
OE

1 (ECL)
A5
A6
A7
A8

DW OR NT PACKAGE

(T0P VIEW)

logic symbol

†

3
4

&

9

11
12

15
14

13

16

17

EN

2

Y1A1
A2
A3

A4
A5
A6

A7
A8

24
23

22
21

Y2

Y3

Y4

Y5

Y6

Y7

Y8

1

10

OE2

OE1

20

ECL/

TTL

ECL/

TTL

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN10KHT5541
OCTAL ECL-TO-TTL TRANSLATOR
WITH 3-STATE OUTPUTS

SDZS003A – OCTOBER 1989 – REVISED OCT OBER 1990

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

A1

A2

A3

A4

A5

A6

A7

A8

OE1 (ECL)

OE2 (TTL)

24

23

22

21

17
20

16

15

14

13

1

2

3

4

9

10

11

12

ECL/TTL

ECL/TTL

ECL/TTL

ECL/TTL

ECL/TTL

ECL/TTL

ECL/TTL

ECL/TTL

ECL/TTL

SN10KHT5541

OCTAL ECL-TO-TTL TRANSLATOR

WITH 3-STATE OUTPUTS

SDZS003A – OCTOBER 1989 – REVISED OCTOBER 1990

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage, V

EE

–8 V to 0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (TTL) (see Note 1) –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (ECL) V

EE

to 0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any output in the high state –0.5 V to V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current (TTL) –30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

TTL supply voltage 4.5 5 5.5 V

V

EE

ECL supply voltage –4.94 –5.2 –5.46 V

V

IH

TTL high-level input voltage 2 V

V

IL

TTL low-level input voltage 0.8 V

TA = 0°C –1170 –840

V

IH

‡

ECL high-level input voltage TA = 25°C –1130 –810 mV

TA = 75°C –1070 –735
TA = 0°C –1950 –1480

V

IL

‡

ECL low-level input voltage TA = 25°C –1950 –1480 mV

TA = 75°C –1950 –1450

I

IK

TTL input clamp current –18 mA

I

OH

High-level output current –15 mA

I

OL

Low-level output current 48 mA

T

A

Operating free-air temperature 0 75 °C

‡

The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.

V

OH

V

UNITPARAMETER

A

OE

1

OE

1

OE

2

OE

2

Y

Y

Y

Y

Y

ns

ns

ns

ns

ns

SN10KHT5541
OCTAL ECL-TO-TTL TRANSLATOR
WITH 3-STATE OUTPUTS

SDZS003A – OCTOBER 1989 – REVISED OCT OBER 1990

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

OE2 only VCC = 4.5 V, VEE = –4.94 V, II = –18 mA –1.2 V

I

I

OE2 only VCC = 5.5 V, VEE = –5.46 V, VI = 7 V 0.1 mA

I

IH

OE2 only VCC = 5.5 V, VEE = –5.46 V, VI = 2.7 V 20 µA

I

IL

OE2 only VCC = 5.5 V, VEE = –5.46 V, VI = 0.5 V –0.5 mA

VCC = 5.5 V, VEE = –5.46 V, VI = –840 mV TA = 0°C 350

I

IH

Data inputs and OE1 VCC = 5.5 V, VEE = –5.46 V, VI = –810 mV TA = 25°C 350 µA

VCC = 5.5 V, VEE = –5.46 V, VI = –735 mV TA = 75°C 350

TA = 0°C 0.5

I

IL

Data inputs and OE1 VCC = 5.5 V, VEE = –5.46 V, VI = –1950 mV TA = 25°C 0.5 µA

TA = 75°C 0.5
VCC = 4.5 V, VEE = –5.2 V ± 5%, IOH = –3 mA 2.4 3.3
VCC = 4.5 V, VEE = –5.2 V ± 5%, IOH = –15 mA 2 3.1

V

OL

VCC = 4.5 V, VEE = –5.2 V ± 5%, IOL = 48 mA 0.38 0.55 V

I

OZH

VCC = 5.5 V, VEE = –5.46 V, VO = 2.7 V 50 µA

I

OZL

VCC = 5.5 V, VEE = –5.46 V, VO = 0.5 V –50 µA

I

OS

‡

VCC = 5.5 V, VEE = –5.46 V, VO = 0 –100 –225 mA

I

CCH

VCC = 5.5 V, VEE = –5.46 V 64 97 mA

I

CCL

VCC = 5.5 V, VEE = –5.46 V 80 120 mA

I

CCZ

VCC = 5.5 V, VEE = –5.46 V 77 116 mA

I

EE

VCC = 5.5 V, VEE = –5.46 V –22 –33 mA

C

i

VCC = 5 V, VEE = –5.2 V 5 pF

C

o

VCC = 5 V, VEE = –5.2 V 7 pF

†

All typical values are at VCC = 5 V, VEE = –5.2 V, TA = 25°C.

‡

Not more than one output should be tested at a time and the duration of the test should not exceed 10 ms.

switching characteristics over recommended ranges of operating free-air temperature and supply
voltage (see Figure 1)

CL = 50 pF,

FROM TO R1 = 500 Ω,

(INPUT) (OUTPUT) R2 = 500 Ω

MIN TYP§MAX

t

PLH

1.7 4 6.2

t

PHL

1.6 4 6.2

t

PZH

2.6 4.7 6.7

t

PZL

3.2 5.9 8.5

t

PHZ

2.9 5.4 7.8

t

PLZ

1.9 4.9 7.8

t

PZH

1.7 4 6.2

t

PZL

2.5 5.1 7.7

t

PHZ

2.1 4.3 6.4

t

PLZ

1.1 3.7 6.3

§

All typical values are at VCC = 5 V, VEE = –5.2 V, TA = 25°C.

SN10KHT5541

OCTAL ECL-TO-TTL TRANSLATOR

WITH 3-STATE OUTPUTS

SDZS003A – OCTOBER 1989 – REVISED OCTOBER 1990

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

TEST

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

S1

Open
Open
Open

Closed

Open

Closed

SWITCH POSITION TABLE

LOAD CIRCUIT

t

PHL

t

PLH

ECL Input

(See Note B)

In-Phase

TTL Output

ECL- INPUT PROPAGATION DELAY TIMES

V

OH

V

OL

20%

–890 mV

–1690 mV

50%

t

PZL

t

PZH

50%

50%

t

PLZ

Output
Control

(Low-level

enabling)

(See Note B)

Output

Waveform 1

(See Note D)

Output

Waveform 2

(See Note D)

TTL ENABLE AND DISABLE TIMES

V

OL

3 V

1.5 V

1.5 V

t

PHZ

20%

3.5 V

0

t

PZL

t

PZH

t

PLZ

ECL ENABLE AND DISABLE TIMES

V

OL

t

PHZ

3.5 V

0

–1690 mV

ECL Output

Control

(Low-level

enabling

(See Note B)

Output

Waveform 1

(See Note D)

50%

50%

V

OH

V

OH

Output

Waveform 2

(See Note D)

S1

From Output

Under Test

Test

Point

R2

C

L

(See Note A)

R1

7 V

Open

0

–890 mV

VOL +0.3 V

VOH –0.3 V

VOL +0.3 V

VOH –0.3 V

50% 50%

t

f

t

r

80%80%

50%

1.5 V1.5

V

NOTES: A. CL includes probe and jig capacitance.

B. For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns,

tf ≤ 2.5 ns.

C. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 0.7 ns,

tf ≤ 0.7 ns.

D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. W aveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control.

E. The outputs are measured one at a time with one transition per measurement.

FIGURE 1. LOAD CIRCUIT AND VOLTAGE WAVEFORMS

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Copyright  1998, Texas Instruments Incorporated