Texas Instruments SN10KHT5541DW, SN10KHT5541DWR, SN10KHT5541NT Datasheet
SN10KHT5541
OCTAL ECL-TO-TTL TRANSLATOR
WITH 3-STATE OUTPUTS
SDZS003A – OCTOBER 1989 – REVISED OCTOBER 1990
Copyright 1990, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 10KH Compatible
• ECL and TTL Control Inputs
• Noninverting Outputs
• Flow-Through Architecture Optimizes PCB
Layout
• Center Pin V
CC
, VEE, and GND
Configurations Minimize High-Speed
Switching Noise
• Package Options Include “Small Outline”
Packages and Standard Plastic 300-mil
DIPs
description
This octal ECL-to-TTL translator is designed to
provide a efficient translation between a 10KH
ECL signal environment and a TTL signal
environment. This device is designed specifically
to improve the performance and density of
ECL-to-TTL CPU/bus-oriented functions such as
memory-address drivers, clock drivers, and
bus-oriented receivers and transmitters.
Two output-enable pins, OE
1 and OE2, are
provided. These control inputs are ANDed
together with OE
1 being ECL compatible and OE2
being TTL compatible. This offers the choice of
controlling the outputs of the device from either a
TTL or ECL signal environment.
The SN10KHT5541 is characterized for operation
from 0°C to 75°C.
FUNCTION TABLE
OUTPUT
DATA OUTPUT
ENABLE INPUT (TTL)
OE1 OE2 A Y
X H X Z
H X X Z
L L L L
L L H H
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Y1
Y2
Y3
Y4
V
CC
GND
GND
GND
Y5
Y6
Y7
Y8
A1
A2
A3
A4
OE
2 (TTL)
V
EE
GND
OE
1 (ECL)
A5
A6
A7
A8
DW OR NT PACKAGE
(T0P VIEW)
logic symbol
†
3
4
&
9
11
12
15
14
13
16
17
EN
2
Y1A1
A2
A3
A4
A5
A6
A7
A8
24
23
22
21
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
10
OE2
OE1
20
ECL/
TTL
ECL/
TTL
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN10KHT5541
OCTAL ECL-TO-TTL TRANSLATOR
WITH 3-STATE OUTPUTS
SDZS003A – OCTOBER 1989 – REVISED OCT OBER 1990
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
A8
OE1 (ECL)
OE2 (TTL)
24
23
22
21
17
20
16
15
14
13
1
2
3
4
9
10
11
12
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
Loading...