Texas Instruments MSP430G2744DA, MSP430G2744RHA, MSP430G2744YFF, PMS430G2744N User Manual
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MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
MSP430G2x44 Mixed-Signal Microcontrollers
1 Device Overview
1.1 Features
1
• Low Supply-Voltage Range: 1.8 V to 3.6 V • 10-Bit 200-ksps Analog-to-Digital Converter (ADC)
• Ultra-Low Power Consumption
– Active Mode: 270 µA at 1 MHz, 2.2 V
– Standby Mode: 1 µA
– Off Mode (RAM Retention): 0.1 µA
• Ultra-Fast Wakeup From Standby Mode in Less
Than 1 µs
• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle
Time
• Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With Four
Calibrated Frequencies
– Internal Very-Low-Power Low-Frequency (LF)
Oscillator
– 32-kHz Crystal
– High-Frequency (HF) Crystal up to 16 MHz
– Resonator
– External Digital Clock Source
– External Resistor
• 16-Bit Timer_A With Three Capture/Compare
Registers
• 16-Bit Timer_B With Three Capture/Compare
Registers
• Universal Serial Communication Interface (USCI)
– Enhanced UART Supports Automatic Baud-
Rate Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C
With Internal Reference, Sample-and-Hold,
Autoscan, and Data Transfer Controller
• Brownout Detector
• Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
• Bootstrap Loader (BSL)
• On-Chip Emulation Module
• Family Members
– MSP430G2444
• 8KB + 256B Flash Memory
• 512B RAM
– MSP430G2544
• 16KB + 256B Flash Memory
• 512B RAM
– MSP430G2744
• 32KB + 256B Flash Memory
• 1KB RAM
• Section 3 Summarizes the Available Family
Members
• Package Options
– TSSOP: 38 Pin (DA)
– QFN: 40 Pin (RHA)
– DSBGA: 49 Pin (YFF)
– PDIP: 40 Pin (N) Available in Sampling
Quantities as PMS430G2744IN40
• For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
1.2 Applications
• Sensor Systems • Radio-Frequency Sensor Front End
1.3 Description
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices
featuring different sets of peripherals targeted for various applications. The architecture, combined with
five low-power modes, is optimized to achieve extended battery life in portable measurement applications.
The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute
to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from
low-power modes to active mode in less than 1 µs.
The MSP430G2x44 series is an ultra-low-power mixed-signal microcontroller with two built-in 16-bit timers,
a universal serial communication interface (USCI), 10-bit analog-to-digital converter (ADC) with integrated
reference and data transfer controller (DTC), and 32 I/O pins.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Basic Clock
System+
RAM
1KB
512B
512B
Brownout
Protection
RST/NMI
VCC VSS
MCLK
SMCLK
Watchdog
WDT+
15/16 Bit
Timer_A3
3 CC
Registers
16-MHz
CPU
incl.
16 Registers
Emulation
(2BP)
XOUT
JTAG
Interface
Flash
32KB
16KB
8KB
ACLK
XIN
MDB
MAB
Spy−Bi Wire
Timer_B3
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
ADC10
10 Bit
12 Channels
Autoscan
DTC
Ports P1/P2
2x8 I/O
Interrupt
capability,
pullup/down
resistors
P1.x/P2.x
2x8
P3.x/P4.x
2x8
Ports P3/P4
2x8 I/O
pullup/down
resistors
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
Typical applications include sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system. Stand-alone radio-frequency
(RF) sensor front ends are another area of application.
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PART NUMBER PACKAGE BODY SIZE
MSP430G2744DA TSSOP (38) 12.5 mm x 6.2 mm
MSP430G2744RHA VQFN (40) 6 mm xm 6 mm
MSP430G2744YFF DSBGA (49) 3.1 mm x 3.1 mm
PMS430G2744N PDIP (40) 52.46 mm x 13.71 mm
(1) For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 8, or see the TI web site at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
1.4 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the MSP430G2x44 devices.
Device Information
(1)
(2)
Figure 1-1. Functional Block Diagram
2 Device Overview Copyright © 2013–2014, Texas Instruments Incorporated
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SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
Table of Contents
1 Device Overview ......................................... 1 5.27 USCI (SPI Slave Mode)............................. 30
1.1 Features .............................................. 1 5.28 USCI (I2C Mode) .................................... 31
1.2 Applications........................................... 1
1.3 Description............................................ 1
1.4 Functional Block Diagram ............................ 2
2 Revision History ......................................... 4
3 Device Comparison ..................................... 5
4 Terminal Configuration and Functions.............. 6
4.1 Pin Diagrams ......................................... 6
4.2 Signal Descriptions.................................. 10
5 Specifications........................................... 13
5.1 Absolute Maximum Ratings......................... 13
5.2 Handling Ratings .................................... 13
5.3 Recommended Operating Conditions............... 13
5.4 Active Mode Supply Current (Into DVCC+ AVCC)
Excluding External Current.......................... 15
5.5 Typical Characteristics - Active-Mode Supply
Current (Into DVCC+ AV
5.6 Low-Power-Mode Supply Currents (Into VCC)
Excluding External Current.......................... 16
5.7 Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and
RST/NMI)............................................ 17
5.8 Leakage Current, Ports Px.......................... 17
5.9 Outputs, Ports Px ................................... 17
5.10 Output Frequency, Ports Px ........................ 17
5.11 Typical Characteristics - Outputs ................... 18
5.12 POR and BOR ...................................... 19
5.13 Typical Characteristics - POR and BOR ............ 20
5.14 DCO Frequency..................................... 21
5.15 Calibrated DCO Frequencies, Tolerance ........... 22
5.16 Wake-Up From Lower-Power Modes (LPM3,
LPM4) ............................................... 23
5.17 Typical Characteristics - DCO Clock Wake-Up Time
From LPM3 or LPM4................................ 23
5.18 DCO With External Resistor R
5.19 Typical Characteristics - DCO With External
Resistor R
5.20 Crystal Oscillator LFXT1, Low-Frequency Mode ... 25
5.21 Internal Very-Low-Power Low-Frequency Oscillator
(VLO)................................................ 25
5.22 Crystal Oscillator LFXT1, High-Frequency Mode... 26
5.23 Typical Characteristics - LFXT1 Oscillator in HF
Mode (XTS = 1) ..................................... 27
5.24 Timer_A, Timer_B................................... 28
5.25 USCI (UART Mode)................................. 28
5.26 USCI (SPI Master Mode)............................ 29
....................................... 24
OSC
)......................... 15 6.3 Operating Modes.................................... 40
CC
.................. 24
OSC
5.29 10-Bit ADC, Power Supply and Input Range
Conditions ........................................... 32
5.30 10-Bit ADC, Built-In Voltage Reference............. 33
5.31 10-Bit ADC, External Reference .................... 34
5.32 10-Bit ADC, Timing Parameters .................... 34
5.33 10-Bit ADC, Linearity Parameters................... 35
5.34 10-Bit ADC, Temperature Sensor and Built-In V
MID
...................................................... 35
5.35 Flash Memory ....................................... 36
5.36 RAM................................................. 36
5.37 JTAG and Spy-Bi-Wire Interface.................... 37
5.38 JTAG Fuse .......................................... 37
6 Detailed Description ................................... 38
6.1 CPU ................................................. 38
6.2 Instruction Set....................................... 39
6.4 Interrupt Vector Addresses.......................... 41
6.5 Special Function Registers.......................... 42
6.6 Memory Organization ............................... 43
6.7 Bootstrap Loader (BSL)............................. 43
6.8 Flash Memory ....................................... 43
6.9 Peripherals .......................................... 44
6.10 Oscillator and System Clock ........................ 44
6.11 Brownout ............................................ 44
6.12 Digital I/O............................................ 44
6.13 Watchdog Timer (WDT+) ........................... 44
6.14 Timer_A3............................................ 45
6.15 Timer_B3............................................ 46
6.16 Universal Serial Communications Interface (USCI). 46
6.17 ADC10............................................... 46
6.18 Peripheral File Map ................................. 47
6.19 Port Schematics..................................... 50
7 Device and Documentation Support ............... 69
7.1 Device Support...................................... 69
7.2 Documentation Support ............................. 72
7.3 Related Links........................................ 72
7.4 Community Resources .............................. 72
7.5 Trademarks.......................................... 72
7.6 Electrostatic Discharge Caution..................... 72
7.7 Glossary............................................. 72
8 Mechanical, Packaging, and Orderable
Information .............................................. 73
Copyright © 2013–2014, Texas Instruments Incorporated Table of Contents 3
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2013) to Revision C Page
• Document formatting changes throughout, including addition of section numbering ........................................ 1
• Added Device Information table .................................................................................................... 2
• Added Section 3; moved and renamed Table 3-1................................................................................ 5
• Corrected size of RAM for MSP430G2744 in Table 3-1......................................................................... 5
• Added Section 5 and moved all electrical specifications to it ................................................................. 13
• Added Section 5.2 and moved T
• Added Section 7 and moved Tools Support, Device Nomenclature, ESD Caution, and Trademarks sections to it ... 69
• Added Section 8 .................................................................................................................... 73
to it .......................................................................................... 13
stg
4 Revision History Copyright © 2013–2014, Texas Instruments Incorporated
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3 Device Comparison
Table 3-1 summarizes the available family members.
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
Table 3-1. Device Comparison
Device BSL EEM Timer_A Timer_B Clock I/O
MSP430G2744IRHA40 32 40-QFN
MSP430G2744IDA38 1 1 32 1K TA3 TB3 12 1 DCO, 32 38-TSSOP
MSP430G2744IYFF 32 49-DSBGA
MSP430G2544IRHA40 32 40-QFN
MSP430G2544IDA38 1 1 16 512 TA3 TB3 12 1 DCO, 32 38-TSSOP
MSP430G2544IYFF 32 49-DSBGA
MSP430G2444IRHA40 32 40-QFN
MSP430G2444IDA38 1 1 8 512 TA3 TB3 12 1 DCO, 32 38-TSSOP
MSP430G2444IYFF 32 49-DSBGA
Flash RAM ADC10 USCI_A0, Package
(KB) (B) Channel USCI_B0 Type
(1)(2)
HF, LF,
VLO
HF, LF,
VLO
HF, LF,
VLO
(1) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI web site at
www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Copyright © 2013–2014, Texas Instruments Incorporated Device Comparison 5
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1TEST/SBWTCK
2DVCC
3P2.5/R
OSC
4
XOUT/P2.7
5
XIN/P2.6 6
RST/NMI/SBWTDIO
7
P2.0/ACLK/A0
8
P2.1/TAINCLK/SMCLK/A1 9
P2.2/TA0/A2
10
P3.0/UCB0STE/UCA0CLK/A5
11
P3.1/UCB0SIMO/UCB0SDA 12
P3.2/UCB0SOMI/UCB0SCL
13
P3.3/UCB0CLK/UCA0STE
14
P4.0/TB0
15
P4.1/TB1
16
P4.2/TB2
17
P4.3/TB0/A12
18 P4.4/TB1/A13
19
38 P1.7/TA2/TDO/TDI
37 P1.6/TA1/TDI
36
P1.5/TA0/TMS
35 P1.4/SMCLK/TCK
34
P1.3/TA2
33
P1.2/TA1
32 P1.1/TA0
31
P1.0/TACLK/ADC10CLK
30
P2.4/TA2/A4/VREF+/VeREF+
29 P2.3/TA1/A3/VREF−/VeREF−
28 P3.7/A7
27 P3.6/A6
26 P3.5/UCA0RXD/UCA0SOMI
25
P3.4/UCA0TXD/UCA0SIMO
24
23AVCC
22
AVSS
21
P4.7/TBCLK
20
P4.6/TBOUTH/A15
DVSS
P4.5/TB2/A14
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the pin diagram for the 38-pin DA package.
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Figure 4-1. 38-Pin TSSOP (DA Package) (Top View)
6 Terminal Configuration and Functions Copyright © 2013–2014, Texas Instruments Incorporated
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1TEST/SBWTCK
2DVCC
3
P2.5/R
OSC
4
XOUT/P2.7
5
XIN/P2.6
6
RST/NMI/SBWTDIO
7
P2.0/ACLK/A0
8
P2.1/TAINCLK/SMCLK/A1
9
P2.2/TA0/A2
10
P3.0/UCB0STE/UCA0CLK/A5
11
P3.1/UCB0SIMO/UCB0SDA
12
P3.2/UCB0SOMI/UCB0SCL
13
P3.3/UCB0CLK/UCA0STE
14
P4.0/TB0
15
P4.1/TB1
16
P4.2/TB2
17
P4.3/TB0/A12
18
P4.4/TB1/A13
19
39
P1.7/TA2/TDO/TDI
38
P1.6/TA1/TDI
37
P1.5/TA0/TMS
36
P1.4/SMCLK/TCK
35
P1.3/TA2
34
P1.2/TA1
33
P1.1/TA0
32
P1.0/TACLK/ADC10CLK
31
P2.4/TA2/A4/VREF+/VeREF+
30
P2.3/TA1/A3/VREF−/VeREF−
29
P3.7/A7
28
P3.6/A6
27
P3.5/UCA0RXD/UCA0SOMI
26
P3.4/UCA0TXD/UCA0SIMO
25
24
AVCC
23
AVSS
22
P4.7/TBCLK
21
P4.6/TBOUTH/A15
DVSS
P4.5/TB2/A14
DVSS
20
DVCC
40
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Figure 4-2 shows the pin diagram for the 40-pin N package.
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
Figure 4-2. 40-Pin PDIP (N Package) (Top View)
Copyright © 2013–2014, Texas Instruments Incorporated Terminal Configuration and Functions 7
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1DVSS
P1.5/TA0/TMS
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
13
P2.4/TA2/A4/VREF+/VeREF+
P2.5/R
OSC
DVCC
TEST/SBWTCK
P1.6/TA1/TDI/TCLK
2
3
4
5
6
7
8
10
9
12 14 15 16 17 18 19
30
29
28
27
26
25
24
23
21
22
3839 37 36 35 34 33 32
XOUT/P2.7
XIN/P2.6
DVSS
RST/NMI/SBWTDIO
P2.0/ACLK/A0
P2.1/TAINCLK/SMCLK/A1
P2.2/TA0/A2
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
DVCC
P1.7/TA2/TDO/TDI
P2.3/TA1/A3/VREF−/VeREF−
P3.7/A7
P3.6/A6
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
AVCC
AVSS
P3.3/UCB0CLK/UCA0STE
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0/A12
P4.4/TB1/A13
P4.5/TB2/A14
P4.6/TBOUTH/A15
P4.7/TBCLK
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
Figure 4-3 shows the pin diagram for the 40-pin RHA package.
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8 Terminal Configuration and Functions Copyright © 2013–2014, Texas Instruments Incorporated
Figure 4-3. 40-Pin QFN (RHA Package) (Top View)
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YFF PACKAGE
(TOP VIEW)
P2.0P2.2 P2.6 P2.7P3.1P3.2
DV
SS
A1A2
A4
A3
A5
A6
A7
B1B2
B4
B3
B5
B6
B7
C1C2C4
C3
C5C6C7
D1D2
D4
D3
D5
D6
D7
E1E2
E4
E3
E5
E6
E7
F1F2
F4
F3
F5
F6
F7
G1G2G4
G3
G5G6G7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5P1.6
P1.7
P2.1
P2.3
P2.4
P2.5
P3.0P3.3
P3.4 P3.5
P3.6
P3.7
P4.0P4.1
P4.2P4.3
P4.4 P4.5
P4.6
P4.7
RST/NMI
TEST
DV
CC
DV
CC
DV
CC
DV
CC
DV
CC
AV
CC
AV
CC
AV
CC
DV
SS
DV
SS
DV
SS
DV
SS
AV
SS
AV
SS
YFF PACKAGE
(BALL-SIDE VIEW)
P2.0 P2.2P2.6P2.7 P3.1 P3.2
DV
SS
A1 A2
A4
A3
A5
A6
A7
B1 B2
B4
B3
B5
B6
B7
C1 C2 C4
C3
C5 C6 C7
D1 D2
D4
D3
D5
D6
D7
E1 E2
E4
E3
E5
E6
E7
F1 F2
F4
F3
F5
F6
F7
G1 G2 G4
G3
G5 G6 G7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5 P1.6
P1.7
P2.1
P2.3
P2.4
P2.5
P3.0 P3.3
P3.4P3.5
P3.6
P3.7
P4.0 P4.1
P4.2 P4.3
P4.4P4.5
P4.6
P4.7
RST/NMI
TEST
DV
CC
DV
CC
DV
CC
DV
CC
DV
CC
AV
CC
AV
CC
AV
CC
DV
SS
DV
SS
DV
SS
DV
SS
AV
SS
AV
SS
D
E E
D
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Figure 4-4 shows the pin diagram for the 49-pin YFF package.
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
Figure 4-4. 49-Pin DSBGA (YFF Package)
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4.2 Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Terminal Functions
TERMINAL
NAME
YFF DA N RHA
P1.0/TACLK/ADC10CLK F2 31 33 29 I/O Timer_A, clock signal TACLK input
P1.1/TA0 G2 32 34 30 I/O
P1.2/TA1 E2 33 35 31 I/O
P1.3/TA2 G1 34 36 32 I/O
P1.4/SMCLK/TCK F1 35 37 33 I/O SMCLK signal output
P1.5/TA0/TMS E1 36 38 34 I/O Timer_A, compare: OUT0 output
P1.6/TA1/TDI/TCLK E3 37 39 35 I/O Timer_A, compare: OUT1 output
P1.7/TA2/TDO/TDI
(1)
D2 38 40 36 I/O Timer_A, compare: OUT2 output
P2.0/ACLK/A0 A4 8 10 6 I/O ACLK output
P2.1/TAINCLK/
SMCLK/A1
B4 9 11 7 I/O Timer_A, clock signal at INCLK, SMCLK signal output
P2.2/TA0/A2 A5 10 12 8 I/O Timer_A, capture: CCI0B input; BSL receive, compare: OUT0 output
P2.3/TA1/A3/ V
P2.4/TA2/A4/
V
REF+/VeREF+
P2.5/R
OSC
REF-/VeREF-
F3 29 31 27 I/O
G3 30 32 28 I/O
C2 3 4 40 I/O
NO. I/O DESCRIPTION
General-purpose digital I/O pin
ADC10, conversion clock
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output; BSL transmit
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
Test Clock input for device programming and test
General-purpose digital I/O pin
Test Mode Select input for device programming and test
General-purpose digital I/O pin
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
ADC10, analog input A0
General-purpose digital I/O pin
ADC10, analog input A1
General-purpose digital I/O pin
ADC10, analog input A2
General-purpose digital I/O pin
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
Negative reference voltage output/input
General-purpose digital I/O pin
Timer_A, compare: OUT2 output
ADC10, analog input A4
Positive reference voltage output/input
General-purpose digital I/O pin
Input for external DCO resistor to define DCO frequency
(1) TDO or TDI is selected via JTAG instruction.
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Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
YFF DA N RHA
XIN/P2.6 A2 6 7 3 I/O
XOUT/P2.7 A1 5 6 2 I/O
P3.0/UCB0STE/
UCA0CLK/A5
P3.1/UCB0SIMO/
UCB0SDA
P3.2/UCB0SOMI/
UCB0SCL
P3.3/UCB0CLK/
UCA0STE
P3.4/UCA0TXD/
UCA0SIMO
P3.5/UCA0RXD/
UCA0SOMI
B5 11 13 9 I/O
A6 12 14 10 I/O USCI_B0 slave in, master out in SPI mode
A7 13 15 11 I/O USCI_B0 slave out, master in SPI mode
B6 14 16 12 I/O USCI_B0 clock input/output
G6 25 27 23 I/O USCI_A0 transmit data output in UART mode
G5 26 28 24 I/O USCI_A0 receive data input in UART mode
P3.6/A6 F4 27 29 25 I/O
P3.7/A7 G4 28 30 26 I/O
P4.0/TB0 D6 17 19 15 I/O
P4.1/TB1 D7 18 20 16 I/O
P4.2/TB2 E6 19 21 17 I/O
P4.3/TB0/A12 E7 20 22 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output
P4.4/TB1/A13 F7 21 23 19 I/O Timer_B, capture: CCI1B input, compare: OUT1 output
P4.5/TB2/A14 F6 22 24 20 I/O Timer_B, compare: OUT2 output
NO. I/O DESCRIPTION
Input terminal of crystal oscillator
General-purpose digital I/O pin
Output terminal of crystal oscillator
General-purpose digital I/O pin
(2)
General-purpose digital I/O pin
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
USCI_B0 SDA I2C data in I2C mode
General-purpose digital I/O pin
USCI_B0 SCL I2C clock in I2C mode
General-purpose digital I/O pin
USCI_A0 slave transmit enable
General-purpose digital I/O pin
USCI_A0 slave in, master out in SPI mode
General-purpose digital I/O pin
USCI_A0 slave out, master in SPI mode
General-purpose digital I/O pin
ADC10 analog input A6
General-purpose digital I/O pin
ADC10 analog input A7
General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
ADC10 analog input A12
General-purpose digital I/O pin
ADC10 analog input A13
General-purpose digital I/O pin
ADC10 analog input A14
(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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Table 4-1. Terminal Functions (continued)
TERMINAL
NAME
YFF DA N RHA
P4.6/TBOUTH/A15 G7 23 25 21 I/O Timer_B, switch all TB0 to TB3 outputs to high impedance
P4.7/TBCLK F5 24 26 22 I/O
RST/NMI/SBWTDIO B3 7 9 5 I
TEST/SBWTCK D1 1 1 37 I
C1,
D3,
DV
CC
D4, 2 2, 3 38, 39 Digital supply voltage
E4,
E5
C6,
AV
CC
C7, 16 18 14 Analog supply voltage
D5
A3,
B1,
DV
SS
B2, 4 5, 8 1, 4 Digital ground reference
C3,
C4
AV
SS
B7,
C5
QFN Pad NA NA NA Pad NA QFN package pad; connection to DVSSrecommended.
NO. I/O DESCRIPTION
General-purpose digital I/O pin
ADC10 analog input A15
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection
fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
15 17 13 Analog ground reference
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5 Specifications
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
5.1 Absolute Maximum Ratings
(1)(2)
MIN MAX UNIT
Voltage applied at V
CC
Voltage applied to any pin
(3)
-0.3 4.1 V
-0.3 VCC+ 0.3 V
Diode current at any device terminal ±2 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS.
(3) The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when
blowing the JTAG fuse.
5.2 Handling Ratings
MIN MAX UNIT
T
stg
Storage temperature (programmed or unprogrammed device)
(1) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
5.3 Recommended Operating Conditions
(1)(2)
Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)
V
CC
V
SS
T
A
f
SYSTEM
(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Supply voltage AVCC= DVCC= V
Supply voltage AVSS= DVSS= V
CC
SS
Operating free-air temperature -40 85 °C
Processor frequency
(maximum MCLK frequency)
(see Figure 5-1)
VCC= 1.8 V, Duty cycle = 50% ±10% dc 4.15
(1)(2)
VCC= 2.7 V, Duty cycle = 50% ±10% dc 12 MHz
VCC≥ 3.3 V, Duty cycle = 50% ±10% dc 16
(1)
-55 150 °C
MIN NOM MAX UNIT
During program execution 1.8 3.6 V
During program and erase of
flash memory
2.2 3.6 V
0 V
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4.15 MHz
12 MHz
16 MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
Supply Voltage − V
System Frequency – MHz
Supply voltage range
during flash memory
programming
Supply voltage range
during program execution
Legend:
7.5 MHz
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
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NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V
of 2.2 V.
Figure 5-1. Operating Area
CC
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0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC− Supply Voltage − V
Active Mode Current − mA
f
DCO
= 1 MHz
f
DCO
= 8 MHz
f
DCO
= 12 MHz
f
DCO
= 16 MHz
0.0
1.0
2.0
3.0
4.0
5.0
0.0 4.0 8.0 12.0 16.0
f
DCO
− DCO Frequency − MHz
Active Mode Current − mA
TA= 25 °C
TA= 85 °C
VCC= 2.2 V
VCC= 3 V
TA= 25 °C
TA= 85 °C
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MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
5.4 Active Mode Supply Current (Into DVCC+ AVCC) Excluding External Current
(1)(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
AM,1MHz
PARAMETER TEST CONDITIONS T
f
= f
Active mode (AM)
current (1 MHz)
DCO
f
ACLK
Program executes in flash,
= f
MCLK
= 32768 Hz,
BCSCTL1 = CALBC1_1MHZ, µA
DCOCTL = CALDCO_1MHZ,
= 1 MHz, 2.2 V 270
SMCLK
A
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
V
CC
MIN TYP MAX UNIT
3 V 390 550
5.5 Typical Characteristics - Active-Mode Supply Current (Into DVCC+ AVCC)
TA= 25°C
Figure 5-2. Active-mode Current vs Supply Voltage Figure 5-3. Active-Mode Current vs DCO Frequency
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5.6 Low-Power-Mode Supply Currents (Into VCC) Excluding External Current
(1)(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
LPM0,1MHz
PARAMETER TEST CONDITIONS T
f
= 0 MHz,
MCLK
f
= f
= 1 MHz,
DCO
= 32768 Hz,
Low-power mode 0
(LPM0) current
(3)
SMCLK
f
ACLK
BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 75 90 µA
DCOCTL = CALDCO_1MHZ,
A
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
f
I
LPM2
Low-power mode 2
(LPM2) current
(4)
= f
MCLK
f
= 1 MHz,
DCO
f
= 32768 Hz,
ACLK
BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 22 µA
DCOCTL = CALDCO_1MHZ,
SMCLK
= 0 MHz,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
f
= f
I
LPM3,LFXT1
Low-power mode 3 f
(LPM3) current
(4)
DCO
ACLK
CPUOFF = 1, SCG0 = 1,
= f
MCLK
= 32768 Hz,
SMCLK
= 0 MHz,
25°C 2.2 V 1 2 µA
SCG1 = 1, OSCOFF = 0
f
= f
I
LPM3,VLO
Low-power mode 3
current, (LPM3)
(4)
DCO
f
ACLK
(VLO), 25°C 2.2 V 0.5 1 µA
= f
MCLK
from internal LF oscillator
CPUOFF = 1, SCG0 = 1,
SMCLK
= 0 MHz,
SCG1 = 1, OSCOFF = 0
f
= f
I
LPM4
Low-power mode 4 f
(LPM4) current
(5)
MCLK
= 0 Hz,
= f
DCO
ACLK
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
= 0 MHz, 25°C 0.1 0.5
SMCLK
85°C 1.5 3
(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
(3) Current for brownout and WDT clocked by SMCLK included.
(4) Current for brownout and WDT clocked by ACLK included.
(5) Current for brownout included.
V
MIN TYP MAX UNIT
CC
2.2 V µA
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5.7 Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
V
Positive-going input threshold voltage V
IT+
V
Negative-going input threshold voltage V
IT-
V
Input voltage hysteresis (V
hys
R
Pullup or pulldown resistor 3 V 20 35 50 kΩ
Pull
C
Input capacitance VIN= VSSor V
I
IT+
- V
) 3 V 0.3 1 V
IT-
For pullup: VIN= VSS,
For pulldown: VIN= V
CC
CC
CC
3 V 1.35 2.25
3 V 0.75 1.65
MIN TYP MAX UNIT
0.45 V
0.25 V
CC
CC
0.75 V
0.55 V
5 pF
CC
CC
5.8 Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
lkg(Px.y)
PARAMETER TEST CONDITIONS V
High-impedance leakage current
(1) (2)
CC
3 V ±50 nA
(1) The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
MIN TYP MAX UNIT
5.9 Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
V
V
High-level output voltage I
OH
Low-level output voltage I
OL
(1) The maximum total current, I
specified.
OH(max)
and I
= -6 mA
OH(max)
= 6 mA
OL(max)
, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
OL(max)
(1)
(1)
CC
3 V VCC- 0.3 V
3 V VSS+ 0.3 V
MIN TYP MAX UNIT
5.10 Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f
Px.y
f
Port_CLK
PARAMETER TEST CONDITIONS V
Port output frequency (with load) 3 V 12 MHz
Clock output frequency Px.y, CL= 20 pF
Px.y, CL= 20 pF,
RL= 1 kΩ against VCC/2
(2)
(1)(2)
CC
3 V 16 MHz
(1) Alternatively, a resistive divider with two 2-kΩ resistors between VCCand VSSis used as load. The output is connected to the center tap
of the divider.
(2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.
MIN TYP MAX UNIT
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VOH− High-Level Output Voltage − V
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC= 2.2 V
P4.5
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOH− High-Level Output Voltage − V
−50.0
−40.0
−30.0
−20.0
−10.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC= 3 V
P4.5
TA= 25°C
TA= 85°C
OH
I − Typical High-Level Output Current − mA
VOL− Low-Level Output V oltage − V
0.0
5.0
10.0
15.0
20.0
25.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC= 2.2 V
P4.5
TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
VOL− Low-Level Output V oltage − V
0.0
10.0
20.0
30.0
40.0
50.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC= 3 V
P4.5
TA= 25°C
TA= 85°C
OL
I − Typical Low-Level Output Current − mA
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
5.11 Typical Characteristics - Outputs
One output loaded at a time.
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Figure 5-4. Typical Low-Level Output Current vs Low-Level Figure 5-5. Typical Low-Level Output Current vs Low-Level
Figure 5-6. Typical High-Level Output Current vs High-Level Figure 5-7. Typical High-Level Output Current vs High-Level
Output Voltage Output Voltage
Output Voltage Output Voltage
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0
1
t
d(BOR)
V
CC
V
(B_IT−)
V
hys(B_IT−)
V
CC(star t)
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5.12 POR and BOR
(1)(2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V
CC(start)
V
(B_IT-)
V
hys(B_IT-)
t
d(BOR)
t
(reset)
PARAMETER TEST CONDITIONS V
See Figure 5-8 dVCC/dt ≤ 3 V/s V
See Figure 5-8 through Figure 5-10 dVCC/dt ≤ 3 V/s 1.35 V
See Figure 5-8 dVCC/dt ≤ 3 V/s 140 mV
See Figure 5-8 2000 µs
Pulse duration needed at RST/NMI pin to
accept reset internally
CC
2.2 V 2 µs
(1) The current consumption of the brownout module is already included in the ICCcurrent consumption data. The voltage level V
V
hys(B_IT-)
(2) During power up, the CPU begins code execution following a period of t
must not be changed until VCC≥ V
is ≤ 1.8 V.
CC(min)
, where V
after VCC= V
is the minimum supply voltage for the desired operating frequency.
CC(min)
d(BOR)
(B_IT-)
MIN TYP MAX UNIT
0.7 ×
V
(B_IT-)
+ V
hys(B_IT-)
. The default DCO settings
(B_IT-)
+
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Figure 5-8. POR and BOR vs Supply Voltage
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V
CC
0
0.5
1
1.5
2
V
CC(drop)
t
pw
tpw− Pulse Width − µs
V
CC(drop)
− V
3 V
0.001 1 1000
t
f
t
r
tpw− Pulse Width − µs
tf= t
r
Typical Conditions
VCC= 3 V
V
CC(drop)
V
CC
3 V
t
pw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
tpw− Pulse Width − µs
V
CC(drop)
− V
tpw− Pulse Width − µs
VCC= 3 V
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
5.13 Typical Characteristics - POR and BOR
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Figure 5-9. V
Figure 5-10. V
CC(drop)
CC(drop)
Level With a Square Voltage Drop to Generate a POR or BOR Signal
Level With a Triangular Voltage Drop to Generate a POR or BOR Signal
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5.14 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V
CC
f
DCO(0,0)
f
DCO(0,3)
f
DCO(1,3)
f
DCO(2,3)
f
DCO(3,3)
f
DCO(4,3)
f
DCO(5,3)
f
DCO(6,3)
f
DCO(7,3)
f
DCO(8,3)
f
DCO(9,3)
f
DCO(10,3)
f
DCO(11,3)
f
DCO(12,3)
f
DCO(13,3)
f
DCO(14,3)
f
DCO(15,3)
f
DCO(15,7)
S
RSEL
S
DCO
PARAMETER TEST CONDITIONS V
CC
RSELx < 14 1.8 3.6
Supply voltage range RSELx = 14 2.2 3.6 V
RSELx = 15 3.0 3.6
DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3 V 0.06 0.14 MHz
DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3 V 0.07 0.17 MHz
DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3 V MHz
DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3 V MHz
DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3 V MHz
DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3 V MHz
DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3 V MHz
DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3 V 0.54 1.06 MHz
DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3 V 0.80 1.50 MHz
DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3 V 1.6 MHz
DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3 V 2.3 MHz
DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3 V 3.4 MHz
DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3 V 4.25 MHz
DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3 V 4.30 7.30 MHz
DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3 V 6.00 9.60 MHz
DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3 V 8.60 13.9 MHz
DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 12.0 18.5 MHz
DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 16.0 26.0 MHz
Frequency step between
range RSEL and RSEL+1
Frequency step between tap
DCO and DCO+1
S
S
= f
RSEL
DCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
= f
DCO
DCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3 V 1.35 ratio
3 V 1.08 ratio
Duty cycle Measured at SMCLK 3 V 50%
MIN TYP MAX UNIT
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5.15 Calibrated DCO Frequencies, Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS T
1-MHz tolerance over
temperature
(1)
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ, 0°C to 85°C 3 V -3% ±0.5% +3%
calibrated at 30°C and 3 V
A
BCSCTL1 = CALBC1_1MHZ,
1-MHz tolerance over V
CC
DCOCTL = CALDCO_1MHZ, 30°C 1.8 V to 3.6 V -3% ±2% +3%
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_1MHZ,
1-MHz tolerance overall DCOCTL = CALDCO_1MHZ, -40°C to 85°C 1.8 V to 3.6 V -6% ±3% +6%
calibrated at 30°C and 3 V
8-MHz tolerance over
temperature
(1)
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ, 0°C to 85°C 3 V -3% ±0.5% +3%
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHZ,
8-MHz tolerance over V
CC
DCOCTL = CALDCO_8MHZ, 30°C 2.2 V to 3.6 V -3% ±2% +3%
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_8MHZ,
8-MHz tolerance overall DCOCTL = CALDCO_8MHZ, -40°C to 85°C 2.2 V to 3.6 V -6% ±3% +6%
calibrated at 30°C and 3 V
12-MHz tolerance over
temperature
(1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ, 0°C to 85°C 3 V -3% ±0.5% +3%
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHZ,
12-MHz tolerance over V
CC
DCOCTL = CALDCO_12MHZ, 30°C 2.7 V to 3.6 V -3% ±2% +3%
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_12MHZ,
12-MHz tolerance overall DCOCTL = CALDCO_12MHZ, -40°C to 85°C 2.7 V to 3.6 V -6% ±3% +6%
calibrated at 30°C and 3 V
16-MHz tolerance over
temperature
(1)
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ, 0°C to 85°C 3 V -3% ±0.5% +3%
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHZ,
16-MHz tolerance over V
CC
DCOCTL = CALDCO_16MHZ, 30°C 3.3 V to 3.6 V -3% ±2% +3%
calibrated at 30°C and 3 V
BCSCTL1 = CALBC1_16MHZ,
16-MHz tolerance overall DCOCTL = CALDCO_16MHZ, -40°C to 85°C 3.3 V to 3.6 V -6% ±3% +6%
calibrated at 30°C and 3 V
(1) This is the frequency change from the measured frequency at 30°C over temperature.
V
CC
MIN TYP MAX UNIT
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DCO Frequency − MHz
0.10
1.00
10.00
0.10 1.00 10.00
RSELx = 0...11
RSELx = 12...15
DCO Wake-Up Time − µs
MSP430G2744, MSP430G2544, MSP430G2444
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SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
5.16 Wake-Up From Lower-Power Modes (LPM3, LPM4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
t
DCO,LPM3/4
t
CPU,LPM3/4
PARAMETER TEST CONDITIONS V
DCO clock wake-up time BCSCTL1 = CALBC1_1MHZ,
from LPM3 or LPM4
CPU wake-up time from 1 / f
LPM3 or LPM4
(1)
(2)
DCOCTL = CALDCO_1MHZ
CC
3 V 1.5 µs
(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
(2) Parameter applicable only if DCOCLK is used for MCLK.
MIN TYP MAX UNIT
+
MCLK
t
Clock,LPM3/4
5.17 Typical Characteristics - DCO Clock Wake-Up Time From LPM3 or LPM4
Figure 5-11. Clock Wake-Up Time From LPM3 vs DCO Frequency
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0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
−50.0 −25.0 0.0 25.0 50.0 75.0 100.0
T
− Temperature − °C
DCO Frequency − MHz
R
OSC
= 100k
R
OSC
= 270k
R
OSC
= 1M
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.0 2.5 3.0 3.5 4.0
VCC− Supply Voltage − V
DCO Frequency − MHz
R
OSC
= 100k
R
OSC
= 270k
R
OSC
= 1M
0.01
0.10
1.00
10.00
10.00 100.00 1000.00 10000.00
R
OSC
− External Resistor − kW
DCO Frequency − MHz
RSELx = 4
0.01
0.10
1.00
10.00
10.00 100.00 1000.00 10000.00
R
OSC
− External Resistor − kW
DCO Frequency − MHz
RSELx = 4
MSP430G2744, MSP430G2544, MSP430G2444
SLAS892C –MARCH 2013–REVISED SEPTEMBER 2014
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5.18 DCO With External Resistor R
OSC
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS V
DCOR = 1, 2.2 V 1.8
f
DCO,ROSC
D
T
D
V
(1) R
DCO output frequency with R
OSC
Temperature drift 2.2 V, 3 V ±0.1 %/°C
Drift with V
= 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK= ±50 ppm/°C.
OSC
CC
RSELx = 4, DCOx = 3, MODx = 0, MHz
TA= 25°C
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
5.19 Typical Characteristics - DCO With External Resistor R
CC
3 V 1.95
2.2 V, 3 V 10 %/V
OSC
MIN TYP MAX UNIT
VCC= 2.2 V TA= 25°C VCC= 3 V TA= 25°C
Figure 5-12. DCO Frequency vs R
VCC= 3 V TA= 25°C
Figure 5-14. DCO Frequency vs Temperature Figure 5-15. DCO Frequency vs Supply Voltage
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Figure 5-13. DCO Frequency vs R
OSC
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