Texas Instruments PGA411-Q1 EVM User Manual

User's Guide

SLAU658–March 2016

PGA411-Q1 EVM User's Guide

The PGA411-Q1 EVM allows users to evaluate the functionality of the PGA411-Q1 device. This user’s guide describes both the hardware platform containing a sample PGA411-Q1 device, and the graphical user interface (GUI) software used to configure the functionality and diagnostics on the PGA411-Q1 resolver-to-digital interface IC. In addition to evaluating the PGA411-Q1 device, the other objective of this board is to display in the GUI the position (angle) or velocity readings from a resolver sensor.

This document also includes the EVM schematics, bill of materials, and PCB layout.

NOTE: Texas Instruments recommends using the PGA411-Q1 EVM user's guide (this document)

after reading and following the steps listed in the PGA411-Q1 Evaluation Module Quick Start Guide. To download this guide, go to the product folder: www.ti.com/product/PGA411-Q1.

Contents

1 Introduction ................................................................................................................... 3

2 Setup and Operation ........................................................................................................ 3

2.1 Required Equipment for Device Evaluation ..................................................................... 3

2.2 Initial EVM Setup ................................................................................................... 3

2.3 GUI Software ........................................................................................................ 7

3 EVM Evaluation Examples................................................................................................ 16

3.1 EVM Checks for Proper Operation.............................................................................. 16

4 Schematics, Bill of Materials, and Layout............................................................................... 20

4.1 Schematics......................................................................................................... 21

4.2 Bill of Materials .................................................................................................... 23

4.3 Layout and Component Placement............................................................................. 27

1 PGA411-Q1 EVM Block Diagram.......................................................................................... 3

2 PGA411-Q1 EVM............................................................................................................ 4

3 PGA411-Q1 GUI Block Diagram........................................................................................... 5

4 PGA411-Q1 Device Startup Failed........................................................................................ 5

5 GUI PGA41x-Q1 EVM Main Screen ...................................................................................... 8

6 Device-State Status and Selection ........................................................................................ 8

7 Pin Configuration Screen ................................................................................................... 9

8 Memory Map................................................................................................................ 11

9 Bit Selection................................................................................................................. 11

10 Hex Selection (REG)....................................................................................................... 11

11 Search Box and Register Descriptions.................................................................................. 12

12 Data Monitor ................................................................................................................ 13

13 DEMO Screen .............................................................................................................. 14

14 Fault Status ................................................................................................................. 15

15 FAULTRES Change in Block Diagram .................................................................................. 16

16 FAULTRES Change in Pin Configuration Tab ......................................................................... 17

MSP430, E2E are trademarks of Texas Instruments. Windows is a registered trademark of Microsoft Corporation. All other trademarks are the property of their respective owners.

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List of Figures

PGA411-Q1 EVM User's Guide

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17 Test Points for Exciter Outputs and Common Mode Voltage ........................................................ 18

18 OE1-OE2 Differential Output from the Exciter.......................................................................... 19

19 DEV_OVUV Register Bits Relevant to Exciter Amplifier Gain........................................................ 19

20 Exciter Amplifier Gain Change Using Memory Map ................................................................... 20

21 OE1-OE2 Differential Output from the Exciter With Updated Gain .................................................. 20

22 EVM Schematic............................................................................................................. 21

23 Schematic—Digital Interface.............................................................................................. 22

24 Top-Side Layout............................................................................................................ 27

25 Bottom-Side Layout ........................................................................................................ 27

List of Tables

1 Description of EVM Switches .............................................................................................. 6

2 Description of EVM Jumpers............................................................................................... 6

3 BOM.......................................................................................................................... 23

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PGA411-Q1

USB

SINE

SPI <4>

PGA411-Q1 EVM

5-V V

EXCITER

20-MHz XTAL

5 V

FAULT

FAULTRES

Data<N>

PGA411-Q1

GUI

From

Resolver

RESET

Resolver

COSINE

MSP430

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1 Introduction

The PGA411-Q1 evaluation module (EVM) is a board designed for the evaluation of the PGA411-Q1 resolver-to-digital interface IC from Texas Instruments. The PGA411-Q1 EVM incorporates all required circuitry and components with the following features:

• PGA411-Q1 resolver-to-digital interface with power supply & amp

• Texas Instruments' MSP430™ microcontroller used for controlling the PGA411-Q1 device through the I/O pins and a SPI port in addition to receiving digital data in different formats

• Voltage LDO regulator, TI's TLV716P, to provide configurable VIOvoltages (3.3 V or 1.8 V)

• Voltage LDO regulator, TI's TPS735, for the 3.3-V MSP430

• Circuitry for interfacing general resolver sensors

• 20-MHz XTAL as PGA411-Q1 single reference clock

• Multiple test points for main analog and digital signals

• UART, JTAG, and USB connectors

Figure 1 shows the PGA411-Q1 EVM architecture, where the key components and blocks previously listed

can be identified.

Introduction

2 Setup and Operation

2.1 Required Equipment for Device Evaluation

The following elements are required for proper operation and to receive consistent results with this user's guide:

• A single power supply that is capable of 5-V operation and a minimum current of 0.5 A

• A computer with Windows®XP or Windows 7 and .net Framework 4.0 or later

• The PGA411-Q1 GUI

• A resolver sensor connected to the correct ports. Refer to the resolver data sheet for more information.

2.2 Initial EVM Setup

2.2.1 Installing Graphical User Interface Software

Before the PGA411-Q1 device can be evaluated the GUI software must be available on a host computer. Run the GUI installer and place the executable file in a convenient location (Desktop or c:\Texas Instruments EVM\) and double click to run the application.

To download the PGA411-Q1 GUI go to www.ti.com/product/PGA411-Q1.

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Figure 1. PGA411-Q1 EVM Block Diagram

PGA411-Q1 EVM User's Guide

NRST

(S3)

FAULT_RES

(S2)

MCU_RST (S4)

USB

(J15)

5-V

(1-2)

J3 (3-4)

J10

(3-5, 4-6)

Resolver Sensor

Connections

J11

PGA411-Q1

MSP430

LED USB_RDY

(D12)

Setup and Operation

2.2.2 Set-Up Instructions

For set-up instructions, refer to Figure 2.

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Figure 2. PGA411-Q1 EVM

This EVM contains components that are sensitive to Electrostatic Discharge (ESD). Use proper laboratory techniques and equipment

WARNING

to minimize the chance of an ESD or EOS event.

Step 1. Set up EVM jumpers as follows:

• Confirm the J3 jumper settings (3-4) for 3.3-V VIO. This step is required for proper operation with the MSP430 device.

• Confirm the J5 jumper settings (3-5 and 4-6) to connect the exciter outputs (OEx pins) to the IEx input pins. The tracking loop inside the PGA411-Q1 device must sense the exciter outputs.

• Confirm that the J2 jumper is present to connect the internal boost supply to the supply input of the integrated exciter amplifier (VEXT).

NOTE: Using the integrated boost supply for the exciter amplifier is strongly

recommended.

Step 2. Apply the 5-V supply to the banana connectors for VCCand GND.

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Reset

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Setup and Operation

Step 3. Connect the USB cable to the EVM and to the PC.

NOTE: Power, as described in Step 2, must be applied before connecting the USB.

Step 4. Verify that the LED USB_RDY (D12) is on, ensuring a good connection. If it is blinking or off,

unplug and replug the USB cable, and press the MCU reset, MCU_RST (S4). Step 5. Launch the PGA411-Q1 GUI. Step 6. Wait a few seconds after the GUI welcome screen appears. The first view should be of a

block diagram which is a high level representation of the PGA411-Q1 resolver-to-digital

interface and contains interactive features. The red boxes indicate controls that can be used

to configure internal blocks inside the PGA411-Q1 device. If the connection is successful, the Connection Status field displays Connected and a revision number

is displayed in the PGA411-Q1 Device field as shown in Figure 3. If the connection process failed, press the S4 switch on the EVM and then press the Reset button in the upper left corner of the GUI (see Figure 3) to restart the connection.

NOTE: Follow the start-up procedure carefully and ensure that board connections are correct. The

power must be applied before the USB cable is plugged in. The USB_RDY LED close to the MSP430 controller should remain on continuously after connecting the USB cable and should not blink. If the device does not power up properly, the EVM status field in the GUI will display: PGA41x-Q1 Device: Not Available as shown in Figure 4. If this occurs, turn off the 5-V power supply, unplug the USB cable, and go back to Step 2.

Figure 4. PGA411-Q1 Device Startup Failed

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Figure 3. PGA411-Q1 GUI Block Diagram

PGA411-Q1 EVM User's Guide

Setup and Operation

2.2.2.1 EVM Switches and Jumpers Settings

Refer to Figure 2 for the locations of the switches and jumpers on the PGA411-Q1 EVM.

Table 1 lists the descriptions of the EVM switches. Table 2 lists the descriptions of the EVM jumpers.

Table 1. Description of EVM Switches

Switch (SW) Description

0: This position is the default and selects the prepopulated IZx resistive divider

S1 Voltage divider

S2 Fault reset S3 Device reset This switch pulls the NRST pin low. This action resets the PGA411-Q1 device.

S4 MSP430 BSL This switch resets the MSP430 microcontroller. The firmware is reloaded.

(30 kΩ / 30 kΩ). 1: This position selects the user-populated IZx resistive divider (30 kΩ / external

resistor value). This switch pulls the FAULTRES pin low when pressed. When this switch is

pressed and then released, all faults from the PGA411 device are cleared.

Table 2. Description of EVM Jumpers

Jumper No. Function State Description

J2 VEXT Jumper

J3 VIO SELECT

J4 OEx Terminal

J5 OEx to IEx

J6 COS IZx terminal

J7 SIN IZx terminal

J10 Analog Connector — Header for analog signals J11 Digital Connector — Header for digital signals J15 USB Connector — Connector for USB cable

Open Disconnect VEXT from boost output

Closed (Default) Connect VEXT to boost output

1-2 Do not use

3-4 (Default) VIO = 3.3 V

5-6

Pin 1 Exciter output 1 to resolver (OE1)

Pin 2 Exciter output 2 to resolver (OE2) 3-5 (Default) Connect OE1 to IE1 through voltage divider 4-6 (Default) Connect OE2 to IE2 through voltage divider

All other combinations Do not use

Pin 1 Input to IZ1 external filter

Pin 2 Input to IZ3 external filter

Pin 1 Input to IZ2 external filter

Pin 2 Input to IZ4 external filter

VIO = VCC (5 V), Do not use with current EVM version. This mode is to interface PGA411-Q1 device with external microcontrollers.

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2.3 GUI Software

2.3.1 PGA41x-Q1 GUI Main Screen

Figure 5 shows the default starting screen of the PGA41x-Q1 GUI. If the EVM is connected properly, the

screen should display the values that follow for the EVM Status fields, as described in Step 5 in

Section 2.2.2:

• USB Controller: USB2ANY I/F Found

• USB Firmware: 2.6.5.53 (this value is designed for Revision B of the EVM)

• Connection Status: Connected

• PGA41x-Q1 Device: Revision: v10.1 The default GUI view is the block diagram of the PGA411-Q1 resolver-to-digital interface IC and contains

interactive features. All boxes in red, as shown in Figure 5, are controls that can be configured. These boxes indicate the default values of the PGA411-Q1 device after power on. The configurable elements in this block diagram include:

• Internal boost voltage control – Boost output voltage from 10 to 17 V

• Exciter amplifier – Exciter frequency (10 to 20 kHz) – Exciter amplitude (4 V – Exciter amplifier gain (1.15 to 1.9 V/V ) – Common-mode offset (0.5 to 2 V)

Use a scope probe on the test points next to exciter connection, J4, to view changes to these blocks instantaneously. The optimum values depend on the characteristics of the resolver sensor that is used.

• Analog front end (AFE) – COS gain and SIN gain from 0.75 to 3.5 V/V. – Diagnostic values for detection thresholds on the AFE amplifiers. These values include both the

high and low thresholds. The optimum AFE settings depend on the signal levels from the resolver outputs (sine and cosine).

Observe these signals on the test points next to the J6 and J7 jumpers when configuring the AFE.

RMS

or 7 V

RMS

Setup and Operation

(1)

)

NOTE: Both gains must match to achieve better accuracy on the angle estimation.

• Read Angle button When pressed, the angle (in degrees) is displayed, if the resolver sensor is rotated and read again, the

value should update.

• BMODE0 which is the control bit for 10-bit and 12-bit modes Higher precision is achieved by changing the resolution from 10 bits to 12 bits by checking the

BMODE0 box. The new angle reading should have more digits of precision.

• Control bit for the FAULTRES pin To ignore faults, ensure that the FAULTRES pin is set to low. To set this pin low, uncheck the box.

NOTE: Toggling the FAULTRES pin with a fault condition still present causes the PGA411-Q1

device to go into normal operation, which may cause damage to the PGA411-Q1 device. This is most likely to occur with high current short circuits on the exciter amplifier.

Ignoring the faults is only recommended for initial evaluation.

(1)

This version is the latest at the time this user guide was generated.

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PGA411-Q1 EVM User's Guide

Setup and Operation

2.3.2 Device State

The Device State menu (see Figure 6) supports two device states: NORMAL and DIAGNOSTICS. This menu displays the current device state. Click on the down arrow for the dropdown menu to select a new state. This menu always displays the current device state, therefore serving as a confirmation that the device transitioned to the new state correctly.

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Figure 5. GUI PGA41x-Q1 EVM Main Screen

Figure 6. Device-State Status and Selection

NOTE: The data sheet includes a detailed description on why and how to change between these

states. Some of the controls in the PGA411-Q1 GUI interactive block diagram change states, from NORMAL to DIAGNOSTIC in a hidden manner to make the configuration changes (for example, changing the exciter sine-wave amplitude from 4 V for more details.

PGA411-Q1 EVM User's Guide

RMS

to 7 V

). See Section 2.3.4

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2.3.3 Pin Configuration and Fault Register Status

The Pin Configuration window (see Figure 7) displays the current status of the digital input and output pins. The input pins of the PGA411-Q1 device are shown in Figure 7 on the left-side (below the Update button) in the GUI, where the low or high values will be driven by the MSP430. Select the status of the nine digital-input pins by clicking on the appropriate button (INPUT-HiZ, OUT-LOW, or OUT-HIGH). The MSP430 device then switches the connected I/O pin to the selected value.

The output pins of the PGA411-Q1 device are displayed to the right of the group of input pins. This section displays the current status of the output pins with logic low equal to 0 and logic high equal to 1. For example if the FAULT pin changes to HIGH the GUI displays a 1 in the field which is then highlighted in red.

The Fault Status tab on the right-side of the Pin Configuration window displays the current status of the device registers which report any fault in the system. The following sections provide more details on the fault status registers.

The display updates each time the Update button is pressed. To automatically update this page, check the

Enable box under the Auto Update section and select an update period in 1-s increments.

Setup and Operation

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Figure 7. Pin Configuration Screen

PGA411-Q1 EVM User's Guide

+ 20 hidden pages

Texas Instruments PGA411-Q1 EVM User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual