TEXAS INSTRUMENTS PGA309 Technical data

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PROGRAMMABLE SENSOR CONDITIONER

PGA309

SBOS292A − DECEMBER 2003 − REVISED AUGUST 2004

Voltage Output

FEATURES

D COMPLETE BRIDGE SENSOR CONDITIONER
D VOLTAGE OUTPUT: Ratiometric or Absolute
D DIGITAL CAL: No Po tent io meters/ Sen so r Trims
D SENSOR ERROR COMPENSATION

− Span, Offset, and Temperature Drifts

D LOW ERROR, TIME-STABLE
D SENSOR LINEARIZATION CIRCUITRY
D TEMPERATURE SENSE: Internal or External
D CALIBRATION LOOKUP TABLE LOGIC

− Uses External EEPROM (SOT23-5)

D OVER/UNDER-SCALE LIMITING
D SENSOR FAULT DETECTION
D +2.7V TO +5.5V OPERATION
D −40°C to +125°C OPERATION
D SMALL TSSOP-16 PACKAGE

APPLICATIONS

D BRIDGE SENSORS
D REMOTE 4-20mA TRANSMITTERS
D STRAIN, LOAD, AND WEIGH SCALES
D AUTOMOTIVE SENSORS

EVALUATION TOOLS

D HARDWARE DESIGNER’S KIT (PGA309EVM)

− Temperature Eval of PGA309 + Sensor

− Full Programming of PGA309

− Sensor Compensation Analysis Tool

P

psi

0

50

No nlinear

Bridge

Transducer

DESCRIPTION

The PGA309 is a programmable a nalog s ignal c onditioner
designed for bridge sensors. The analog signal path am­plifies the sensor signal and provides digital calibration for
zero, span, zero drift, span drift, and sensor linearization
errors with a ppl ie d s tress ( pre ssure , strain, e tc.). The cal­ibration is done via a One-Wire digital serial interfac e or
through a Two-Wire industry-standard connection. The
calibration paramet ers are stored in external nonvolatile
memory (typically SOT23-5) to eliminate manual trimming
and achieve long-term st ability.

The all-analog signal path contains a 2x2 input m ultiplex­er (mux), auto-zero programmable-gain instrum entation
amplifier, linearization circuit, voltage refer ence, internal
oscillator, control logic, and an output amplifier. Program­mable level shifting compens ates for sensor DC offsets.

The core of the PGA309 is the precision, low-drift, no 1/f
noise Front-End PGA (Programmable Gain Amplifier).
The overall gain of the Front-End PGA + Output Amplifier
can be adjusted from 2.7V/V to 1152V/V. The polarity of
the inputs can be switched through the input mux to ac­commodate sens ors with unknown polarity output. The
Fault Monit or cir cuit detects and signals sens or burnout,
overload, and syst em fault condit ions .

For deta iled applic at ion infor ma tion, s ee t he PGA309
User’s Gui de (SBO U024), avai lable for dow nload at
www.ti.c om .

V

PGA309

EXC

Analog Sensor Linearization

V

S

Linearization

Circuit

Ref

Lin DAC

Fault

Monitor

+125_ C

Digital

T

−40_C

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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Ext Temp

www.ti.com

Temperature
Compensation

ExtTemp

Auto−Zero

PGA

IntTemp

Temp

ADC

Copyright  2003−2004, Texas Instruments Incorporated

Over/Under

Scale Limiter

AnalogSignalConditioning

Control Register

Interface Circuitry

Linear
V

OUT

DigitalCal

EEPROM

(SOT23−5

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SBOS292A − DECEMBER 2003 − REVISED AUGUST 2004

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(1)

−0.3V to VSA +0.3V. . . . . . . . . . . . . . . . . . . . .

(1)

TEMPERATURE

+7.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±150mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPECIFIED

RANGE

proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more
susceptible t o damage because very small parametric changes could
cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

PRODUCT PACKAGE−LEAD

PGA309 TSSOP-16 PW −40°C to +125°C PGA309

(1)

For the most current package and ordering information, refer to our web site at www.ti.com.

DRAWING

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range unless otherwise noted.

Supply Voltage, VSD, V
Input Voltage, V
Input Current, VFB, V

Input Current ±10mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Current Limit 50mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage Temperature Range −60°C to +150°C. . . . . . . . . . . . . . . . . . . . . . . .

Operating Temperature Range −55°C to +150°C. . . . . . . . . . . . . . . . . . . . . .

Junction Temperature +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead Temperature (soldering, 10s) +300°C. . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD Protection (Human Body Model) 4kV. . . . . . . . . . . . . . . . . . . . . . . . . . .

(1)

Stresses above these ratings may cause permanent damage.

IN1

, V

SD

IN2

OUT

(2)

Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only , an d
functional operation of the device at these or any other conditions
beyond those specified is not implied.

(2)

Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply
rails should be current limited to 10mA or less.

PACKAGE
MARKING

ORDERING

NUMBER

PGA309AIPWR Tape and Reel, 2500
PGA309AIPWT Tape and Reel, 250

TRANSPORT MEDIA,

QUANTITY

This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe

2

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SBOS292A − DECEMBER 2003 − REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS

BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C

TA = +25°C, VSA = VSD = +5V (VSA = V
unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS
FRONT-END PGA + OUTPUT AMPLIFIER

V

V
V
V
V
External Sensor Output Sensitivity VSA = VSD = V

FRONT-END PGA

Auto-Zero Internal Frequency 7 kHz
Offset Voltage (RTI)

Linear Input Voltage Range

Input Bias Current 0.1 1.5 nA
Input Impedance: Differential 30 || 6 GΩ || pF
Input Impedance: Common-Mode 50 || 20 GΩ || pF
Input Voltage Noise 0.1Hz to 10Hz, GF = 128 4 µV
PGA Gain

Output Voltage Range 0.05 to VSA − 0.1 V

Bandwidth Gain = 4 400 kHz

COARSE OFFSET ADJUST
(RTI OF FRONT-END PGA)

Range ±(14)(V

Resolution ±14 steps, 4-Bit + Sign 4 mV

FINE OFFSET ADJUST (ZERO DAC)
(RTO of the Front-End PGA)

Programming Range 0 V
Output Range 0.1 VSA−0.1 V
Resolution 65,536 steps, 16-Bit DAC 73 µV
Integral Nonlinearity 20 LSB
Differential Nonlinearity 0.5 LSB
Gain Error 0.1 %
Gain Error Drift 10 ppm/°C
Offset 5 mV
Offset Drift 10 µV/°C

OUTPUT FINE GAIN ADJUST (GAIN DAC)

Range 0.33 to 1 V/V
Resolution 65,536 steps, 16-Bit DAC 10 µV/V
Integral NonLinearity 20 LSB
Differential NonLinearity 0.5 LSB

Differential Signal Gain Range

OUT/VIN

Slew Rate 0.5 V/µs

OUT

Settling Time (0.01%) V

OUT

Settling Time (0.01%) V

OUT

Nonlinearity 0.002 %FSR

OUT

(2)

vs Temperature +0.2 µV/°C

vs Supply Voltage, V
vs Common-Mode Voltage GF = Front-End PGA Gain 1500/GF6000/G

Gain Range Steps 4, 8, 16, 23.27, 32, 42.67, 64, 128 4 to 128 V/V
Initial Gain Error GF = 4 to 42 0.2 ±1 %

vs Temperature 10 ppm/°C

vs Temperature 0.004 %/°C

SA

SUPPLY ANALOG

(1)

(3)

(2)

, VSD = V

SUPPLY DIGITAL

Front-End PGA Gains: 4, 8, 16, 23.27, 32, 42.67, 64, 128

Output Amplifier Gains: 2, 2.4, 3, 3.6, 4.5, 6, 9

OUT/VIN

OUT/VIN

Fine Gain Adjust = 1

Differential Gain = 8, RL = 5kΩ || 200pF 6 µs

Differential Gain = 191, RL = 5kΩ || 200pF 4.1 µs

Coarse Offset Adjust Disabled ±3 ±50 µV

; VSA must equal VSD), GNDD = GNDA = 0, and V

= +5V 1 to 245 mV/V

EXC

GF = 64 0.25 ±1.2 %

GF = 128 0.3 ±1.6 %

Gain = 128 60 kHz

)(0.00085) ±56 ±59.5 ±64 mV

REF

= REFIN/REF

REF

PGA309

8 to 1152 V/V

±2 µV/V

0.2 VSA−1.5 V

REF

OUT

µV/V

F

= +5V ,

PP

V

3

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ELECTRICAL CHARACTERISTICS (continued)

BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C

TA = +25°C, VSA = VSD = +5V (VSA = V
unless otherwise noted.

PARAMETER UNITSMAXTYPMINCONDITIONS
OUTPUT AMPLIFIER

Offset Voltage (RTI of Output Amplifier)

vs Temperature 5 µV/°C

vs Supply Voltage, V

Common-Mode Input Range 0 VSA−1.5 V

Input Bias Current 100 pA
Amplifier Internal Gain

Gain Range Steps 2, 2.4, 3, 3.6, 4.5, 6, 9 2 to 9 V/V
Initial Gain Error 2, 2.4, 3.6 0.25 ±1 %

vs Temperature 2, 2.4, 3.6 5 ppm/°C

Output Voltage Range

Open Loop Gain 115 dB
Gain-Bandwidth Product 2 MHz
Phase Margin Gain = 2, CL = 200pF 45 Degrees
Output Resistance AC Small-Signal, Open-Loop, f = 1MHz, IO = 0 675 Ω

OVER- AND UNDER-SCALE LIMITS (V
Over-Scale Thresholds Ratio of V

Over-Scale Comparator Offset +6 +60 +114 mV
Over-Scale Comparator Offset Drift +0.37 mV/°C
Under-Scale Thresholds Ratio of V

Under-Scale Comparator Offset −7 −50 +93 mV
Under-Scale Comparator Offset Drift −0.15 mV/°C

FAULT MONITOR CIRCUIT

INP_HI, INN_HI Comparator Threshold See Note 5 VSA−1.2 or V
INP_LO, INN_LO Comparator Threshold 40 100 mV
A1SAT_HI, A2SAT_HI Comparator Threshold VSA−0.12 V
A1SAT_LO, A2SAT_LO Comparator Threshold VSA−0.12 V
A3_VCM Comparator Threshold VSA−1.2 V
Comparator Hysteresis 20 mV

SA

(4)

SUPPLY ANALOG

(2)

, VSD = V

Ratio of V
Ratio of V
Ratio of V
Ratio of V
Ratio of V
Ratio of V

Ratio of V
Ratio of V
Ratio of V
Ratio of V
Ratio of V
Ratio of V
Ratio of V

SUPPLY DIGITAL

, Register 5—Bits D5, D4, D3 = ‘000’ 0.9708

REF

, Register 5—Bits D5, D4, D3 = ‘001’ 0.9610

REF

, Register 5—Bits D5, D4, D3 = ‘010’ 0.9394

REF

, Register 5—Bits D5, D4, D3 = ‘011’ 0.9160

REF

, Register 5—Bits D5, D4, D3 = ‘100’ 0.9102

REF

, Register 5—Bits D5, D4, D3 = ‘101’ 0.7324

REF

, Register 5—Bits D5, D4, D3 = ‘110’ 0.5528

REF

, Register 5—Bits D2, D1, D0 = ‘111’ 0.0605

REF

, Register 5—Bits D2, D1, D0 = ‘110’ 0.0547

REF

, Register 5—Bits D2, D1, D0 = ‘101’ 0.0507

REF

, Register 5—Bits D2, D1, D0 = ‘100’ 0.0449

REF

, Register 5—Bits D2, D1, D0 = ‘011’ 0.0391

REF

, Register 5—Bits D2, D1, D0 = ‘010’ 0.0352

REF

, Register 5—Bits D2, D1, D0 = ‘001’ 0.0293

REF

, Register 5—Bits D2, D1, D0 = ‘000’ 0.0254

REF

; VSA must equal VSD), GNDD = GNDA = 0, and V

4.5 0.3 ±1.2 %
6 0.4 ±1.5 %
9 0.6 ±2.0 %

4.5 5 ppm/°C
6 15 ppm/°C
9 30 ppm/°C

RL = 10kΩ 0.1 4.9 V

= 4.096)

REF

= REFIN/REF

REF

PGA309

3 mV

30 µV/V

−0.1 V

EXC

OUT

= +5V ,

4

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SBOS292A − DECEMBER 2003 − REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (continued)

BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C

TA = +25°C, VSA = VSD = +5V (VSA = V
unless otherwise noted.

SUPPLY ANALOG

PARAMETER UNITSMAXTYPMINCONDITIONS
INTERNAL VOLTAGE REFERENCE

V

REF1

V

Drift vs Temperature +10 ppm/°C

REF1

V

REF2

V

Drift vs Temperature +10 ppm/°C

REF2

Input Current REFIN/REF
Output Current REFIN/REF

OUT

OUT

TEMPERATURE SENSE CIRCUITRY (ADC)

Internal Temperature Measurement Register 6, Bit D9 = 1

Accuracy ±2 °C
Resolution 12-Bit + Sign, Two’s Complement Data Format ±0.0625 °C
Temperature Measurement Range −55 +150 °C
Conversion Rate R1, R0 = ‘11’, 12-Bi t + Sign Resolu tion 24 ms

TEMPERATURE ADC

External Temperature Mode Temp PGA + Temp ADC

Gain Range Steps G
Analog Input Voltage Range GND−0.2 VSA+0.2 V

Temperature ADC Internal REF (2.048V) Register 6, Bit D8 = 1

Full-Scale Input Voltage (+Input) − (−Input) ±2.048/G
Differential Input Impedance 2.8/G
Common-Mode Input Impedance G

Resolution R1, R0 = ‘00’, ADC2X = ‘0’, Conversion Time = 8ms 11 Bits + Sign

Integral Nonlinearity 0.004 %
Offset Error G

Offset Drift G

Offset vs V

SA

Gain Error 0.05 0.50 %
Gain Error Drift 5 50 ppm/°C
Noise All Gains < 1 LSB
Gain vs V
Common-Mode Rejection At DC and G

SA

, VSD = V

SUPPLY DIGITAL

; VSA must equal VSD), GNDD = GNDA = 0, and V

= REFIN/REF

REF

OUT

PGA309

Register 3, Bit D9 = 1 2.46 2.5 2.53 V

Register 3, Bit D9 = 0 4.0 4.096 4.14 V

Internal V

VSA > 2.7V for V

VSA > 4.3V for V

Disabled 100 µA

REF

= 2.5V 1 mA

REF

= 4.096V 1 mA

REF

= 1, 2, 4, 8 1 to 8 V/V

PGA

PGA

= 1 3.5 MΩ

PGA

G

= 2 3.5 MΩ

PGA

G

= 4 1.8 MΩ

PGA

G

= 8 0.9 MΩ

PGA

PGA

MΩ

R1, R0 = ‘01’, ADC2X = ‘0’, Conversion Time = 32ms 13 Bits + Sign
R1, R0 = ‘10’, ADC2X = ‘0’, Conversion Time = 64ms 14 Bits + Sign

R1, R0 = ‘11’, ADC2X = ‘0’, Conversion Time = 128ms 15 Bits + Sign

= 1 1.2 mV

PGA

G

= 2 0.7 mV

PGA

G

= 4 0.5 mV

PGA

G

= 8 0.4 mV

PGA

= 1 1.2 µV/°C

PGA

G

= 2 0.6 µV/°C

PGA

G

= 4 0.3 µV/°C

PGA

G

= 8 0.3 µV/°C

PGA

G

= 1 800 µV/V

PGA

G

= 2 400 µV/V

PGA

G

= 4 200 µV/V

PGA

G

= 8 150 µV/V

PGA

80 ppm/V

= 8 105 dB

At DC and G

PGA

= 1 100 dB

PGA

= +5V ,

V

5

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SBOS292A − DECEMBER 2003 − REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS (continued)

BOLDFACE limits apply over the specified temperature range: TA = −40°C to +125°C

TA = +25°C, VSA = VSD = +5V (VSA = V
unless otherwise noted.

SUPPLY ANALOG

PARAMETER UNITSMAXTYPMINCONDITIONS
TEMPERATURE ADC (CONTINUED)

Temp ADC Ext. REF (V

Full-Scale Input Voltage (+Input) − (−Input) ±V

REFT

= V

REF

, V

, or VSA) Register 6, Bit D8 = 0

EXC

Differential Input Impedance 2.4/G
Common-Mode Input Impedance G

Resolution R1, R0 = ‘00’, ADC2X = ‘0’, Conversion Time = 6ms 11 Bits + Sign

Integral Nonlinearity 0.01 %
Offset Error G

Offset Drift G

Gain Error −0.2 %
Gain Error Drift 2 ppm/°C
Gain vs V
Common-Mode Rejection At DC and G

External Temperature Current Excitation I

Current Excitation 5.8 7 8 µA

SA

TEMP

Temperature Drift 5 nA/°C
Voltage Compliance VSA−1.2 V

LINEARIZATION ADJUST AND EXCITATION VOLTAGE (V

Range 0 Register 3, Bit D11 = 0

Linearization DAC Range With Respect to V
Linearization DAC Resolution ±127 Steps, 7-Bit + Sign 1.307 mV/V
V

Gain With Respect to V

EXC

Gain Error Drift 25 ppm/°C

Range 1 Register 3, Bit D11 = 1

Linearization DAC Range With Respect to V
Linearization DAC Resolution ±127 Steps, 7-Bit + Sign 0.9764 mV/V
V

Gain With Respect to V

EXC

Gain Error Drift 25 ppm/°C

V

Range Upper Limit I

EXC

I

EXC SHORT

DIGITAL INTERFACE

Two-Wire Compatible Bus Speed 1 400 kHz
One-Wire Serial Speed Baud Rate 4.8K 38.4K Bits/s
Maximum Lookup Table Size

(6)

Two-Wire Data Rate PGA309 to EEPROM (SCL frequency) 65 kHz

LOGIC LEVELS

Input Levels (SDA, SCL, PRG, TEST) Low 0.2 • V

(SDA, SCL, PRG, TEST) High 0.7 • V

(SDA, SCL) Hysteresis 0.1 • V
Pull-Up Current Source (SDA, SCL) 55 85 125 µA
Pull-Down Current Source (TEST) 15 25 40 µA
Output LOW Level (SDA, SCL, PRG) Open Drain, I

, VSD = V

SUPPLY DIGITAL

; VSA must equal VSD), GNDD = GNDA = 0, and V

= REFIN/REF

REF

OUT

PGA309

REFT/GPGA

= 1 8 MΩ

PGA

G

= 2 8 MΩ

PGA

G

= 4 8 MΩ

PGA

G

= 8 8 MΩ

PGA

PGA

R1, R0 = ‘01’, ADC2X = ‘0’, Conversion Time = 24ms 13 Bits + S ign
R1, R0 = ‘10’, ADC2X = ‘0’, Conversion Time = 50ms 14 Bits + S ign

R1, R0 = ‘11’, ADC2X = ‘0’, Conversion Time = 100ms 15 Bits + Sign

= 1 2.5 mV

PGA

G

= 2 1.25 mV

PGA

G

= 4 0.7 mV

PGA

G

= 8 0.3 mV

PGA

= 1 1.5 µV/°C

PGA

G

= 2 1.0 µV/°C

PGA

G

= 4 0.7 µV/°C

PGA

G

= 8 0.6 µV/°C

PGA

80 ppm/V

= 8 100 dB

At DC and G

PGA

= 1 85 dB

PGA

Register 6, Bit D11 = 1

)

EXC

−0.166 to +0.166 V/V

0.83 V/V

−0.124 to +0.124 V/V

0.52 V/V

Short-Circuit V

EXC

FB

REF

FB

REF

= 5mA VSA − 0.5 V

Output Current 50 mA

EXC

17 x 3 x 16 Bits

SD

SD

SD

= 5mA 0.4 V

SINK

= +5V ,

V

MΩ

V
V
V

6